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add _sync_debug wires

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This commit is contained in:
Zack Buhman 2024-08-14 22:03:25 -05:00
parent df26b1c578
commit 07a460e0f0
4 changed files with 45 additions and 27 deletions
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3
vga.ccf
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@ -71,3 +71,6 @@ Net "blue[3]" Loc = "IO_WB_A6";
Net "blue[2]" Loc = "IO_WB_B6";
Net "blue[1]" Loc = "IO_WB_A7";
Net "blue[0]" Loc = "IO_WB_B7";
Net "h_sync_debug" Loc = "IO_EB_A8";
Net "v_sync_debug" Loc = "IO_EB_A0";

23
vga_fb.v
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@ -4,8 +4,8 @@ module vga_fb
output reg [3:0] red,
output reg [3:0] green,
output reg [3:0] blue,
output reg h_sync,
output reg v_sync);
output h_sync,
output v_sync);
wire [9:0] h_count;
@ -24,23 +24,12 @@ module vga_fb
.display(display));
always @(posedge clk) begin
h_sync <= h_sync1;
v_sync <= v_sync1;
h_sync <= !h_sync1;
v_sync <= !v_sync1;
if (display) begin
if (h_count == 0 && v_count == 0) begin
red <= 4'd15;
green <= 4'd15;
blue <= 4'd15;
end else if (v_count[3]) begin
red <= 4'd15;
green <= 4'd15;
blue <= 4'd0;
end else begin
red <= 4'd15;
green <= 4'd0;
blue <= 4'd0;
end
red <= v_count[8:5];
blue <= h_count[8:5];
end else begin
red <= 4'd0;
green <= 4'd0;

20
vga_spg.v
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@ -12,6 +12,12 @@ module vga_spg
localparam h_frontporch = 16;
localparam h_syncpulse = 96;
localparam h_backporch = 48;
/*
localparam h_visible = 800;
localparam h_frontporch = 40;
localparam h_syncpulse = 128;
localparam h_backporch = 88;
*/
localparam h_period = h_visible +
h_frontporch +
h_syncpulse +
@ -21,6 +27,12 @@ module vga_spg
localparam v_frontporch = 10;
localparam v_syncpulse = 2;
localparam v_backporch = 33;
/*
localparam v_visible = 600;
localparam v_frontporch = 1;
localparam v_syncpulse = 4;
localparam v_backporch = 23;
*/
localparam v_period = v_visible +
v_backporch +
v_syncpulse +
@ -32,9 +44,9 @@ module vga_spg
// h_count
always @(posedge clk) begin
if (rst) begin
h_count <= 10'd0;
h_count <= 11'd0;
end else if (h_count_h_period) begin
h_count <= 10'd0;
h_count <= 11'd0;
end else begin
h_count <= h_count + 1;
end
@ -74,6 +86,8 @@ module vga_spg
end
// display
assign display = h_count < h_visible && v_count < v_visible;
always @(posedge clk) begin
display <= h_count < h_visible && v_count < v_visible;
end
endmodule

26
vga_top.v
View File

@ -8,7 +8,9 @@ module vga_top
output reg [3:0] green,
output reg [3:0] blue,
output wire h_sync,
output wire v_sync
output wire v_sync,
output wire h_sync_debug,
output wire v_sync_debug
);
reg [26:0] counter;
@ -17,8 +19,8 @@ module vga_top
wire usr_pll_lock_stdy, usr_pll_lock;
CC_PLL #(
.REF_CLK(10.0), // reference input in MHz
.OUT_CLK(25.175), // pll output frequency in MHz
.REF_CLK("10.0"), // reference input in MHz
.OUT_CLK("25.175"), // pll output frequency in MHz
.PERF_MD("SPEED"), // LOWPOWER, ECONOMY, SPEED
.LOW_JITTER(1), // 0: disable, 1: enable low jitter mode
.CI_FILTER_CONST(2), // optional CI filter constant
@ -40,12 +42,22 @@ module vga_top
end
end
vga_fb fb(.clk(clk),
.rst(rst),
wire h_sync1;
wire v_sync1;
assign v_sync = v_sync1;
assign h_sync = h_sync1;
assign v_sync_debug = v_sync1;
assign h_sync_debug = h_sync1;
vga_fb fb(.clk(clk0),
.rst(!rst),
.red(red),
.green(green),
.blue(blue),
.h_sync(h_sync),
.v_sync(v_sync));
.h_sync(h_sync1),
.v_sync(v_sync1));
endmodule