Zack Buhman a498132c0a add ram

2024-08-15 03:14:44 -05:00

bin

initial

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log

initial

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net

initial

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.gitignore

improve test bench

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build.sh

add ram

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gen_vga_mem.py

add ram

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parrot.data

add ram

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parrot.png

add ram

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test.sh

add ram

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vga_fb.v

add ram

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vga_mem.v

add ram

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vga_ram.hex

add ram

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vga_spg.v

add ram

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vga_tb.v

add ram

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vga_top.v

add _sync_debug wires

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vga.ccf

add _sync_debug wires

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Description

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776 KiB

Languages

Verilog 88.9%

Shell 5.8%

Python 5.3%