From 07a460e0f021dc073981c2091fac4c2474dbea78 Mon Sep 17 00:00:00 2001
From: Zack Buhman <zack@buhman.org>
Date: Wed, 14 Aug 2024 22:03:25 -0500
Subject: [PATCH] add _sync_debug wires

---
 vga.ccf   |  3 +++
 vga_fb.v  | 23 ++++++-----------------
 vga_spg.v | 20 +++++++++++++++++---
 vga_top.v | 26 +++++++++++++++++++-------
 4 files changed, 45 insertions(+), 27 deletions(-)

diff --git a/vga.ccf b/vga.ccf
index b20b5c6..0d622f7 100644
--- a/vga.ccf
+++ b/vga.ccf
@@ -71,3 +71,6 @@ Net   "blue[3]" Loc = "IO_WB_A6";
 Net   "blue[2]" Loc = "IO_WB_B6";
 Net   "blue[1]" Loc = "IO_WB_A7";
 Net   "blue[0]" Loc = "IO_WB_B7";
+
+Net   "h_sync_debug" Loc = "IO_EB_A8";
+Net   "v_sync_debug" Loc = "IO_EB_A0";
\ No newline at end of file
diff --git a/vga_fb.v b/vga_fb.v
index 45cfb94..3bcdbcc 100644
--- a/vga_fb.v
+++ b/vga_fb.v
@@ -4,8 +4,8 @@ module vga_fb
    output reg [3:0] red,
    output reg [3:0] green,
    output reg [3:0] blue,
-   output reg	    h_sync,
-   output reg	    v_sync);
+   output 	    h_sync,
+   output 	    v_sync);
 
 
    wire [9:0] h_count;
@@ -24,23 +24,12 @@ module vga_fb
 	       .display(display));
 
    always @(posedge clk) begin
-      h_sync <= h_sync1;
-      v_sync <= v_sync1;
+      h_sync <= !h_sync1;
+      v_sync <= !v_sync1;
 
       if (display) begin
-	 if (h_count == 0 && v_count == 0) begin
-	    red <= 4'd15;
-	    green <= 4'd15;
-	    blue <= 4'd15;
-	 end else if (v_count[3]) begin
-	    red <= 4'd15;
-	    green <= 4'd15;
-	    blue <= 4'd0;
-         end else begin
-	    red <= 4'd15;
-	    green <= 4'd0;
-	    blue <= 4'd0;
-         end
+         red <= v_count[8:5];
+         blue <= h_count[8:5];
       end else begin
 	 red <= 4'd0;
 	 green <= 4'd0;
diff --git a/vga_spg.v b/vga_spg.v
index b02069f..cbdd9b4 100644
--- a/vga_spg.v
+++ b/vga_spg.v
@@ -12,6 +12,12 @@ module vga_spg
    localparam h_frontporch  = 16;
    localparam h_syncpulse   = 96;
    localparam h_backporch   = 48;
+    /*
+   localparam h_visible     = 800;
+   localparam h_frontporch  = 40;
+   localparam h_syncpulse   = 128;
+   localparam h_backporch   = 88;
+     */
    localparam h_period      = h_visible +
                               h_frontporch +
                               h_syncpulse +
@@ -21,6 +27,12 @@ module vga_spg
    localparam v_frontporch  = 10;
    localparam v_syncpulse   = 2;
    localparam v_backporch   = 33;
+   /*
+   localparam v_visible     = 600;
+   localparam v_frontporch  = 1;
+   localparam v_syncpulse   = 4;
+   localparam v_backporch   = 23;
+    */
    localparam v_period      = v_visible +
                               v_backporch +
                               v_syncpulse +
@@ -32,9 +44,9 @@ module vga_spg
    // h_count
    always @(posedge clk) begin
       if (rst) begin
-	 h_count <= 10'd0;
+	 h_count <= 11'd0;
       end else if (h_count_h_period) begin
-	 h_count <= 10'd0;
+	 h_count <= 11'd0;
       end else begin
 	 h_count <= h_count + 1;
       end
@@ -74,6 +86,8 @@ module vga_spg
    end
 
    // display
-   assign display = h_count < h_visible && v_count < v_visible;
+   always @(posedge clk) begin
+      display <= h_count < h_visible && v_count < v_visible;
+   end
 
 endmodule
diff --git a/vga_top.v b/vga_top.v
index bd23207..9937c30 100644
--- a/vga_top.v
+++ b/vga_top.v
@@ -8,7 +8,9 @@ module vga_top
    output reg [3:0] green,
    output reg [3:0] blue,
    output wire h_sync,
-   output wire v_sync
+   output wire v_sync,
+   output wire h_sync_debug,
+   output wire v_sync_debug
    );
 
    reg [26:0]		 counter;
@@ -17,8 +19,8 @@ module vga_top
    wire			 usr_pll_lock_stdy, usr_pll_lock;
 
    CC_PLL #(
-	    .REF_CLK(10.0),      // reference input in MHz
-	    .OUT_CLK(25.175),     // pll output frequency in MHz
+	    .REF_CLK("10.0"),      // reference input in MHz
+	    .OUT_CLK("25.175"),     // pll output frequency in MHz
 	    .PERF_MD("SPEED"), // LOWPOWER, ECONOMY, SPEED
 	    .LOW_JITTER(1),      // 0: disable, 1: enable low jitter mode
 	    .CI_FILTER_CONST(2), // optional CI filter constant
@@ -40,12 +42,22 @@ module vga_top
 	end
      end
 
-   vga_fb fb(.clk(clk),
-	     .rst(rst),
+
+   wire h_sync1;
+   wire v_sync1;
+
+   assign v_sync = v_sync1;
+   assign h_sync = h_sync1;
+
+   assign v_sync_debug = v_sync1;
+   assign h_sync_debug = h_sync1;
+
+   vga_fb fb(.clk(clk0),
+	     .rst(!rst),
 	     .red(red),
 	     .green(green),
 	     .blue(blue),
-	     .h_sync(h_sync),
-	     .v_sync(v_sync));
+	     .h_sync(h_sync1),
+	     .v_sync(v_sync1));
 
 endmodule