41 lines
753 B
Verilog
41 lines
753 B
Verilog
module vga_fb
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(input wire clk,
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input wire rst,
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output reg [3:0] red,
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output reg [3:0] green,
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output reg [3:0] blue,
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output h_sync,
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output v_sync);
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wire [9:0] h_count;
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wire [9:0] v_count;
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wire display;
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wire h_sync1;
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wire v_sync1;
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vga_spg spg(.clk(clk),
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.rst(rst),
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.h_count(h_count),
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.v_count(v_count),
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.h_sync(h_sync1),
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.v_sync(v_sync1),
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.display(display));
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always @(posedge clk) begin
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h_sync <= !h_sync1;
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v_sync <= !v_sync1;
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if (display) begin
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red <= v_count[8:5];
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blue <= h_count[8:5];
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end else begin
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red <= 4'd0;
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green <= 4'd0;
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blue <= 4'd0;
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end
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end
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endmodule
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