94 lines
2.2 KiB
Verilog
94 lines
2.2 KiB
Verilog
module vga_spg
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(input wire clk,
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input wire rst,
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output reg [9:0] h_count,
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output reg [9:0] v_count,
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output reg h_sync,
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output reg v_sync,
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output wire display
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);
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localparam h_visible = 640;
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localparam h_frontporch = 16;
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localparam h_syncpulse = 96;
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localparam h_backporch = 48;
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/*
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localparam h_visible = 800;
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localparam h_frontporch = 40;
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localparam h_syncpulse = 128;
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localparam h_backporch = 88;
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*/
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localparam h_period = h_visible +
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h_frontporch +
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h_syncpulse +
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h_backporch;
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localparam v_visible = 480;
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localparam v_frontporch = 10;
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localparam v_syncpulse = 2;
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localparam v_backporch = 33;
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/*
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localparam v_visible = 600;
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localparam v_frontporch = 1;
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localparam v_syncpulse = 4;
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localparam v_backporch = 23;
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*/
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localparam v_period = v_visible +
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v_backporch +
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v_syncpulse +
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v_frontporch;
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wire h_count_h_period;
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assign h_count_h_period = h_count == h_period - 1;
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// h_count
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always @(posedge clk) begin
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if (rst) begin
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h_count <= 11'd0;
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end else if (h_count_h_period) begin
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h_count <= 11'd0;
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end else begin
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h_count <= h_count + 1;
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end
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end
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// h_sync
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always @(posedge clk) begin
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if (h_count == h_visible + h_frontporch - 1) begin
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h_sync <= 1;
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end else if (h_count == h_visible + h_frontporch + h_syncpulse - 1) begin
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h_sync <= 0;
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end
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end
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// v_count
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always @(posedge clk) begin
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if (rst) begin
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v_count <= 10'd0;
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end else if (h_count_h_period) begin
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if (v_count == v_period - 1) begin
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v_count <= 10'd0;
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end else begin
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v_count <= v_count + 1;
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end
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end
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end
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// v_sync
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always @(posedge clk) begin
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if (h_count_h_period) begin
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if (v_count == v_visible + v_frontporch - 1) begin
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v_sync <= 1;
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end else if (v_count == v_visible + v_frontporch + v_syncpulse - 1) begin
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v_sync <= 0;
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end
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end
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end
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// display
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always @(posedge clk) begin
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display <= h_count < h_visible && v_count < v_visible;
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end
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endmodule
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