syntax.txt: initial

sh4: fix manual typos for SH2 instructions
These changes fix logical consistency and correctness issues with the instruction definitions as printed in the manual. The most serious issues were: - div0u/div0s/div1 use `m` as a temporary variable which contradicts the existence of the `m` register number - missing semicolons - inconsistent references to immediate and displacement variable names
2024-04-21 13:16:14 +08:00 · 2024-04-21 13:16:14 +08:00 · 2024-04-21 13:09:45 +08:00
51 changed files with 202 additions and 75 deletions
--- a/sh4/ADD
+++ b/sh4/ADD
@ -1,5 +1,5 @@
 0111nnnniiiiiiii
-imm ← SignExtend8(s);
+imm ← SignExtend8(i);
 op2 ← SignExtend32(Rn);
 op2 ← op2 + imm;
 Rn ← Register(op2);
--- a/sh4/ADDV
+++ b/sh4/ADDV
@ -2,6 +2,6 @@
 op1 ← SignExtend32(Rm);
 op2 ← SignExtend32(Rn);
 op2 ← op2 + op1;
-t ← INT ((op2 < (- 231)) OR (op2 ≥ 231));
+t ← INT ((op2 < (- (1 << 31))) OR (op2 ≥ (1 << 31)));
 Rn ← Register(op2);
 T ← Bit(t);
--- a/sh4/BF
+++ b/sh4/BF
@ -3,7 +3,7 @@ t ← ZeroExtend1(T);
 pc ← SignExtend32(PC);
 newpc ← SignExtend32(PC’);
 delayedpc ← SignExtend32(PC’’);
-label ← SignExtend8(s) << 1;
+label ← SignExtend8(d) << 1;
 IF (IsDelaySlot())
 THROW ILLSLOT;
 IF (t = 0)
--- a/sh4/BF_S
+++ b/sh4/BF_S
@ -2,7 +2,7 @@
 t ← ZeroExtend1(T);
 pc ← SignExtend32(PC);
 delayedpc ← SignExtend32(PC’’);
-label ← SignExtend8(s) << 1;
+label ← SignExtend8(d) << 1;
 IF (IsDelaySlot())
 THROW ILLSLOT;
 IF (t = 0)
--- a/sh4/BRA
+++ b/sh4/BRA
@ -1,6 +1,6 @@
 1010dddddddddddd
 pc ← SignExtend32(PC);
-label ← SignExtend12(s) << 1;
+label ← SignExtend12(d) << 1;
 IF (IsDelaySlot())
 THROW ILLSLOT;
 temp ← ZeroExtend32(pc + 4 + label);
--- a/sh4/BSR
+++ b/sh4/BSR
@ -1,6 +1,6 @@
 1011dddddddddddd
 pc ← SignExtend32(PC);
-label ← SignExtend12(s) << 1;
+label ← SignExtend12(d) << 1;
 IF (IsDelaySlot())
 THROW ILLSLOT;
 delayedpr ← pc + 4;
--- a/sh4/BT
+++ b/sh4/BT
@ -3,7 +3,7 @@ t ← ZeroExtend1(T);
 pc ← SignExtend32(PC);
 newpc ← SignExtend32(PC’);
 delayedpc ← SignExtend32(PC’’);
-label ← SignExtend8(s) << 1;
+label ← SignExtend8(d) << 1;
 IF (IsDelaySlot())
 THROW ILLSLOT;
 IF (t = 1)
--- a/sh4/BT_S
+++ b/sh4/BT_S
@ -2,7 +2,7 @@
 t ← ZeroExtend1(T);
 pc ← SignExtend32(PC);
 delayedpc ← SignExtend32(PC’’);
-label ← SignExtend8(s) << 1;
+label ← SignExtend8(d) << 1;
 IF (IsDelaySlot())
 THROW ILLSLOT;
 IF (t = 1)
--- a/sh4/CMP_EQ
+++ b/sh4/CMP_EQ
@ -1,5 +1,5 @@
 10001000iiiiiiii
 r0 ← SignExtend32(R0);
-imm ← SignExtend8(s);
+imm ← SignExtend8(i);
 t ← INT (r0 = imm);
 T ← Bit(t);
--- a/sh4/DIV0S
+++ b/sh4/DIV0S
@ -2,8 +2,8 @@
 op1 ← SignExtend32(Rm);
 op2 ← SignExtend32(Rn);
 q ← op2< 31 FOR 1 >;
-m ← op1< 31 FOR 1 >;
-t ← m ⊕ q;
+_m ← op1< 31 FOR 1 >;
+t ← _m ⊕ q;
 Q ← Bit(q);
-M ← Bit(m);
+M ← Bit(_m);
 T ← Bit(t);
--- a/sh4/DIV0U
+++ b/sh4/DIV0U
@ -1,7 +1,7 @@
 0000000000011001
 q ← 0;
-m ← 0;
+_m ← 0;
 t ← 0;
 Q ← Bit(q);
-M ← Bit(m);
+M ← Bit(_m);
 T ← Bit(t);
--- a/sh4/DIV1
+++ b/sh4/DIV1
@ -1,18 +1,18 @@
 0011nnnnmmmm0100
 q ← ZeroExtend1(Q);
-m ← ZeroExtend1(M);
+_m ← ZeroExtend1(M);
 t ← ZeroExtend1(T);
 op1 ← ZeroExtend32(SignExtend32(Rm));
 op2 ← ZeroExtend32(SignExtend32(Rn));
 oldq ← q;
 q ← op2< 31 FOR 1 >;
 op2 ← ZeroExtend32(op2 << 1) ∨ t;
-IF (oldq = m)
+IF (oldq = _m)
 op2 ← op2 - op1;
 ELSE
 op2 ← op2 + op1;
-q ← (q ⊕ m) ⊕ op2< 32 FOR 1 >;
-t ← 1 - (q ⊕ m);
+q ← (q ⊕ _m) ⊕ op2< 32 FOR 1 >;
+t ← 1 - (q ⊕ _m);
 Rn ← Register(op2);
 Q ← Bit(q);
 T ← Bit(t);
--- a/sh4/FSCHG
+++ b/sh4/FSCHG
@ -1,10 +1,10 @@
 1111001111111101
 Available only when PR=0
 sr ← ZeroExtend32(SR);
-sz ← ZeroExtend1(SR.SZ);
+sz ← ZeroExtend1(FPSCR.SZ);
 IF (FpuIsDisabled(sr) AND IsDelaySlot())
 THROW SLOTFPUDIS;
 IF (FpuIsDisabled(sr))
 THROW FPUDIS;
 sz ← sz ⊕ 1;
-SR.SZ ← Bit(sz);
+FPSCR.SZ ← Bit(sz);
--- a/sh4/LDS
+++ b/sh4/LDS
@ -5,8 +5,4 @@ IF (FpuIsDisabled(sr) AND IsDelaySlot())
 THROW SLOTFPUDIS;
 IF (FpuIsDisabled(sr))
 THROW FPUDIS;
-fps, pr, sz, fr ← UnpackFPSCR(op1);
-FPSCR ← ZeroExtend32(fps);
-SR.PR ← Bit(pr);
-SR.SZ ← Bit(sz);
-SR.FR ← Bit(fr);
+FPSCR ← ZeroExtend32(op1);
--- a/sh4/LDS.L
+++ b/sh4/LDS.L
@ -7,10 +7,6 @@ IF (FpuIsDisabled(sr))
 THROW FPUDIS;
 address ← ZeroExtend32(op1);
 value ← ReadMemory32(address);
-fps, pr, sz, fr ← UnpackFPSCR(value);
 op1 ← op1 + 4;
 Rm ← Register(op1);
-FPSCR ← ZeroExtend32(fps);
-SR.PR ← Bit(pr);
-SR.SZ ← Bit(sz);
-SR.FR ← Bit(fr);
+FPSCR ← ZeroExtend32(value);
--- a/sh4/LDTLB
+++ b/sh4/LDTLB
@ -2,13 +2,13 @@
 md ← ZeroExtend1(MD);
 IF (md = 0)
 THROW RESINST;
-UTLB[MMUCR.URC].ASID ← PTEH.ASID
-UTLB[MMUCR.URC].VPN ← PTEH.VPN
-UTLB[MMUCR.URC].PPN ← PTEH.PPN
-UTLB[MMUCR.URC].SZ ← PTEL.SZ1<<1 + PTEL.SZ0
-UTLB[MMUCR.URC].SH ← PTEL.SH
-UTLB[MMUCR.URC].PR ← PTEL.PR
-UTLB[MMUCR.URC].WT ← PTEL.WT
-UTLB[MMUCR.URC].C ← PTEL.C
-UTLB[MMUCR.URC].D ← PTEL.D
-UTLB[MMUCR.URC].V ← PTEL.V
+UTLB[MMUCR.URC].ASID ← PTEH.ASID;
+UTLB[MMUCR.URC].VPN ← PTEH.VPN;
+UTLB[MMUCR.URC].PPN ← PTEH.PPN;
+UTLB[MMUCR.URC].SZ ← PTEL.SZ1<<1 + PTEL.SZ0;
+UTLB[MMUCR.URC].SH ← PTEL.SH;
+UTLB[MMUCR.URC].PR ← PTEL.PR;
+UTLB[MMUCR.URC].WT ← PTEL.WT;
+UTLB[MMUCR.URC].C ← PTEL.C;
+UTLB[MMUCR.URC].D ← PTEL.D;
+UTLB[MMUCR.URC].V ← PTEL.V;
--- a/sh4/MAC.L
+++ b/sh4/MAC.L
@ -21,9 +21,10 @@ result ← mac + mul;
 IF (s = 1)
 IF (((result ⊕ mac) ∧ (result ⊕ mul))< 63 FOR 1 > = 1)
 IF (mac< 63 FOR 1 > = 0)
-result ← 247 - 1;
+result ← (1 << 47) - 1;
+ELSE
+result ← - (1 << 47);
 ELSE
-ELSEresult ← - 247;
 result ← SignedSaturate48(result);
 macl ← result;
 mach ← result >> 32;
--- a/sh4/MAC.W
+++ b/sh4/MAC.W
@ -16,6 +16,7 @@ n_address ← n_address + 2;
 value1 ← SignExtend16(ReadMemory16(ZeroExtend32(m_address)));
 m_address ← m_address + 2;
 mul ← value2 × value1;
+result ← 0;
 IF (s = 1)
 {
 macl ← SignExtend32(macl) + mul;
@ -23,7 +24,7 @@ temp ← SignedSaturate32(macl);
 IF (macl = temp)
 result ← (mach << 32) ∨ ZeroExtend32(macl);
 ELSE
-result ← (0x1 << 32) ∨ ZeroExtend32(temp);
+result ← (1 << 32) ∨ ZeroExtend32(temp);
 }
 ELSE
 result ← ((mach << 32) + macl) + mul;
--- a/sh4/MOV
+++ b/sh4/MOV
@ -1,4 +1,4 @@
 1110nnnniiiiiiii
-imm ← SignExtend8(s);
+imm ← SignExtend8(i);
 op2 ← imm;
 Rn ← Register(op2);
--- a/sh4/MOV.B
+++ b/sh4/MOV.B
@ -1,6 +1,6 @@
 11000100dddddddd
 gbr ← SignExtend32(GBR);
-disp ← ZeroExtend8(i);
+disp ← ZeroExtend8(d);
 address ← ZeroExtend32(disp + gbr);
 r0 ← SignExtend8(ReadMemory8(address));
 R0 ← Register(r0);
--- a/sh4/MOV.B
+++ b/sh4/MOV.B
@ -1,5 +1,5 @@
 10000100mmmmdddd
-disp ← ZeroExtend4(i);
+disp ← ZeroExtend4(d);
 op2 ← SignExtend32(Rm);
 address ← ZeroExtend32(disp + op2);
 r0 ← SignExtend8(ReadMemory8(address));
--- a/sh4/MOV.B
+++ b/sh4/MOV.B
@ -1,6 +1,6 @@
 11000000dddddddd
 gbr ← SignExtend32(GBR);
 r0 ← SignExtend32(R0);
-disp ← ZeroExtend8(i);
+disp ← ZeroExtend8(d);
 address ← ZeroExtend32(disp + gbr);
 WriteMemory8(address, r0);
--- a/sh4/MOV.B
+++ b/sh4/MOV.B
@ -1,6 +1,6 @@
 10000000nnnndddd
 r0 ← SignExtend32(R0);
-disp ← ZeroExtend4(i);
+disp ← ZeroExtend4(d);
 op2 ← SignExtend32(Rn);
 address ← ZeroExtend32(disp + op2);
 WriteMemory8(address, r0);
--- a/sh4/MOV.L
+++ b/sh4/MOV.L
@ -1,6 +1,6 @@
 11000110dddddddd
 gbr ← SignExtend32(GBR);
-disp ← ZeroExtend8(i) << 2;
+disp ← ZeroExtend8(d) << 2;
 address ← ZeroExtend32(disp + gbr);
 r0 ← SignExtend32(ReadMemory32(address));
 R0 ← Register(r0);
--- a/sh4/MOV.L
+++ b/sh4/MOV.L
@ -1,6 +1,6 @@
 1101nnnndddddddd
 pc ← SignExtend32(PC);
-disp ← ZeroExtend8(i) << 2;
+disp ← ZeroExtend8(d) << 2;
 IF (IsDelaySlot())
 THROW ILLSLOT;
 address ← ZeroExtend32(disp + ((pc + 4) ∧ (~ 0x3)));
--- a/sh4/MOV.L
+++ b/sh4/MOV.L
@ -1,5 +1,5 @@
 0101nnnnmmmmdddd
-disp ← ZeroExtend4(i) << 2;
+disp ← ZeroExtend4(d) << 2;
 op2 ← SignExtend32(Rm);
 address ← ZeroExtend32(disp + op2);
 op3 ← SignExtend32(ReadMemory32(address));
--- a/sh4/MOV.L
+++ b/sh4/MOV.L
@ -1,6 +1,6 @@
 11000010dddddddd
 gbr ← SignExtend32(GBR);
 r0 ← SignExtend32(R0);
-disp ← ZeroExtend8(i) << 2;
+disp ← ZeroExtend8(d) << 2;
 address ← ZeroExtend32(disp + gbr);
 WriteMemory32(address, r0);
--- a/sh4/MOV.L
+++ b/sh4/MOV.L
@ -1,6 +1,6 @@
 0001nnnnmmmmdddd
 op1 ← SignExtend32(Rm);
-disp ← ZeroExtend4(i) << 2;
+disp ← ZeroExtend4(d) << 2;
 op3 ← SignExtend32(Rn);
 address ← ZeroExtend32(disp + op3);
 WriteMemory32(address, op1);
--- a/sh4/MOV.W
+++ b/sh4/MOV.W
@ -1,6 +1,6 @@
 11000101dddddddd
 gbr ← SignExtend32(GBR);
-disp ← ZeroExtend8(i) << 1;
+disp ← ZeroExtend8(d) << 1;
 address ← ZeroExtend32(disp + gbr);
 r0 ← SignExtend16(ReadMemory16(address));
 R0 ← Register(r0);
--- a/sh4/MOV.W
+++ b/sh4/MOV.W
@ -1,6 +1,6 @@
 1001nnnndddddddd
 pc ← SignExtend32(PC);
-disp ← ZeroExtend8(i) << 1;
+disp ← ZeroExtend8(d) << 1;
 IF (IsDelaySlot())
 THROW ILLSLOT;
 address ← ZeroExtend32(disp + (pc + 4));
--- a/sh4/MOV.W
+++ b/sh4/MOV.W
@ -1,5 +1,5 @@
 10000101mmmmdddd
-disp ← ZeroExtend4(i) << 1;
+disp ← ZeroExtend4(d) << 1;
 op2 ← SignExtend32(Rm);
 address ← ZeroExtend32(disp + op2);
 r0 ← SignExtend16(ReadMemory16(address));
--- a/sh4/MOV.W
+++ b/sh4/MOV.W
@ -1,6 +1,6 @@
 11000001dddddddd
 gbr ← SignExtend32(GBR);
 r0 ← SignExtend32(R0);
-disp ← ZeroExtend8(i) << 1;
+disp ← ZeroExtend8(d) << 1;
 address ← ZeroExtend32(disp + gbr);
 WriteMemory16(address, r0);
--- a/sh4/MOV.W
+++ b/sh4/MOV.W
@ -1,6 +1,6 @@
 10000001nnnndddd
 r0 ← SignExtend32(R0);
-disp ← ZeroExtend4(i) << 1;
+disp ← ZeroExtend4(d) << 1;
 op2 ← SignExtend32(Rn);
 address ← ZeroExtend32(disp + op2);
 WriteMemory16(address, r0);
--- a/sh4/MOVA
+++ b/sh4/MOVA
@ -1,6 +1,6 @@
 11000111dddddddd
 pc ← SignExtend32(PC);
-disp ← ZeroExtend8(i) << 2;
+disp ← ZeroExtend8(d) << 2;
 IF (IsDelaySlot())
 THROW ILLSLOT;
 r0 ← disp + ((pc + 4) ∧ (~ 0x3));
--- a/sh4/MOVCA.L
+++ b/sh4/MOVCA.L
@ -8,7 +8,7 @@ THROW WTLBMISS, op1;
 IF (MMU() AND WriteProhibited(op1))
 THROW WRITEPROT, op1;
 IF (MMU() AND NOT DirtyBit(op1))
-THROW FIRSTWRITE, op1
+THROW FIRSTWRITE, op1;
 ALLOCO(op1);
 address ← ZeroExtend32(op1);
 WriteMemory32(op1, r0);
--- a/sh4/NOP
+++ b/sh4/NOP
@ -1,2 +1,2 @@
 0000000000001001
-NOP
+NOP;
--- a/sh4/OCBI
+++ b/sh4/OCBI
@ -7,5 +7,5 @@ THROW WTLBMISS, op1;
 IF (MMU() AND WriteProhibited(op1))
 THROW WRITEPROT, op1;
 IF (MMU() AND NOT DirtyBit(op1))
-THROW FIRSTWRITE, op1
+THROW FIRSTWRITE, op1;
 OCBI(op1);
--- a/sh4/PREF
+++ b/sh4/PREF
@ -1,7 +1,7 @@
 0000nnnn10000011
 op1 ← SignExtend32(Rn);
 IF (AddressUnavailable(op1))
-THROW RADDERR, op1
+THROW RADDERR, op1;
 IF (NOT (MMU() AND DataAccessMiss(op1)))
 IF (NOT (MMU() AND ReadProhibited(op1)))
 PREF(op1);
--- a/sh4/RTE
+++ b/sh4/RTE
@ -3,7 +3,7 @@ md ← ZeroExtend1(MD);
 IF (md = 0)
 THROW RESINST;
 ssr ← SignExtend32(SSR);
-pc ← SignExtend32(PC)
+pc ← SignExtend32(PC);
 IF (IsDelaySlot())
 THROW ILLSLOT;
 target ← pc;
--- a/sh4/SLEEP
+++ b/sh4/SLEEP
@ -2,4 +2,4 @@
 md ← ZeroExtend1(MD);
 IF (md = 0)
 THROW RESINST;
-SLEEP()
+SLEEP();
--- a/sh4/STC
+++ b/sh4/STC
@ -3,5 +3,5 @@ md ← ZeroExtend1(MD);
 IF (md = 0)
 THROW RESINST;
 dbr ← SignExtend32(DBR);
-op1 ← dbr
+op1 ← dbr;
 Rn ← Register(op1);
--- a/sh4/STC
+++ b/sh4/STC
@ -3,5 +3,5 @@ md ← ZeroExtend1(MD);
 IF (md = 0)
 THROW RESINST;
 sgr ← SignExtend32(SGR);
-op1 ← sgr
+op1 ← sgr;
 Rn ← Register(op1);
--- a/sh4/STC
+++ b/sh4/STC
@ -3,5 +3,5 @@ md ← ZeroExtend1(MD);
 IF (md = 0)
 THROW RESINST;
 spc ← SignExtend32(SPC);
-op1 ← spc
+op1 ← spc;
 Rn ← Register(op1);
--- a/sh4/STC
+++ b/sh4/STC
@ -3,5 +3,5 @@ md ← ZeroExtend1(MD);
 IF (md = 0)
 THROW RESINST;
 sr ← SignExtend32(SR);
-op1 ← sr
+op1 ← sr;
 Rn ← Register(op1);
--- a/sh4/STC
+++ b/sh4/STC
@ -3,5 +3,5 @@ md ← ZeroExtend1(MD);
 IF (md = 0)
 THROW RESINST;
 ssr ← SignExtend32(SSR);
-op1 ← ssr
+op1 ← ssr;
 Rn ← Register(op1);
--- a/sh4/STC
+++ b/sh4/STC
@ -3,5 +3,5 @@ md ← ZeroExtend1(MD);
 IF (md = 0)
 THROW RESINST;
 vbr ← SignExtend32(VBR);
-op1 ← vbr
+op1 ← vbr;
 Rn ← Register(op1);
--- a/sh4/SUBV
+++ b/sh4/SUBV
@ -2,6 +2,6 @@
 op1 ← SignExtend32(Rm);
 op2 ← SignExtend32(Rn);
 op2 ← op2 - op1;
-t ← INT ((op2 < (- 231)) OR (op2 ≥ 231));
+t ← INT ((op2 < (- (1 << 31))) OR (op2 ≥ (1 << 31)));
 Rn ← Register(op2);
 T ← Bit(t);
--- a/sh4/TAS.B
+++ b/sh4/TAS.B
@ -1,7 +1,7 @@
 0100nnnn00011011
 op1 ← SignExtend32(Rn);
 address ← ZeroExtend32(op1);
-OCBP(address)
+OCBP(address);
 value ← ZeroExtend8(ReadMemory8(address));
 t ← INT (value = 0);
 value ← value ∨ (1 << 7);
--- a/syntax.txt
+++ b/syntax.txt
@ -0,0 +1,133 @@
+identifier:
+	identifier-start
+	identifier identifier-continue
+
+identifier-start:
+	nondigit
+
+identifier-contine:
+	digit
+	nondigit
+
+primary-expression:
+	identifier
+	constant
+	"(" expression ")"
+
+postfix-expression:
+	primary-expression
+	postfix-expression "[" expression "]"
+	postfix-expression "(" argument-expression-list? ")"
+	postfix-expression "<" for-expression ">"
+	postfix-expression "." identifier
+
+for-expression:
+	primary-expression
+	primary-expression "FOR" primary-expression
+
+argument-expression-list:
+	assignment-expression
+	argument-expression-list "," assignment-expression
+
+unary-expression:
+	postfix-expression
+	"NOT" unary-expression
+	"INT" unary-expression
+	"~" unary-expression	 # bitwise complement
+	"-" unary-expression	 # integer negation
+	"|" unary-expression "|" # integer absolute value
+
+multiplicative-expression:
+	unary-expression
+	multiplicative-expression "×" unary-expression
+	multiplicative-expression "/" unary-expression
+
+additive-expression:
+	multiplicative-expression
+	additive-expression "+" multiplicative-expression
+	additive-expression "-" multiplicative-expression
+
+shift-expression:
+	additive-expression
+	shift-expression "<<" additive-expression
+	shift-expression ">>" additive-expression
+
+relational-expression:
+	shift-expression
+	relational-expression "<" shift-expression
+	relational-expression ">" shift-expression
+	relational-expression "≤" shift-expression
+	relational-expression "≥" shift-expression
+
+equality-expression:
+	relational-expression
+	equality-expression "=" relational-expression
+	equality-expression "≠" relational-expression
+
+bitwise-AND-expression:
+	equality-expression
+	bitwise-AND-expression "∧" equality-expression
+
+bitwise-XOR-expression:
+	bitwise-AND-expression
+	bitwise-XOR-expression "⊕" bitwise-AND-expression
+
+bitwise-OR-expression:
+	bitwise-XOR-expression
+	bitwise-OR-expression "∨" bitwise-XOR-expression
+
+logical-AND-expression:
+	bitwise-OR-expression
+	logical-AND-expression "AND" bitwise-OR-expression
+
+logical-XOR-expression:
+	logical-AND-expression
+	logical-XOR-expression "XOR" logical-AND-expression
+
+logical-OR-expression:
+	logical-XOR-expression
+	logical-OR-expression "OR" logical-XOR-expression
+
+assignment-expression:
+	logical-OR-expression
+	unary-expression "←" assignment-expression
+
+expression:
+	assignment-expression
+
+# statement
+
+statement:
+	unlabeled-statement
+
+unlabeled-statement:
+	expression-statement
+	primary-block
+
+primary-block:
+	compound-statement
+	selection-statement
+	throw-statement
+
+secondary-block:
+	statement
+
+compound-statement:
+	"{" block-item-list? "}"
+
+block-item-list:
+	block-item
+	block-item-list block-item
+
+block-item:
+	unlabeled-statement
+
+expression-statement:
+	expression ";"
+
+selection-statement:
+	"IF" "(" expression ")" secondary-block
+	"IF" "(" expression ")" secondary-block "ELSE" secondary-block
+
+throw-statement:
+	"THROW" secondary-block