sh4: add descriptions for all instructions

python/instruction_table.py

@@ -158,10 +158,13 @@ def parse_variables(operands):
     for token in parse_tokens(operands):
         yield from get_variable(token)
 
-
 def parse_instruction(*, instruction, operands, code, operation, **kwargs):
     code = parse_code(code)
-    variables = tuple(parse_variables(operands))
+    try:
+        variables = tuple(parse_variables(operands))
+    except:
+        print(instruction)
+        raise
 
     return (
         instruction,
@@ -233,3 +236,19 @@ def untabulate_instructions_sh4():
     ]))
 
     return untabulate_instructions(os.path.join(directory, "sh4.txt"), columns)
+
+l = untabulate_instructions_sh4()
+from pprint import pprint
+for ins in list(l):
+    if ins.operands:
+        fn = ' '.join([ins.instruction, ins.operands])
+    else:
+        fn = ins.instruction
+    fn = fn.replace('/', '_')
+    code = list(f'{ins.code.code_bits:016b}')
+    for operand in ins.code.operands.values():
+        for i in range(operand.lsb, operand.lsb + operand.length):
+            code[15 - i] = operand.operand
+
+    with open(os.path.join(directory, "sh4", fn), 'w') as f:
+        f.write(''.join(code) + '\n')

sh4.txt

@@ -250,5 +250,7 @@ FTRV    XMTRX,FVn       transform_vector [XMTRX, FVn] → FVn
 FRCHG                   ~FPSCR.FR → SPFCR.FR                                    1111101111111101        —           —
 FSCHG                   ~FPSCR.SZ → SPFCR.SZ                                    1111001111111101        —           —
 
-FCSA    FPUL, DRn       sin(FPUL) → FRn ; cos(FPUL) → FR[n+1]                   1111nnn011111101        —           —
+FCSA    FPUL,DRn        sin(FPUL) → FRn ; cos(FPUL) → FR[n+1]                   1111nnn011111101        —           —
 FSRRA   FRn             1/√FRn → FRn                                            1111nnnn01111101        —           —
+
+BRK                     BREAK                                                   0000000000111011        —           —

sh4/ADD #imm,Rn

@@ -0,0 +1,5 @@
+0111nnnniiiiiiii
+imm ← SignExtend8(s);
+op2 ← SignExtend32(Rn);
+op2 ← op2 + imm;
+Rn ← Register(op2);

sh4/ADD Rm,Rn

@@ -0,0 +1,5 @@
+0011nnnnmmmm1100
+op1 ← SignExtend32(Rm);
+op2 ← SignExtend32(Rn);
+op2 ← op2 + op1;
+Rn ← Register(op2);

sh4/ADDC Rm,Rn

@@ -0,0 +1,8 @@
+0011nnnnmmmm1110
+t ← ZeroExtend1(T);
+op1 ← ZeroExtend32(SignExtend32(Rm));
+op2 ← ZeroExtend32(SignExtend32(Rn));
+op2 ← (op2 + op1) + t;
+t ← op2< 32 FOR 1 >;
+Rn ← Register(op2);
+T ← Bit(t);

sh4/ADDV Rm,Rn

@@ -0,0 +1,7 @@
+0011nnnnmmmm1111
+op1 ← SignExtend32(Rm);
+op2 ← SignExtend32(Rn);
+op2 ← op2 + op1;
+t ← INT ((op2 < (- 231)) OR (op2 ≥ 231));
+Rn ← Register(op2);
+T ← Bit(t);

sh4/AND #imm,R0

@@ -0,0 +1,5 @@
+11001001iiiiiiii
+r0 ← ZeroExtend32(R0);
+imm ← ZeroExtend8(i);
+r0 ← r0 ∧ imm;
+R0 ← Register(r0);

sh4/AND Rm,Rn

@@ -0,0 +1,5 @@
+0010nnnnmmmm1001
+op1 ← ZeroExtend32(Rm);
+op2 ← ZeroExtend32(Rn);
+op2 ← op2 ∧ op1;
+Rn ← Register(op2);

sh4/AND.B #imm,@(R0,GBR)

@@ -0,0 +1,8 @@
+11001101iiiiiiii
+r0 ← SignExtend32(R0);
+gbr ← SignExtend32(GBR);
+imm ← ZeroExtend8(i);
+address ← ZeroExtend32(r0 + gbr);
+value ← ZeroExtend8(ReadMemory8(address));
+value ← value ∧ imm;
+WriteMemory8(address, value);

sh4/BF label

@@ -0,0 +1,16 @@
+10001011dddddddd
+t ← ZeroExtend1(T);
+pc ← SignExtend32(PC);
+newpc ← SignExtend32(PC’);
+delayedpc ← SignExtend32(PC’’);
+label ← SignExtend8(s) << 1;
+IF (IsDelaySlot())
+THROW ILLSLOT;
+IF (t = 0)
+{
+temp ← ZeroExtend32(pc + 4 + label);
+newpc ← temp;
+delayedpc ← temp + 2;
+}
+PC’ ← Register(newpc);
+PC’’ ← Register(delayedpc);

sh4/BF_S label

@@ -0,0 +1,13 @@
+10001111dddddddd
+t ← ZeroExtend1(T);
+pc ← SignExtend32(PC);
+delayedpc ← SignExtend32(PC’’);
+label ← SignExtend8(s) << 1;
+IF (IsDelaySlot())
+THROW ILLSLOT;
+IF (t = 0)
+{
+temp ← ZeroExtend32(pc + 4 + label);
+delayedpc ← temp;
+}
+PC’’ ← Register(delayedpc);

sh4/BRA label

@@ -0,0 +1,8 @@
+1010dddddddddddd
+pc ← SignExtend32(PC);
+label ← SignExtend12(s) << 1;
+IF (IsDelaySlot())
+THROW ILLSLOT;
+temp ← ZeroExtend32(pc + 4 + label);
+delayedpc ← temp;
+PC’’ ← Register(delayedpc);

sh4/BRAF Rn

@@ -0,0 +1,8 @@
+0000nnnn00100011
+pc ← SignExtend32(PC);
+op1 ← SignExtend32(Rn);
+IF (IsDelaySlot())
+THROW ILLSLOT;
+target ← ZeroExtend32(pc + 4 + op1);
+delayedpc ← target ∧ (~ 0x1);
+PC’’ ← Register(delayedpc);

sh4/BRK

@@ -0,0 +1,2 @@
+0000000000111011
+THROW BREAK;

sh4/BSR label

@@ -0,0 +1,10 @@
+1011dddddddddddd
+pc ← SignExtend32(PC);
+label ← SignExtend12(s) << 1;
+IF (IsDelaySlot())
+THROW ILLSLOT;
+delayedpr ← pc + 4;
+temp ← ZeroExtend32(pc + 4 + label);
+delayedpc ← temp;
+PR’’ ← Register(delayedpr);
+PC’’ ← Register(delayedpc);

sh4/BSRF Rn

@@ -0,0 +1,10 @@
+0000nnnn00000011
+pc ← SignExtend32(PC);
+op1 ← SignExtend32(Rn);
+IF (IsDelaySlot())
+THROW ILLSLOT;
+delayedpr ← pc + 4;
+target ← ZeroExtend32(pc + 4 + op1);
+delayedpc ← target ∧ (~ 0x1);
+PR’’ ← Register(delayedpr);
+PC’’ ← Register(delayedpc);

sh4/BT label

@@ -0,0 +1,16 @@
+10001001dddddddd
+t ← ZeroExtend1(T);
+pc ← SignExtend32(PC);
+newpc ← SignExtend32(PC’);
+delayedpc ← SignExtend32(PC’’);
+label ← SignExtend8(s) << 1;
+IF (IsDelaySlot())
+THROW ILLSLOT;
+IF (t = 1)
+{
+temp ← ZeroExtend32(pc + 4 + label);
+newpc ← temp;
+delayedpc ← temp + 2;
+}
+PC’ ← Register(newpc);
+PC’’ ← Register(delayedpc);

sh4/BT_S label

@@ -0,0 +1,13 @@
+10001101dddddddd
+t ← ZeroExtend1(T);
+pc ← SignExtend32(PC);
+delayedpc ← SignExtend32(PC’’);
+label ← SignExtend8(s) << 1;
+IF (IsDelaySlot())
+THROW ILLSLOT;
+IF (t = 1)
+{
+temp ← ZeroExtend32(pc + 4 + label);
+delayedpc ← temp;
+}
+PC’’ ← Register(delayedpc);

sh4/CLRMAC

@@ -0,0 +1,5 @@
+0000000000101000
+macl ← 0;
+mach ← 0;
+MACL ← ZeroExtend32(macl);
+MACH ← ZeroExtend32(mach);

sh4/CLRS

@@ -0,0 +1,3 @@
+0000000001001000
+s ← 0;
+S ← Bit(s);

sh4/CLRT

@@ -0,0 +1,3 @@
+0000000000001000
+t ← 0;
+T ← Bit(t);

sh4/CMP_EQ #imm,R0

@@ -0,0 +1,5 @@
+10001000iiiiiiii
+r0 ← SignExtend32(R0);
+imm ← SignExtend8(s);
+t ← INT (r0 = imm);
+T ← Bit(t);

sh4/CMP_EQ Rm,Rn

@@ -0,0 +1,5 @@
+0011nnnnmmmm0000
+op1 ← SignExtend32(Rm);
+op2 ← SignExtend32(Rn);
+t ← INT (op2 = op1);
+T ← Bit(t);

sh4/CMP_GE Rm,Rn

@@ -0,0 +1,5 @@
+0011nnnnmmmm0011
+op1 ← SignExtend32(Rm);
+op2 ← SignExtend32(Rn);
+t ← INT (op2 ≥ op1);
+T ← Bit(t);

sh4/CMP_GT Rm,Rn

@@ -0,0 +1,5 @@
+0011nnnnmmmm0111
+op1 ← SignExtend32(Rm);
+op2 ← SignExtend32(Rn);
+t ← INT (op2 > op1);
+T ← Bit(t);

sh4/CMP_HI Rm,Rn

@@ -0,0 +1,5 @@
+0011nnnnmmmm0110
+op1 ← ZeroExtend32(SignExtend32(Rm));
+op2 ← ZeroExtend32(SignExtend32(Rn));
+t ← INT (op2 > op1);
+T ← Bit(t);

sh4/CMP_HS Rm,Rn

@@ -0,0 +1,5 @@
+0011nnnnmmmm0010
+op1 ← ZeroExtend32(SignExtend32(Rm));
+op2 ← ZeroExtend32(SignExtend32(Rn));
+t ← INT (op2 ≥ op1);
+T ← Bit(t);

sh4/CMP_PL Rn

@@ -0,0 +1,4 @@
+0100nnnn00010101
+op1 ← SignExtend32(Rn);
+t ← INT (op1 > 0);
+T ← Bit(t);

sh4/CMP_PZ Rn

@@ -0,0 +1,4 @@
+0100nnnn00010001
+op1 ← SignExtend32(Rn);
+t ← INT (op1 ≥ 0);
+T ← Bit(t);

sh4/CMP_STR Rm,Rn

@@ -0,0 +1,9 @@
+0010nnnnmmmm1100
+op1 ← SignExtend32(Rm);
+op2 ← SignExtend32(Rn);
+temp ← op1 ⊕ op2;
+t ← INT (temp< 0 FOR 8 > = 0);
+t ← (INT (temp< 8 FOR 8 > = 0)) ∨ t;
+t ← (INT (temp< 16 FOR 8 > = 0)) ∨ t;
+t ← (INT (temp< 24 FOR 8 > = 0)) ∨ t;
+T ← Bit(t);

sh4/DIV0S Rm,Rn

@@ -0,0 +1,9 @@
+0010nnnnmmmm0111
+op1 ← SignExtend32(Rm);
+op2 ← SignExtend32(Rn);
+q ← op2< 31 FOR 1 >;
+m ← op1< 31 FOR 1 >;
+t ← m ⊕ q;
+Q ← Bit(q);
+M ← Bit(m);
+T ← Bit(t);

sh4/DIV0U

@@ -0,0 +1,7 @@
+0000000000011001
+q ← 0;
+m ← 0;
+t ← 0;
+Q ← Bit(q);
+M ← Bit(m);
+T ← Bit(t);

sh4/DIV1 Rm,Rn

@@ -0,0 +1,18 @@
+0011nnnnmmmm0100
+q ← ZeroExtend1(Q);
+m ← ZeroExtend1(M);
+t ← ZeroExtend1(T);
+op1 ← ZeroExtend32(SignExtend32(Rm));
+op2 ← ZeroExtend32(SignExtend32(Rn));
+oldq ← q;
+q ← op2< 31 FOR 1 >;
+op2 ← ZeroExtend32(op2 << 1) ∨ t;
+IF (oldq = m)
+op2 ← op2 - op1;
+ELSE
+op2 ← op2 + op1;
+q ← (q ⊕ m) ⊕ op2< 32 FOR 1 >;
+t ← 1 - (q ⊕ m);
+Rn ← Register(op2);
+Q ← Bit(q);
+T ← Bit(t);

sh4/DMULS.L Rm,Rn

@@ -0,0 +1,8 @@
+0011nnnnmmmm1101
+op1 ← SignExtend32(Rm);
+op2 ← SignExtend32(Rn);
+mac ← op2 × op1;
+macl ← mac;
+mach ← mac >> 32;
+MACL ← ZeroExtend32(macl);
+MACH ← ZeroExtend32(mach);

sh4/DMULU.L Rm,Rn

@@ -0,0 +1,8 @@
+0011nnnnmmmm0101
+op1 ← ZeroExtend32(SignExtend32(Rm));
+op2 ← ZeroExtend32(SignExtend32(Rn));
+mac ← op2 × op1;
+macl ← mac;
+mach ← mac >> 32;
+MACL ← ZeroExtend32(macl);
+MACH ← ZeroExtend32(mach);

sh4/DT Rn

@@ -0,0 +1,6 @@
+0100nnnn00010000
+op1 ← SignExtend32(Rn);
+op1 ← op1 - 1;
+t ← INT (op1 = 0);
+Rn ← Register(op1);
+T ← Bit(t);

sh4/EXTS.B Rm,Rn

@@ -0,0 +1,4 @@
+0110nnnnmmmm1110
+op1 ← SignExtend8(Rm);
+op2 ← op1;
+Rn ← Register(op2);

sh4/EXTS.W Rm,Rn

@@ -0,0 +1,4 @@
+0110nnnnmmmm1111
+op1 ← SignExtend16(Rm);
+op2 ← op1;
+Rn ← Register(op2);

sh4/EXTU.B Rm,Rn

@@ -0,0 +1,4 @@
+0110nnnnmmmm1100
+op1 ← ZeroExtend8(Rm);
+op2 ← op1;
+Rn ← Register(op2);

sh4/EXTU.W Rm,Rn

@@ -0,0 +1,4 @@
+0110nnnnmmmm1101
+op1 ← ZeroExtend16(Rm);
+op2 ← op1;
+Rn ← Register(op2);

sh4/FABS DRn

@@ -0,0 +1,10 @@
+1111nnn001011101
+Available only when PR=1 and SZ=0
+sr ← ZeroExtend32(SR);
+op1 ← FloatValue64(DR2n);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+op1 ← FABS_D(op1);
+DR2n ← FloatRegister64(op1);

sh4/FABS FRn

@@ -0,0 +1,10 @@
+1111nnnn01011101
+Available only when PR=0
+sr ← ZeroExtend32(SR);
+op1 ← FloatValue32(FRn);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+op1 ← FABS_S(op1);
+FRn ← FloatRegister32(op1);

sh4/FADD DRm,DRn

@@ -0,0 +1,19 @@
+1111nnn0mmm00000
+Available only when PR=1 and SZ=0
+sr ← ZeroExtend32(SR);
+fps ← ZeroExtend32(FPSCR);
+op1 ← FloatValue64(DR2m);
+op2 ← FloatValue64(DR2n);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+op2, fps ← FADD_D(op1, op2, fps);
+IF (FpuEnableV(fps) AND FpuCauseV(fps))
+THROW FPUEXC, fps;
+IF (FpuCauseE(fps))
+THROW FPUEXC, fps;
+IF ((FpuEnableI(fps) OR FpuEnableO(fps)) OR FpuEnableU(fps))
+THROW FPUEXC, fps;
+DR2n ← FloatRegister64(op2);
+FPSCR ← ZeroExtend32(fps);

sh4/FADD FRm,FRn

@@ -0,0 +1,19 @@
+1111nnnnmmmm0000
+Available only when PR=0
+sr ← ZeroExtend32(SR);
+fps ← ZeroExtend32(FPSCR);
+op1 ← FloatValue32(FRm);
+op2 ← FloatValue32(FRn);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+op2, fps ← FADD_S(op1, op2, fps);
+IF (FpuEnableV(fps) AND FpuCauseV(fps))
+THROW FPUEXC, fps;
+IF (FpuCauseE(fps))
+THROW FPUEXC, fps;
+IF ((FpuEnableI(fps) OR FpuEnableO(fps)) OR FpuEnableU(fps))
+THROW FPUEXC, fps;
+FRn ← FloatRegister32(op2);
+FPSCR ← ZeroExtend32(fps);

sh4/FCMP_EQ DRm,DRn

@@ -0,0 +1,15 @@
+1111nnn0mmm00100
+Available only when PR=1 and SZ=0
+sr ← ZeroExtend32(SR);
+fps ← ZeroExtend32(FPSCR);
+op1 ← FloatValue64(DR2m);
+op2 ← FloatValue64(DR2n);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+t, fps ← FCMPEQ_D(op1, op2, fps);
+IF (FpuEnableV(fps) AND FpuCauseV(fps))
+THROW FPUEXC, fps;
+FPSCR ← ZeroExtend32(fps);
+T ← Bit(t);

sh4/FCMP_EQ FRm,FRn

@@ -0,0 +1,15 @@
+1111nnnnmmmm0100
+Available only when PR=0
+sr ← ZeroExtend32(SR);
+fps ← ZeroExtend32(FPSCR);
+op1 ← FloatValue32(FRm);
+op2 ← FloatValue32(FRn);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+t, fps ← FCMPEQ_S(op1, op2, fps);
+IF (FpuEnableV(fps) AND FpuCauseV(fps))
+THROW FPUEXC, fps;
+FPSCR ← ZeroExtend32(fps);
+T ← Bit(t);

sh4/FCMP_GT DRm,DRn

@@ -0,0 +1,15 @@
+1111nnn0mmm00101
+Available only when PR=1 and SZ=0
+sr ← ZeroExtend32(SR);
+fps ← ZeroExtend32(FPSCR);
+op1 ← FloatValue64(DR2m);
+op2 ← FloatValue64(DR2n);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+t, fps ← FCMPGT_D(op2, op1, fps);
+IF (FpuEnableV(fps) AND FpuCauseV(fps))
+THROW FPUEXC, fps;
+FPSCR ← ZeroExtend32(fps);
+T ← Bit(t);

sh4/FCMP_GT FRm,FRn

@@ -0,0 +1,15 @@
+1111nnnnmmmm0101
+Available only when PR=0
+sr ← ZeroExtend32(SR);
+fps ← ZeroExtend32(FPSCR);
+op1 ← FloatValue32(FRm);
+op2 ← FloatValue32(FRn);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+t, fps ← FCMPGT_S(op2, op1, fps);
+IF (FpuEnableV(fps) AND FpuCauseV(fps))
+THROW FPUEXC, fps;
+FPSCR ← ZeroExtend32(fps);
+T ← Bit(t);

sh4/FCNVDS DRm,FPUL

@@ -0,0 +1,18 @@
+1111mmm010111101
+Available only when PR=1 and SZ=0
+sr ← ZeroExtend32(SR);
+fps ← ZeroExtend32(FPSCR);
+op1 ← FloatValue64(DR2m);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+fpul, fps ← FCNV_DS(op1, fps);
+IF (FpuEnableV(fps) AND FpuCauseV(fps))
+THROW FPUEXC, fps;
+IF (FpuCauseE(fps))
+THROW FPUEXC, fps;
+IF ((FpuEnableI(fps) OR FpuEnableO(fps)) OR FpuEnableU(fps))
+THROW FPUEXC, fps;
+FPSCR ← ZeroExtend32(fps);
+FPUL ← ZeroExtend32(fpul);

sh4/FCNVSD FPUL,DRn

@@ -0,0 +1,16 @@
+1111nnn010101101
+Available only when PR=1 and SZ=0
+sr ← ZeroExtend32(SR);
+fps ← ZeroExtend32(FPSCR);
+fpul ← SignExtend32(FPUL);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+op1, fps ← FCNV_SD(fpul, fps);
+IF (FpuEnableV(fps) AND FpuCauseV(fps))
+THROW FPUEXC, fps;
+IF (FpuCauseE(fps))
+THROW FPUEXC, fps;
+DR2n ← FloatRegister64(op1);
+FPSCR ← ZeroExtend32(fps);

sh4/FCSA FPUL,DRn

@@ -0,0 +1 @@
+1111nnn011111101

sh4/FDIV DRm,DRn

@@ -0,0 +1,21 @@
+1111nnn0mmm00011
+Available only when PR=1 and SZ=0
+sr ← ZeroExtend32(SR);
+fps ← ZeroExtend32(FPSCR);
+op1 ← FloatValue64(DR2m);
+op2 ← FloatValue64(DR2n);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+op2, fps ← FDIV_D(op2, op1, fps);
+IF (FpuEnableV(fps) AND FpuCauseV(fps))
+THROW FPUEXC, fps;
+IF (FpuEnableZ(fps) AND FpuCauseZ(fps))
+THROW FPUEXC, fps;
+IF (FpuCauseE(fps))
+THROW FPUEXC, fps;
+IF ((FpuEnableI(fps) OR FpuEnableO(fps)) OR FpuEnableU(fps))
+THROW FPUEXC, fps;
+DR2n ← FloatRegister64(op2);
+FPSCR ← ZeroExtend32(fps);

sh4/FDIV FRm,FRn

@@ -0,0 +1,21 @@
+1111nnnnmmmm0011
+Available only when PR=0
+sr ← ZeroExtend32(SR);
+fps ← ZeroExtend32(FPSCR);
+op1 ← FloatValue32(FRm);
+op2 ← FloatValue32(FRn);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+op2, fps ← FDIV_S(op2, op1, fps);
+IF (FpuEnableV(fps) AND FpuCauseV(fps))
+THROW FPUEXC, fps;
+IF (FpuEnableZ(fps) AND FpuCauseZ(fps))
+THROW FPUEXC, fps;
+IF (FpuCauseE(fps))
+THROW FPUEXC, fps;
+IF ((FpuEnableI(fps) OR FpuEnableO(fps)) OR FpuEnableU(fps))
+THROW FPUEXC, fps;
+FRn ← FloatRegister32(op2);
+FPSCR ← ZeroExtend32(fps);

sh4/FIPR FVm,FVn

@@ -0,0 +1,17 @@
+1111nnmm11101101
+Available only when PR=0
+sr ← ZeroExtend32(SR);
+fps ← ZeroExtend32(FPSCR);
+op1 ← FloatValueVector32(FV4m);
+op2 ← FloatValueVector32(FV4n);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+op2[3], fps ← FIPR_S(op1, op2, fps);
+IF (FpuEnableV(fps) AND FpuCauseV(fps))
+THROW FPUEXC, fps;
+IF ((FpuEnableI(fps) OR FpuEnableO(fps)) OR FpuEnableU(fps))
+THROW FPUEXC, fps;
+FV4n ← FloatRegisterVector32(op2);
+FPSCR ← ZeroExtend32(fps);

sh4/FLDI0 FRn

@@ -0,0 +1,9 @@
+1111nnnn10001101
+Available only when PR=0
+sr ← ZeroExtend32(SR);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+op1 ← 0x00000000;
+FRn ← FloatRegister32(op1);

sh4/FLDI1 FRn

@@ -0,0 +1,9 @@
+1111nnnn10011101
+Available only when PR=0
+sr ← ZeroExtend32(SR);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+op1 ← 0x3F800000;
+FRn ← FloatRegister32(op1);

sh4/FLDS FRm,FPUL

@@ -0,0 +1,9 @@
+1111mmmm00011101
+sr ← ZeroExtend32(SR);
+op1 ← FloatValue32(FRm);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+fpul ← op1;
+FPUL ← ZeroExtend32(fpul);

sh4/FLOAT FPUL,DRn

@@ -0,0 +1,11 @@
+1111nnn000101101
+Available only when PR=1 and SZ=0
+fpul ← SignExtend32(FPUL);
+sr ← ZeroExtend32(SR);
+fps ← ZeroExtend32(FPSCR);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+op1, fps ← FLOAT_LD(fpul, fps);
+DR2n ← FloatRegister64(op1);

sh4/FLOAT FPUL,FRn

@@ -0,0 +1,14 @@
+1111nnnn00101101
+Available only when PR=0
+sr ← ZeroExtend32(SR);
+fps ← ZeroExtend32(FPSCR);
+fpul ← SignExtend32(FPUL);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+op1, fps ← FLOAT_LS(fpul, fps);
+IF (FpuEnableI(fps))
+THROW FPUEXC, fps;
+FRn ← FloatRegister32(op1);
+FPSCR ← ZeroExtend32(fps);

sh4/FMAC FR0,FRm,FRn

@@ -0,0 +1,20 @@
+1111nnnnmmmm1110
+Available only when PR=0
+sr ← ZeroExtend32(SR);
+fps ← ZeroExtend32(FPSCR);
+fr0 ← FloatValue32(FR0);
+op1 ← FloatValue32(FRm);
+op2 ← FloatValue32(FRn);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+op2, fps ← FMAC_S(fr0, op1, op2, fps);
+IF (FpuEnableV(fps) AND FpuCauseV(fps))
+THROW FPUEXC, fps;
+IF (FpuCauseE(fps))
+THROW FPUEXC, fps;
+IF ((FpuEnableI(fps) OR FpuEnableO(fps)) OR FpuEnableU(fps))
+THROW FPUEXC, fps;
+FRn ← FloatRegister32(op2);
+FPSCR ← ZeroExtend32(fps);

sh4/FMOV @(R0,Rm),DRn

@@ -0,0 +1,12 @@
+1111nnn0mmmm0110
+Available only when PR=0 and SZ=1
+sr ← ZeroExtend32(SR);
+r0 ← SignExtend32(R0);
+op1 ← SignExtend32(Rm);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+address ← ZeroExtend32(r0 + op1);
+op2 ← ReadMemoryPair32(address);
+FP2n ← FloatRegisterPair32(op2);

sh4/FMOV @(R0,Rm),XDn

@@ -0,0 +1,12 @@
+1111nnn1mmmm0110
+Available only when PR=0 and SZ=1
+sr ← ZeroExtend32(SR);
+r0 ← SignExtend32(R0);
+op1 ← SignExtend32(Rm);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+address ← ZeroExtend32(r0 + op1);
+op2 ← ReadMemoryPair32(address);
+XD2n ← FloatRegisterPair32(op2);

sh4/FMOV @Rm+,DRn

@@ -0,0 +1,14 @@
+1111nnn0mmmm1001
+Available only when PR=0 and SZ=1
+sr ← ZeroExtend32(SR);
+fps ← ZeroExtend32(FPSCR);
+op1 ← SignExtend32(Rm);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+address ← ZeroExtend32(op1);
+op2 ← ReadMemoryPair32(address);
+op1 ← op1 + 8;
+Rm ← Register(op1);
+FP2n ← FloatRegisterPair32(op2);

sh4/FMOV @Rm+,XDn

@@ -0,0 +1,14 @@
+1111nnn1mmmm1001
+Available only when PR=0 and SZ=1
+sr ← ZeroExtend32(SR);
+fps ← ZeroExtend32(FPSCR);
+op1 ← SignExtend32(Rm);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+address ← ZeroExtend32(op1);
+op2 ← ReadMemoryPair32(address);
+op1 ← op1 + 8;
+Rm ← Register(op1);
+XD2n ← FloatRegisterPair32(op2);

sh4/FMOV @Rm,DRn

@@ -0,0 +1,11 @@
+1111nnn0mmmm1000
+Available only when PR=0 and SZ=1
+sr ← ZeroExtend32(SR);
+op1 ← SignExtend32(Rm);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+address ← ZeroExtend32(op1);
+op2 ← ReadMemoryPair32(address);
+FP2n ← FloatRegisterPair32(op2);

sh4/FMOV @Rm,XDn

@@ -0,0 +1,12 @@
+1111nnn1mmmm1000
+Available only when PR=0 and SZ=1
+sr ← ZeroExtend32(SR);
+fps ← ZeroExtend32(FPSCR);
+op1 ← SignExtend32(Rm);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+address ← ZeroExtend32(op1);
+op2 ← ReadMemoryPair32(address);
+XD2n ← FloatRegisterPair32(op2);

sh4/FMOV DRm,@(R0,Rn)

@@ -0,0 +1,12 @@
+1111nnnnmmm00111
+Available only when PR=0 and SZ=1
+sr ← ZeroExtend32(SR);
+r0 ← SignExtend32(R0);
+op1 ← FloatValuePair32(FP2m);
+op2 ← SignExtend32(Rn);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+address ← ZeroExtend32(r0 + op2);
+WriteMemoryPair32(address, op1);

sh4/FMOV DRm,@-Rn

@@ -0,0 +1,14 @@
+1111nnnnmmm01011
+Available only when PR=0 and SZ=1
+sr ← ZeroExtend32(SR);
+fps ← ZeroExtend32(FPSCR);
+op1 ← FloatValuePair32(FP2m);
+op2 ← SignExtend32(Rn);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+address ← ZeroExtend32(op2 - 8);
+WriteMemoryPair32(address, op1);
+op2 ← address;
+Rn ← Register(op2);

sh4/FMOV DRm,@Rn

@@ -0,0 +1,12 @@
+1111nnnnmmm01010
+Available only when PR=0 and SZ=1
+sr ← ZeroExtend32(SR);
+fps ← ZeroExtend32(FPSCR);
+op1 ← FloatValuePair32(FP2m);
+op2 ← SignExtend32(Rn);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+address ← ZeroExtend32(op2);
+WriteMemoryPair32(address, op1);

sh4/FMOV DRm,DRn

@@ -0,0 +1,10 @@
+1111nnn0mmm01100
+Available only when PR=0 and SZ=1
+sr ← ZeroExtend32(SR);
+op1 ← FloatValuePair32(FP2m);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+op2 ← op1;
+FP2n ← FloatRegisterPair32(op2);

sh4/FMOV DRm,XDn

@@ -0,0 +1,10 @@
+1111nnn1mmm01100
+Available only when PR=0 and SZ=1
+sr ← ZeroExtend32(SR);
+op1 ← FloatValuePair32(DR2m);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+op2 ← op1;
+XD2n ← FloatRegisterPair32(op2);

sh4/FMOV FRm,FRn

@@ -0,0 +1,11 @@
+1111nnnnmmmm1100
+Available only when SZ=0
+sr ← ZeroExtend32(SR);
+fps ← ZeroExtend32(FPSCR);
+op1 ← FloatValue32(FRm);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+op2 ← op1;
+FRn ← FloatRegister32(op2);

sh4/FMOV XDm,@(R0,Rn)

@@ -0,0 +1,12 @@
+1111nnnnmmm10111
+Available only when PR=0 and SZ=1
+sr ← ZeroExtend32(SR);
+r0 ← SignExtend32(R0);
+op1 ← FloatValuePair32(XD2m);
+op2 ← SignExtend32(Rn);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+address ← ZeroExtend32(r0 + op2);
+WriteMemoryPair32(address, op1);

sh4/FMOV XDm,@-Rn

@@ -0,0 +1,15 @@
+1111nnnnmmm11011
+Available only when PR=0 and SZ=1
+sr ← ZeroExtend32(SR);
+fps ← ZeroExtend32(FPSCR);
+op1 ← FloatValuePair32(XD2m);
+op2 ← SignExtend32(Rn);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+address ← ZeroExtend32(op2 - 8);
+WriteMemoryPair32(address, op1);
+op2 ← address;
+Rn ← Register(op2);
+FPSCR ← ZeroExtend32(fps);

sh4/FMOV XDm,@Rn

@@ -0,0 +1,12 @@
+1111nnnnmmm11010
+Available only when PR=0 and SZ=1
+sr ← ZeroExtend32(SR);
+fps ← ZeroExtend32(FPSCR);
+op1 ← FloatValuePair32(XD2m);
+op2 ← SignExtend32(Rn);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+address ← ZeroExtend32(op2);
+WriteMemoryPair32(address, op1);

sh4/FMOV XDm,DRn

@@ -0,0 +1,11 @@
+1111nnn0mmm11100
+Available only when PR=0 and SZ=1
+sr ← ZeroExtend32(SR);
+fps ← ZeroExtend32(FPSCR);
+op1 ← FloatValuePair32(XD2m);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+op2 ← op1;
+DR2n ← FloatRegisterPair32(op2);

sh4/FMOV XDm,XDn

@@ -0,0 +1,11 @@
+1111nnn1mmm11100
+Available only when PR=0 and SZ=1
+sr ← ZeroExtend32(SR);
+fps ← ZeroExtend32(FPSCR);
+op1 ← FloatValue64(XD2m);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+op2 ← op1;
+XD2n ← FloatRegister64(op2);

sh4/FMOV.S @(R0,Rm),FRn

@@ -0,0 +1,12 @@
+1111nnnnmmmm0110
+Available only when SZ=0
+sr ← ZeroExtend32(SR);
+r0 ← SignExtend32(R0);
+op1 ← SignExtend32(Rm);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+address ← ZeroExtend32(r0 + op1);
+op2 ← ReadMemory32(address);
+FRn ← FloatRegister32(op2);

sh4/FMOV.S @Rm+,FRn

@@ -0,0 +1,13 @@
+1111nnnnmmmm1001
+Available only when SZ=0
+sr ← ZeroExtend32(SR);
+op1 ← SignExtend32(Rm);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+address ← ZeroExtend32(op1);
+op2 ← ReadMemory32(address);
+op1 ← op1 + 4;
+Rm ← Register(op1);
+FRn ← FloatRegister32(op2);

sh4/FMOV.S @Rm,FRn

@@ -0,0 +1,12 @@
+1111nnnnmmmm1000
+Available only when SZ=0
+sr ← ZeroExtend32(SR);
+fps ← ZeroExtend32(FPSCR);
+op1 ← SignExtend32(Rm);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+address ← ZeroExtend32(op1);
+op2 ← ReadMemory32(address);
+FR2n ← FloatRegister32(op2);

sh4/FMOV.S FRm,@(R0,Rn)

@@ -0,0 +1,12 @@
+1111nnnnmmmm0111
+Available only when SZ=0
+sr ← ZeroExtend32(SR);
+r0 ← SignExtend32(R0);
+op1 ← FloatValue32(FRm);
+op2 ← SignExtend32(Rn);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+address ← ZeroExtend32(r0 + op2);
+WriteMemory32(address, op1);

sh4/FMOV.S FRm,@-Rn

@@ -0,0 +1,14 @@
+1111nnnnmmmm1011
+Available only when SZ=0
+sr ← ZeroExtend32(SR);
+fps ← ZeroExtend32(FPSCR);
+op1 ← FloatValue32(FRm);
+op2 ← SignExtend32(Rn);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+address ← ZeroExtend32(op2 - 4);
+WriteMemory32(address, op1);
+op2 ← address;
+Rn ← Register(op2);

sh4/FMOV.S FRm,@Rn

@@ -0,0 +1,12 @@
+1111nnnnmmmm1010
+Available only when SZ=0
+sr ← ZeroExtend32(SR);
+fps ← ZeroExtend32(FPSCR);
+op1 ← FloatValue32(FRm);
+op2 ← SignExtend32(Rn);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+address ← ZeroExtend32(op2);
+WriteMemory32(address, op1);

sh4/FMUL DRm,DRn

@@ -0,0 +1,19 @@
+1111nnn0mmm00010
+Available only when PR=1 and SZ=0
+sr ← ZeroExtend32(SR);
+fps ← ZeroExtend32(FPSCR);
+op1 ← FloatValue64(DR2m);
+op2 ← FloatValue64(DR2n);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+op2, fps ← FMUL_D(op1, op2, fps);
+IF (FpuEnableV(fps) AND FpuCauseV(fps))
+THROW FPUEXC, fps;
+IF (FpuCauseE(fps))
+THROW FPUEXC, fps;
+IF ((FpuEnableI(fps) OR FpuEnableO(fps)) OR FpuEnableU(fps))
+THROW FPUEXC, fps;
+DR2n ← FloatRegister64(op2);
+FPSCR ← ZeroExtend32(fps);

sh4/FMUL FRm,FRn

@@ -0,0 +1,19 @@
+1111nnnnmmmm0010
+Available only when PR=0
+sr ← ZeroExtend32(SR);
+fps ← ZeroExtend32(FPSCR);
+op1 ← FloatValue32(FRm);
+op2 ← FloatValue32(FRn);
+IF (FpuIsDisabled(sr) AND IsDelaySlot())
+THROW SLOTFPUDIS;
+IF (FpuIsDisabled(sr))
+THROW FPUDIS;
+op2, fps ← FMUL_S(op1, op2, fps);
+IF (FpuEnableV(fps) AND FpuCauseV(fps))
+THROW FPUEXC, fps;
+IF (FpuCauseE(fps))
+THROW FPUEXC, fps;
+IF ((FpuEnableI(fps) OR FpuEnableO(fps)) OR FpuEnableU(fps))
+THROW FPUEXC, fps;
+FRn ← FloatRegister32(op2);
+FPSCR ← ZeroExtend32(fps);