module vga_spg
  (input wire  clk,
   input wire  rst,
   output reg  [9:0] h_count,
   output reg  [9:0] v_count,
   output reg  h_sync,
   output reg  v_sync,
   output wire display
   );

   localparam h_visible     = 640;
   localparam h_frontporch  = 16;
   localparam h_syncpulse   = 96;
   localparam h_backporch   = 48;
    /*
   localparam h_visible     = 800;
   localparam h_frontporch  = 40;
   localparam h_syncpulse   = 128;
   localparam h_backporch   = 88;
     */
   localparam h_period      = h_visible +
                              h_frontporch +
                              h_syncpulse +
                              h_backporch;

   localparam v_visible     = 480;
   localparam v_frontporch  = 10;
   localparam v_syncpulse   = 2;
   localparam v_backporch   = 33;
   /*
   localparam v_visible     = 600;
   localparam v_frontporch  = 1;
   localparam v_syncpulse   = 4;
   localparam v_backporch   = 23;
    */
   localparam v_period      = v_visible +
                              v_backporch +
                              v_syncpulse +
                              v_frontporch;

   wire	      h_count_h_period;
   assign h_count_h_period = h_count == h_period - 1;

   // h_count
   always @(posedge clk) begin
      if (rst) begin
	 h_count <= 11'd0;
      end else if (h_count_h_period) begin
	 h_count <= 11'd0;
      end else begin
	 h_count <= h_count + 1;
      end
   end

   // h_sync
   always @(posedge clk) begin
      if (h_count == h_visible + h_frontporch - 1) begin
	 h_sync <= 1;
      end else if (h_count == h_visible + h_frontporch + h_syncpulse - 1) begin
	 h_sync <= 0;
      end
   end

   // v_count
   always @(posedge clk) begin
      if (rst) begin
	 v_count <= 10'd0;
      end else if (h_count_h_period) begin
	 if (v_count == v_period - 1) begin
	    v_count <= 10'd0;
	 end else begin
	    v_count <= v_count + 1;
	 end
      end
   end

   // v_sync
   always @(posedge clk) begin
      if (h_count_h_period) begin
	if (v_count == v_visible + v_frontporch - 1) begin
	   v_sync <= 1;
	end else if (v_count == v_visible + v_frontporch + v_syncpulse - 1) begin
	   v_sync <= 0;
	end
      end
   end

   // display
   always @(posedge clk) begin
      display <= h_count < h_visible && v_count < v_visible;
   end

endmodule