add ram

build.sh

@@ -2,6 +2,7 @@ set -eux
 
 yosys <<EOF
 read_verilog vga_spg.v
+read_verilog vga_mem.v
 read_verilog vga_fb.v
 read_verilog vga_top.v
 synth_gatemate -top vga_top -nomx8 -vlog net/synth.v

gen_vga_mem.py

@@ -0,0 +1,17 @@
+with open('parrot.data', 'rb') as f:
+    buf = f.read()
+
+assert len(buf) == 320 * 240 * 3, len(buf)
+
+with open('vga_ram.hex', 'w') as f:
+    for i in range(320 * 240):
+        r = buf[i * 3 + 0]
+        g = buf[i * 3 + 1]
+        b = buf[i * 3 + 2]
+
+        r4 = r >> 4
+        g4 = g >> 4
+        b4 = b >> 4
+
+        f.write(f'{r4:x}{g4:x}{b4:x}')
+        f.write('\n')

test.sh

@@ -1,4 +1,4 @@
 set -eux
 
-iverilog -o bin/vga_tb vga_spg.v vga_fb.v vga_tb.v
+iverilog -o bin/vga_tb vga_spg.v vga_fb.v vga_tb.v vga_mem.v
 vvp bin/vga_tb

vga_fb.v

@@ -4,13 +4,13 @@ module vga_fb
    output reg [3:0]  red,
    output reg [3:0]  green,
    output reg [3:0]  blue,
-   output 	    h_sync,
-   output 	    v_sync);
-
-
-   wire [9:0] h_count;
-   wire [9:0] v_count;
-   wire	      display;
+   output reg	     h_sync,
+   output reg	     v_sync,
+   output wire [9:0] h_count,
+   output wire [9:0] v_count,
+   output wire	     display,
+   output reg [18:0] addr
+   );
 
    wire	      h_sync1;
    wire	      v_sync1;
@@ -23,13 +23,43 @@ module vga_fb
 	       .v_sync(v_sync1),
 	       .display(display));
 
+   //reg [18:0] addr;
+   reg	      clk2;
+
+   always @(posedge clk) begin
+      if (rst)
+	clk2 <= 1'b0;
+      else
+	clk2 <= ~clk2;
+
+      if (rst || v_sync1) begin
+	 addr <= 0;
+      end else if (display) begin
+	 if (clk2)
+	   if (addr < 76799)
+	     addr <= addr + 1;
+	   else
+	     addr <= 0;
+      end
+   end
+
+   wire read = 1'b1;
+
+   wire [11:0] rdata;
+
+   vga_mem mem(.clk(clk),
+	       .read(read),
+	       .addr(addr),
+	       .rdata(rdata));
+
    always @(posedge clk) begin
       h_sync <= !h_sync1;
       v_sync <= !v_sync1;
 
       if (display) begin
-         red <= v_count[8:5];
-         blue <= h_count[8:5];
+         red <= rdata[11:8];
+	 green <= rdata[7:4];
+         blue <= rdata[3:0];
       end else begin
 	 red <= 4'd0;
 	 green <= 4'd0;

vga_mem.v

@@ -0,0 +1,18 @@
+module vga_mem
+  (input wire        clk,
+   input wire	     read,
+   input wire [18:0] addr,
+   output reg [11:0] rdata
+   );
+
+   reg [11:0] mem [0:76799];
+
+   initial
+      $readmemh("vga_ram.hex", mem);
+
+   always @(posedge clk) begin
+      if (read) begin
+         rdata <= mem[addr];
+      end
+   end
+endmodule

vga_spg.v

@@ -5,7 +5,7 @@ module vga_spg
    output reg [9:0] v_count,
    output reg	    h_sync,
    output reg	    v_sync,
-   output wire display
+   output reg	    display
    );
 
    localparam h_visible     = 640;
@@ -86,6 +86,7 @@ module vga_spg
    end
 
    // display
+   //assign display = h_count < h_visible && v_count < v_visible;
    always @(posedge clk) begin
       display <= h_count < h_visible && v_count < v_visible;
    end

vga_tb.v

@@ -19,6 +19,10 @@ module vga_tb;
    wire [3:0] blue;
    wire	      h_sync;
    wire	      v_sync;
+   wire [9:0] h_count;
+   wire [9:0] v_count;
+   wire	      display;
+   wire [18:0] addr;
 
    vga_fb fb(clk,
 	     rst,
@@ -26,6 +30,15 @@ module vga_tb;
 	     green,
 	     blue,
 	     h_sync,
-	     v_sync);
+	     v_sync,
+	     h_count,
+	     v_count,
+	     display,
+	     addr);
+
+   always @(negedge clk) begin
+      if (!rst && display)
+	$display("%h %h %h %h %h %h", addr, h_count, v_count, red, green, blue);
+   end
 
 endmodule