19 lines
315 B
Verilog
19 lines
315 B
Verilog
module vga_mem
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(input wire clk,
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input wire read,
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input wire [18:0] addr,
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output reg [11:0] rdata
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);
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reg [11:0] mem [0:76799];
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initial
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$readmemh("vga_ram.hex", mem);
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always @(posedge clk) begin
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if (read) begin
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rdata <= mem[addr];
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end
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end
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endmodule
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