71 lines
1.3 KiB
Verilog
71 lines
1.3 KiB
Verilog
module vga_fb
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(input wire clk,
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input wire rst,
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output reg [3:0] red,
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output reg [3:0] green,
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output reg [3:0] blue,
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output reg h_sync,
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output reg v_sync,
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output wire [9:0] h_count,
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output wire [9:0] v_count,
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output wire display,
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output reg [18:0] addr
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);
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wire h_sync1;
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wire v_sync1;
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vga_spg spg(.clk(clk),
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.rst(rst),
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.h_count(h_count),
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.v_count(v_count),
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.h_sync(h_sync1),
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.v_sync(v_sync1),
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.display(display));
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//reg [18:0] addr;
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reg clk2;
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always @(posedge clk) begin
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if (rst)
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clk2 <= 1'b0;
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else
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clk2 <= ~clk2;
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if (rst || v_sync1) begin
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addr <= 0;
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end else if (display) begin
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if (clk2)
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if (addr < 76799)
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addr <= addr + 1;
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else
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addr <= 0;
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end
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end
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wire read = 1'b1;
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wire [11:0] rdata;
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vga_mem mem(.clk(clk),
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.read(read),
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.addr(addr),
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.rdata(rdata));
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always @(posedge clk) begin
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h_sync <= !h_sync1;
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v_sync <= !v_sync1;
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if (display) begin
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red <= rdata[11:8];
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green <= rdata[7:4];
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blue <= rdata[3:0];
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end else begin
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red <= 4'd0;
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green <= 4'd0;
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blue <= 4'd0;
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end
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end
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endmodule
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