32 lines
453 B
Verilog
32 lines
453 B
Verilog
module vga_tb;
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reg rst = 0;
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initial begin
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$dumpfile("test.vcd");
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$dumpvars;
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# 10 rst = 1;
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# 2 rst = 0;
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# 2800000 $finish;
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end
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reg clk = 0;
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always #1 clk = !clk;
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wire [9:0] h_count;
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wire [9:0] v_count;
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wire h_sync;
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wire v_sync;
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wire display;
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vga_spg spg(clk,
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rst,
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h_count,
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v_count,
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h_sync,
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v_sync,
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display);
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endmodule
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