module vga_tb;

   reg rst = 0;

   initial begin
      $dumpfile("test.vcd");
      $dumpvars;

      # 10 rst = 1;
      # 2 rst = 0;
      # 2800000 $finish;
   end

   reg clk = 0;
   always #1 clk = !clk;

   wire	[9:0] h_count;
   wire	[9:0] v_count;
   wire	      h_sync;
   wire	      v_sync;
   wire	      display;

   vga_spg spg(clk,
	       rst,
	       h_count,
	       v_count,
	       h_sync,
	       v_sync,
	       display);

endmodule