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Zack Buhman bc90b3d80c decode: implement PR- and SZ- instruction decode discrimination

Some SH4 floating point instructions have ambiguous encodings that
depend on FPSCR variables. Exhaustively, these are:

    FMOV XDm,DRn 	      (sz 1)
    FMOV FRm,FRn 	      (sz 0)

    FMOV DRm,@(R0,Rn) 	      (sz 1)
    FMOV.S FRm,@(R0,Rn)       (sz 0)

    FCMP/EQ DRm,DRn 	      (pr 1)
    FCMP/EQ FRm,FRn 	      (pr 0)

    FMOV @Rm+,XDn 	      (sz 1)
    FMOV.S @Rm+,FRn 	      (sz 0)

    FMOV XDm,@(R0,Rn) 	      (sz 1)
    FMOV.S FRm,@(R0,Rn)       (sz 0)

    FMUL DRm,DRn 	      (pr 1)
    FMUL FRm,FRn 	      (pr 0)

    FMOV.S @Rm+,FRn 	      (sz 0)
    FMOV @Rm+,DRn 	      (sz 1)

    FLOAT FPUL,DRn 	      (pr 1)
    FLOAT FPUL,FRn 	      (pr 0)

    FNEG DRn 		      (pr 1)
    FNEG FRn 		      (pr 0)

    FTRC DRm,FPUL 	      (pr 1)
    FTRC FRm,FPUL 	      (pr 0)

    FMOV.S @(R0,Rm),FRn       (sz 0)
    FMOV @(R0,Rm),DRn 	      (sz 1)

    FMOV.S @Rm,FRn 	      (sz 0)
    FMOV @Rm,DRn 	      (sz 1)

    FMOV XDm,XDn 	      (sz 1)
    FMOV FRm,FRn 	      (sz 0)

    FABS FRn 		      (pr 0)
    FABS DRn 		      (pr 1)

    FMOV.S FRm,@Rn 	      (sz 0)
    FMOV DRm,@Rn 	      (sz 1)

    FSUB DRm,DRn 	      (pr 1)
    FSUB FRm,FRn 	      (pr 0)

    FDIV DRm,DRn 	      (pr 1)
    FDIV FRm,FRn 	      (pr 0)

    FCMP/GT DRm,DRn 	      (pr 1)
    FCMP/GT FRm,FRn 	      (pr 0)

    FMOV DRm,DRn 	      (sz 1)
    FMOV FRm,FRn 	      (sz 0)

    FMOV.S FRm,@-Rn 	      (sz 0)
    FMOV DRm,@-Rn 	      (sz 1)

    FADD DRm,DRn 	      (pr 1)
    FADD FRm,FRn 	      (pr 0)

    FMOV.S FRm,@Rn 	      (sz 0)
    FMOV XDm,@Rn 	      (sz 1)

    FMOV.S @(R0,Rm),FRn       (sz 0)
    FMOV @(R0,Rm),XDn         (sz 1)

    FMOV DRm,XDn 	      (sz 1)
    FMOV FRm,FRn 	      (sz 0)

    FMOV XDm,@-Rn 	      (sz 1)
    FMOV.S FRm,@-Rn 	      (sz 0)

    FSQRT DRn 		      (pr 1)
    FSQRT FRn 		      (pr 0)

    FMOV.S @Rm,FRn 	      (sz 0)
    FMOV @Rm,XDn 	      (sz 1)

This commit automatically calculates which FPU instructions require
FPSCR-discrimination, and automatically inserts the appropriate
conditional logic in the instruction decoder.

2024-04-26 18:34:20 +08:00

decode: implement PR- and SZ- instruction decode discrimination

2024-04-26 18:34:20 +08:00

python

decode: implement PR- and SZ- instruction decode discrimination

2024-04-26 18:34:20 +08:00

sh4

sh4: fix FLDS/FMOV/FMOV.S/FNEG/FRCHG/FSTS documentation typos

2024-04-23 15:58:37 +08:00

tests

initial sh2 interpreter

2024-04-09 09:57:08 +08:00