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sh4: fix FLDS/FMOV/FMOV.S/FNEG/FRCHG/FSTS documentation typos

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This commit is contained in:
Zack Buhman 2024-04-23 15:58:37 +08:00
parent ea3c389944
commit 367079adbd
20 changed files with 14 additions and 25 deletions
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2
sh4/FLDS FRm,FPUL
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@ -5,5 +5,5 @@ IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;
IF (FpuIsDisabled(sr))
THROW FPUDIS;
fpul ← op1;
fpul ← FloatRegister32(op1);
FPUL ← ZeroExtend32(fpul);

1
sh4/FMOV @Rm+,DRn
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@ -1,7 +1,6 @@
1111nnn0mmmm1001
Available only when PR=0 and SZ=1
sr ← ZeroExtend32(SR);
fps ← ZeroExtend32(FPSCR);
op1 ← SignExtend32(Rm);
IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;

1
sh4/FMOV @Rm+,XDn
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@ -1,7 +1,6 @@
1111nnn1mmmm1001
Available only when PR=0 and SZ=1
sr ← ZeroExtend32(SR);
fps ← ZeroExtend32(FPSCR);
op1 ← SignExtend32(Rm);
IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;

1
sh4/FMOV @Rm,XDn
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@ -1,7 +1,6 @@
1111nnn1mmmm1000
Available only when PR=0 and SZ=1
sr ← ZeroExtend32(SR);
fps ← ZeroExtend32(FPSCR);
op1 ← SignExtend32(Rm);
IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;

1
sh4/FMOV DRm,@-Rn
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@ -1,7 +1,6 @@
1111nnnnmmm01011
Available only when PR=0 and SZ=1
sr ← ZeroExtend32(SR);
fps ← ZeroExtend32(FPSCR);
op1 ← FloatValuePair32(FP2m);
op2 ← SignExtend32(Rn);
IF (FpuIsDisabled(sr) AND IsDelaySlot())

1
sh4/FMOV DRm,@Rn
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@ -1,7 +1,6 @@
1111nnnnmmm01010
Available only when PR=0 and SZ=1
sr ← ZeroExtend32(SR);
fps ← ZeroExtend32(FPSCR);
op1 ← FloatValuePair32(FP2m);
op2 ← SignExtend32(Rn);
IF (FpuIsDisabled(sr) AND IsDelaySlot())

1
sh4/FMOV FRm,FRn
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@ -1,7 +1,6 @@
1111nnnnmmmm1100
Available only when SZ=0
sr ← ZeroExtend32(SR);
fps ← ZeroExtend32(FPSCR);
op1 ← FloatValue32(FRm);
IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;

3
sh4/FMOV XDm,@-Rn
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@ -1,7 +1,6 @@
1111nnnnmmm11011
Available only when PR=0 and SZ=1
sr ← ZeroExtend32(SR);
fps ← ZeroExtend32(FPSCR);
op1 ← FloatValuePair32(XD2m);
op2 ← SignExtend32(Rn);
IF (FpuIsDisabled(sr) AND IsDelaySlot())
@ -12,4 +11,4 @@ address ← ZeroExtend32(op2 - 8);
WriteMemoryPair32(address, op1);
op2 ← address;
Rn ← Register(op2);
FPSCR ← ZeroExtend32(fps);

1
sh4/FMOV XDm,@Rn
View File

@ -1,7 +1,6 @@
1111nnnnmmm11010
Available only when PR=0 and SZ=1
sr ← ZeroExtend32(SR);
fps ← ZeroExtend32(FPSCR);
op1 ← FloatValuePair32(XD2m);
op2 ← SignExtend32(Rn);
IF (FpuIsDisabled(sr) AND IsDelaySlot())

1
sh4/FMOV XDm,DRn
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@ -1,7 +1,6 @@
1111nnn0mmm11100
Available only when PR=0 and SZ=1
sr ← ZeroExtend32(SR);
fps ← ZeroExtend32(FPSCR);
op1 ← FloatValuePair32(XD2m);
IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;

1
sh4/FMOV XDm,XDn
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@ -1,7 +1,6 @@
1111nnn1mmm11100
Available only when PR=0 and SZ=1
sr ← ZeroExtend32(SR);
fps ← ZeroExtend32(FPSCR);
op1 ← FloatValue64(XD2m);
IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;

2
sh4/FMOV.S @(R0,Rm),FRn
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@ -8,5 +8,5 @@ THROW SLOTFPUDIS;
IF (FpuIsDisabled(sr))
THROW FPUDIS;
address ← ZeroExtend32(r0 + op1);
op2 ← ReadMemory32(address);
op2 ← FloatValue32(ReadMemory32(address));
FRn ← FloatRegister32(op2);

2
sh4/FMOV.S @Rm+,FRn
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@ -7,7 +7,7 @@ THROW SLOTFPUDIS;
IF (FpuIsDisabled(sr))
THROW FPUDIS;
address ← ZeroExtend32(op1);
op2 ← ReadMemory32(address);
op2 ← FloatValue32(ReadMemory32(address));
op1 ← op1 + 4;
Rm ← Register(op1);
FRn ← FloatRegister32(op2);

3
sh4/FMOV.S @Rm,FRn
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@ -1,12 +1,11 @@
1111nnnnmmmm1000
Available only when SZ=0
sr ← ZeroExtend32(SR);
fps ← ZeroExtend32(FPSCR);
op1 ← SignExtend32(Rm);
IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;
IF (FpuIsDisabled(sr))
THROW FPUDIS;
address ← ZeroExtend32(op1);
op2 ← ReadMemory32(address);
op2 ← FloatValue32(ReadMemory32(address));
FRn ← FloatRegister32(op2);

3
sh4/FMOV.S FRm,@(R0,Rn)
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@ -9,4 +9,5 @@ THROW SLOTFPUDIS;
IF (FpuIsDisabled(sr))
THROW FPUDIS;
address ← ZeroExtend32(r0 + op2);
WriteMemory32(address, op1);
value ← FloatRegister32(op1);
WriteMemory32(address, value);

4
sh4/FMOV.S FRm,@-Rn
View File

@ -1,7 +1,6 @@
1111nnnnmmmm1011
Available only when SZ=0
sr ← ZeroExtend32(SR);
fps ← ZeroExtend32(FPSCR);
op1 ← FloatValue32(FRm);
op2 ← SignExtend32(Rn);
IF (FpuIsDisabled(sr) AND IsDelaySlot())
@ -9,6 +8,7 @@ THROW SLOTFPUDIS;
IF (FpuIsDisabled(sr))
THROW FPUDIS;
address ← ZeroExtend32(op2 - 4);
WriteMemory32(address, op1);
value ← FloatRegister32(op1);
WriteMemory32(address, value);
op2 ← address;
Rn ← Register(op2);

4
sh4/FMOV.S FRm,@Rn
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@ -1,7 +1,6 @@
1111nnnnmmmm1010
Available only when SZ=0
sr ← ZeroExtend32(SR);
fps ← ZeroExtend32(FPSCR);
op1 ← FloatValue32(FRm);
op2 ← SignExtend32(Rn);
IF (FpuIsDisabled(sr) AND IsDelaySlot())
@ -9,4 +8,5 @@ THROW SLOTFPUDIS;
IF (FpuIsDisabled(sr))
THROW FPUDIS;
address ← ZeroExtend32(op2);
WriteMemory32(address, op1);
value ← FloatRegister32(op1);
WriteMemory32(address, value);

1
sh4/FNEG FRn
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@ -1,7 +1,6 @@
1111nnnn01001101
Available only when PR=0
sr ← ZeroExtend32(SR);
fps ← ZeroExtend32(FPSCR);
op1 ← FloatValue32(FRn);
IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;

4
sh4/FRCHG
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@ -1,10 +1,10 @@
1111101111111101
Available only when PR=0
sr ← ZeroExtend32(SR);
fr ← ZeroExtend1(SR.FR);
fr ← ZeroExtend1(FPSCR.FR);
IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;
IF (FpuIsDisabled(sr))
THROW FPUDIS;
fr ← fr ⊕ 1;
SR.FR ← Bit(fr);
FPSCR.FR ← Bit(fr);

2
sh4/FSTS FPUL,FRn
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@ -5,5 +5,5 @@ IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS;
IF (FpuIsDisabled(sr))
THROW FPUDIS;
op1 ← fpul;
op1 ← FloatValue32(fpul);
FRn ← FloatRegister32(op1);