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regs: add display registers, memory controller, pcie

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This commit is contained in:
Zack Buhman 2025-11-15 13:03:09 -06:00
parent bed4b640ad
commit 687bc734d9
8 changed files with 6434 additions and 10 deletions
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86
pci_user/main.c
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@ -21,6 +21,41 @@ static inline void wreg(void * rmmio, uint32_t offset, uint32_t value)
asm volatile ("" ::: "memory"); asm volatile ("" ::: "memory");
} }
static inline void wreg_slow(void * rmmio, uint32_t offset, uint32_t value)
{
#define MM_INDEX 0x0
#define MM_DATA 0x4
wreg(rmmio, MM_INDEX, offset);
wreg(rmmio, MM_DATA, value);
}
static inline uint32_t rreg_slow(void * rmmio, uint32_t offset)
{
wreg(rmmio, MM_INDEX, offset);
uint32_t value = rreg(rmmio, MM_DATA);
return value;
}
struct name_address {
const char * name;
const int address;
};
const struct name_address display_addresses[] = {
#include "../regs/display_registers.inc"
};
const int display_addresses_length = (sizeof (display_addresses)) / (sizeof (display_addresses[0]));
const struct name_address memory_controller_addresses[] = {
#include "../regs/memory_controller_registers.inc"
};
const int memory_controller_addresses_length = (sizeof (memory_controller_addresses)) / (sizeof (memory_controller_addresses[0]));
const struct name_address pcie_addresses[] = {
#include "../regs/pcie_registers.inc"
};
const int pcie_addresses_length = (sizeof (pcie_addresses)) / (sizeof (pcie_addresses[0]));
int main() int main()
{ {
//////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////
@ -36,16 +71,47 @@ int main()
void * rmmio = resource2_base; void * rmmio = resource2_base;
uint32_t value1 = rreg(rmmio, 0x6110); if (1) {
printf("[r500] D1GRPH_PRIMARY_SURFACE_ADDRESS %08x\n", value1); for (int i = 0; i < display_addresses_length; i++) {
uint32_t value2 = rreg(rmmio, 0x6110 + 0x800); uint32_t value = rreg(rmmio, display_addresses[i].address);
printf("[r500] D2GRPH_PRIMARY_SURFACE_ADDRESS %08x\n", value2); printf("%s %x %08x\n", display_addresses[i].name, display_addresses[i].address, value);
}
}
uint32_t value3 = rreg(rmmio, 0x6118); if (0) {
printf("[r500] D1GRPH_SECONDARY_SURFACE_ADDRESS %08x\n", value3); #define MC_IND_INDEX 0x70
uint32_t value4 = rreg(rmmio, 0x6118 + 0x800); #define MC_IND_INDEX__MC_IND_ADDR(x) (((x) & 0xffff) << 0)
printf("[r500] D2GRPH_SECONDARY_SURFACE_ADDRESS %08x\n", value4); #define MC_IND_INDEX__MC_IND_ADDR__CLEAR (~0xffff)
#define MC_IND_DATA 0x74
// skip MC_IND_INDEX/MC_IND_DATA
const int masks[] = {
(1 << 16),
(1 << 17),
(1 << 20),
(1 << 21),
(1 << 22),
};
wreg(rmmio, 0x6110, 0x813000); for (int i = 2; i < memory_controller_addresses_length; i++) {
wreg(rmmio, 0x6118, 0x813000); const char * name = memory_controller_addresses[i].name;
int address = memory_controller_addresses[i].address;
int mask = (1 << 16) | (1 << 17) | (1 << 20) | (1 << 21) | (1 << 22);
wreg(rmmio, MC_IND_INDEX, MC_IND_INDEX__MC_IND_ADDR(address) | mask);
uint32_t value = rreg(rmmio, MC_IND_DATA);
wreg(rmmio, MC_IND_INDEX, MC_IND_INDEX__MC_IND_ADDR__CLEAR);
printf("%s %x %08x\n", name, address, value);
}
}
if (0) {
#define PCIE_INDEX 0x30
#define PCIE_DATA 0x38
for (int i = 0; i < pcie_addresses_length; i++) {
const char * name = pcie_addresses[i].name;
int address = pcie_addresses[i].address;
wreg_slow(rmmio, PCIE_INDEX, address);
uint32_t value = rreg_slow(rmmio, PCIE_DATA);
printf("%s %x %08x\n", name, address, value);
}
}
} }

2336
regs/display_registers.inc Normal file
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File diff suppressed because it is too large Load Diff

1752
regs/display_registers.txt Normal file
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File diff suppressed because it is too large Load Diff

628
regs/memory_controller_registers.inc Normal file
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@ -0,0 +1,628 @@
{
.name = "MC_IND_INDEX",
.address = 0x70,
},
{
.name = "MC_IND_DATA",
.address = 0x74,
},
{
.name = "MC_STATUS",
.address = 0x0,
},
{
.name = "MC_ARB_MIN",
.address = 0x10,
},
{
.name = "MC_PT0_CNTL",
.address = 0x100,
},
{
.name = "MC_PT0_CONTEXT0_CNTL",
.address = 0x102,
},
{
.name = "MC_PT0_CONTEXT1_CNTL",
.address = 0x103,
},
{
.name = "MC_PT0_CONTEXT2_CNTL",
.address = 0x104,
},
{
.name = "MC_PT0_CONTEXT3_CNTL",
.address = 0x105,
},
{
.name = "MC_PT0_CONTEXT4_CNTL",
.address = 0x106,
},
{
.name = "MC_PT0_CONTEXT5_CNTL",
.address = 0x107,
},
{
.name = "MC_PT0_CONTEXT6_CNTL",
.address = 0x108,
},
{
.name = "MC_PT0_CONTEXT7_CNTL",
.address = 0x109,
},
{
.name = "MC_PT0_SYSTEM_APERTURE_LOW_ADDR",
.address = 0x112,
},
{
.name = "MC_PT0_SYSTEM_APERTURE_HIGH_ADDR",
.address = 0x114,
},
{
.name = "MC_PT0_SURFACE_PROBE",
.address = 0x116,
},
{
.name = "MC_PT0_SURFACE_PROBE_FAULT_STATUS",
.address = 0x118,
},
{
.name = "MC_PT0_PROTECTION_FAULT_STATUS",
.address = 0x11a,
},
{
.name = "MC_PT0_CONTEXT0_DEFAULT_READ_ADDR",
.address = 0x11c,
},
{
.name = "MC_PT0_CONTEXT1_DEFAULT_READ_ADDR",
.address = 0x11d,
},
{
.name = "MC_PT0_CONTEXT2_DEFAULT_READ_ADDR",
.address = 0x11e,
},
{
.name = "MC_PT0_CONTEXT3_DEFAULT_READ_ADDR",
.address = 0x11f,
},
{
.name = "MC_ARB_TIMERS",
.address = 0x12,
},
{
.name = "MC_PT0_CONTEXT4_DEFAULT_READ_ADDR",
.address = 0x120,
},
{
.name = "MC_PT0_CONTEXT5_DEFAULT_READ_ADDR",
.address = 0x121,
},
{
.name = "MC_PT0_CONTEXT6_DEFAULT_READ_ADDR",
.address = 0x122,
},
{
.name = "MC_PT0_CONTEXT7_DEFAULT_READ_ADDR",
.address = 0x123,
},
{
.name = "MC_PT0_CONTEXT0_FLAT_BASE_ADDR",
.address = 0x12c,
},
{
.name = "MC_PT0_CONTEXT1_FLAT_BASE_ADDR",
.address = 0x12d,
},
{
.name = "MC_PT0_CONTEXT2_FLAT_BASE_ADDR",
.address = 0x12e,
},
{
.name = "MC_PT0_CONTEXT3_FLAT_BASE_ADDR",
.address = 0x12f,
},
{
.name = "MC_ARB_DRAM_PENALTIES",
.address = 0x13,
},
{
.name = "MC_PT0_CONTEXT4_FLAT_BASE_ADDR",
.address = 0x130,
},
{
.name = "MC_PT0_CONTEXT5_FLAT_BASE_ADDR",
.address = 0x131,
},
{
.name = "MC_PT0_CONTEXT6_FLAT_BASE_ADDR",
.address = 0x132,
},
{
.name = "MC_PT0_CONTEXT7_FLAT_BASE_ADDR",
.address = 0x133,
},
{
.name = "MC_PT0_CONTEXT0_FLAT_START_ADDR",
.address = 0x13c,
},
{
.name = "MC_PT0_CONTEXT1_FLAT_START_ADDR",
.address = 0x13d,
},
{
.name = "MC_PT0_CONTEXT2_FLAT_START_ADDR",
.address = 0x13e,
},
{
.name = "MC_PT0_CONTEXT3_FLAT_START_ADDR",
.address = 0x13f,
},
{
.name = "MC_ARB_DRAM_PENALTIES2",
.address = 0x14,
},
{
.name = "MC_PT0_CONTEXT4_FLAT_START_ADDR",
.address = 0x140,
},
{
.name = "MC_PT0_CONTEXT5_FLAT_START_ADDR",
.address = 0x141,
},
{
.name = "MC_PT0_CONTEXT6_FLAT_START_ADDR",
.address = 0x142,
},
{
.name = "MC_PT0_CONTEXT7_FLAT_START_ADDR",
.address = 0x143,
},
{
.name = "MC_PT0_CONTEXT0_FLAT_END_ADDR",
.address = 0x14c,
},
{
.name = "MC_PT0_CONTEXT1_FLAT_END_ADDR",
.address = 0x14d,
},
{
.name = "MC_PT0_CONTEXT2_FLAT_END_ADDR",
.address = 0x14e,
},
{
.name = "MC_PT0_CONTEXT3_FLAT_END_ADDR",
.address = 0x14f,
},
{
.name = "MC_ARB_DRAM_PENALTIES3",
.address = 0x15,
},
{
.name = "MC_PT0_CONTEXT4_FLAT_END_ADDR",
.address = 0x150,
},
{
.name = "MC_PT0_CONTEXT5_FLAT_END_ADDR",
.address = 0x151,
},
{
.name = "MC_PT0_CONTEXT6_FLAT_END_ADDR",
.address = 0x152,
},
{
.name = "MC_PT0_CONTEXT7_FLAT_END_ADDR",
.address = 0x153,
},
{
.name = "MC_PT0_CONTEXT0_MULTI_LEVEL_BASE_ADDR",
.address = 0x15c,
},
{
.name = "MC_PT0_CONTEXT1_MULTI_LEVEL_BASE_ADDR",
.address = 0x15d,
},
{
.name = "MC_PT0_CONTEXT2_MULTI_LEVEL_BASE_ADDR",
.address = 0x15e,
},
{
.name = "MC_PT0_CONTEXT3_MULTI_LEVEL_BASE_ADDR",
.address = 0x15f,
},
{
.name = "MC_ARB_RATIO_CLK_SEQ",
.address = 0x16,
},
{
.name = "MC_PT0_CONTEXT4_MULTI_LEVEL_BASE_ADDR",
.address = 0x160,
},
{
.name = "MC_PT0_CONTEXT5_MULTI_LEVEL_BASE_ADDR",
.address = 0x161,
},
{
.name = "MC_PT0_CONTEXT6_MULTI_LEVEL_BASE_ADDR",
.address = 0x162,
},
{
.name = "MC_PT0_CONTEXT7_MULTI_LEVEL_BASE_ADDR",
.address = 0x163,
},
{
.name = "MC_PT0_CLIENT0_CNTL",
.address = 0x16c,
},
{
.name = "MC_PT0_CLIENT1_CNTL",
.address = 0x16d,
},
{
.name = "MC_PT0_CLIENT2_CNTL",
.address = 0x16e,
},
{
.name = "MC_PT0_CLIENT3_CNTL",
.address = 0x16f,
},
{
.name = "MC_ARB_RDWR_SWITCH",
.address = 0x17,
},
{
.name = "MC_PT0_CLIENT4_CNTL",
.address = 0x170,
},
{
.name = "MC_PT0_CLIENT5_CNTL",
.address = 0x171,
},
{
.name = "MC_PT0_CLIENT6_CNTL",
.address = 0x172,
},
{
.name = "MC_PT0_CLIENT7_CNTL",
.address = 0x173,
},
{
.name = "MC_PT0_CLIENT8_CNTL",
.address = 0x174,
},
{
.name = "MC_PT0_CLIENT9_CNTL",
.address = 0x175,
},
{
.name = "MC_PT0_CLIENT10_CNTL",
.address = 0x176,
},
{
.name = "MC_PT0_CLIENT11_CNTL",
.address = 0x177,
},
{
.name = "MC_PT0_CLIENT12_CNTL",
.address = 0x178,
},
{
.name = "MC_PT0_CLIENT13_CNTL",
.address = 0x179,
},
{
.name = "MC_PT0_CLIENT14_CNTL",
.address = 0x17a,
},
{
.name = "MC_PT0_CLIENT15_CNTL",
.address = 0x17b,
},
{
.name = "MC_PT0_CLIENT16_CNTL",
.address = 0x17c,
},
{
.name = "MC_SW_CNTL",
.address = 0x18,
},
{
.name = "MC_TIMING_CNTL_2",
.address = 0x3,
},
{
.name = "MC_WRITE_AGE1",
.address = 0x37,
},
{
.name = "MC_WRITE_AGE2",
.address = 0x38,
},
{
.name = "MC_FB_LOCATION",
.address = 0x4,
},
{
.name = "MC_AGP_LOCATION",
.address = 0x5,
},
{
.name = "AGP_BASE",
.address = 0x6,
},
{
.name = "MC_SEQ_DRAM",
.address = 0x60,
},
{
.name = "MC_SEQ_RAS_TIMING",
.address = 0x61,
},
{
.name = "MC_SEQ_CAS_TIMING",
.address = 0x62,
},
{
.name = "MC_SEQ_MISC_TIMING",
.address = 0x63,
},
{
.name = "MC_SEQ_RD_CTL_I0",
.address = 0x64,
},
{
.name = "MC_SEQ_RD_CTL_I1",
.address = 0x65,
},
{
.name = "MC_SEQ_WR_CTL_I0",
.address = 0x66,
},
{
.name = "MC_SEQ_WR_CTL_I1",
.address = 0x67,
},
{
.name = "MC_SEQ_IO_CTL_I0",
.address = 0x68,
},
{
.name = "MC_SEQ_IO_CTL_I1",
.address = 0x69,
},
{
.name = "MC_SEQ_NPL_CTL_I0",
.address = 0x6a,
},
{
.name = "MC_SEQ_NPL_CTL_I1",
.address = 0x6b,
},
{
.name = "MC_SEQ_CK_PAD_CNTL_I0",
.address = 0x6c,
},
{
.name = "MC_SEQ_CK_PAD_CNTL_I1",
.address = 0x6d,
},
{
.name = "MC_SEQ_CMD_PAD_CNTL_I0",
.address = 0x6e,
},
{
.name = "MC_SEQ_CMD_PAD_CNTL_I1",
.address = 0x6f,
},
{
.name = "AGP_BASE_2",
.address = 0x7,
},
{
.name = "MC_SEQ_DQ_PAD_CNTL_I0",
.address = 0x70,
},
{
.name = "MC_SEQ_DQ_PAD_CNTL_I1",
.address = 0x71,
},
{
.name = "MC_SEQ_QS_PAD_CNTL_I0",
.address = 0x72,
},
{
.name = "MC_SEQ_QS_PAD_CNTL_I1",
.address = 0x73,
},
{
.name = "MC_SEQ_A_PAD_CNTL_I0",
.address = 0x74,
},
{
.name = "MC_SEQ_A_PAD_CNTL_I1",
.address = 0x75,
},
{
.name = "MC_SEQ_CMD",
.address = 0x76,
},
{
.name = "MC_SEQ_STATUS",
.address = 0x77,
},
{
.name = "MC_CNTL0",
.address = 0x8,
},
{
.name = "MC_IO_PAD_CNTL_I0",
.address = 0x80,
},
{
.name = "MC_IO_PAD_CNTL_I1",
.address = 0x81,
},
{
.name = "MC_IO_PAD_CNTL",
.address = 0x82,
},
{
.name = "MC_IO_RD_DQ_CNTL_I0",
.address = 0x84,
},
{
.name = "MC_IO_RD_DQ_CNTL_I1",
.address = 0x85,
},
{
.name = "MC_IO_RD_QS_CNTL_I0",
.address = 0x86,
},
{
.name = "MC_IO_RD_QS_CNTL_I1",
.address = 0x87,
},
{
.name = "MC_IO_WR_CNTL_I0",
.address = 0x88,
},
{
.name = "MC_IO_WR_CNTL_I1",
.address = 0x89,
},
{
.name = "MC_IO_CK_PAD_CNTL_I0",
.address = 0x8a,
},
{
.name = "MC_IO_CK_PAD_CNTL_I1",
.address = 0x8b,
},
{
.name = "MC_IO_CMD_PAD_CNTL_I0",
.address = 0x8c,
},
{
.name = "MC_IO_CMD_PAD_CNTL_I1",
.address = 0x8d,
},
{
.name = "MC_IO_DQ_PAD_CNTL_I0",
.address = 0x8e,
},
{
.name = "MC_IO_DQ_PAD_CNTL_I1",
.address = 0x8f,
},
{
.name = "MC_CNTL1",
.address = 0x9,
},
{
.name = "MC_IO_QS_PAD_CNTL_I0",
.address = 0x90,
},
{
.name = "MC_IO_QS_PAD_CNTL_I1",
.address = 0x91,
},
{
.name = "MC_IO_A_PAD_CNTL_I0",
.address = 0x92,
},
{
.name = "MC_IO_A_PAD_CNTL_I1",
.address = 0x93,
},
{
.name = "MC_IO_WR_DQ_CNTL_I0",
.address = 0x94,
},
{
.name = "MC_IO_WR_DQ_CNTL_I1",
.address = 0x95,
},
{
.name = "MC_IO_WR_QS_CNTL_I0",
.address = 0x96,
},
{
.name = "MC_IO_WR_QS_CNTL_I1",
.address = 0x97,
},
{
.name = "MC_VENDOR_ID_I0",
.address = 0x98,
},
{
.name = "MC_VENDOR_ID_I1",
.address = 0x99,
},
{
.name = "MC_NPL_STATUS_I0",
.address = 0x9a,
},
{
.name = "MC_NPL_STATUS_I1",
.address = 0x9b,
},
{
.name = "MC_IO_RD_QS2_CNTL_I0",
.address = 0x9c,
},
{
.name = "MC_IO_RD_QS2_CNTL_I1",
.address = 0x9d,
},
{
.name = "MC_RFSH_CNTL",
.address = 0xa,
},
{
.name = "MC_IMP_CNTL",
.address = 0xa0,
},
{
.name = "MC_IMP_DEBUG",
.address = 0xa1,
},
{
.name = "MC_IMP_STATUS",
.address = 0xa2,
},
{
.name = "MC_RBS_MAP",
.address = 0xb0,
},
{
.name = "MC_RBS_CZT_HWM",
.address = 0xb1,
},
{
.name = "MC_RBS_SUN_HWM",
.address = 0xb2,
},
{
.name = "MC_RBS_MISC",
.address = 0xb3,
},
{
.name = "MC_PMG_CMD",
.address = 0xe0,
},
{
.name = "MC_PMG_CFG",
.address = 0xe1,
},
{
.name = "MC_MISC_0",
.address = 0xf0,
},
{
.name = "MC_MISC_1",
.address = 0xf1,
},
{
.name = "MC_DEBUG",
.address = 0xfe,
},

471
regs/memory_controller_registers.txt Normal file
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@ -0,0 +1,471 @@
MC_IND_INDEX
MCDEC:0x70
2-2
MC_IND_DATA
MCDEC:0x74
2-2
MC_STATUS
MCIND:0x0
2-2
MC_ARB_MIN
MCIND:0x10
2-8
MC_PT0_CNTL
MCIND:0x100
2-32
MC_PT0_CONTEXT0_CNTL
MCIND:0x102
2-33
MC_PT0_CONTEXT1_CNTL
MCIND:0x103
2-33
MC_PT0_CONTEXT2_CNTL
MCIND:0x104
2-33
MC_PT0_CONTEXT3_CNTL
MCIND:0x105
2-34
MC_PT0_CONTEXT4_CNTL
MCIND:0x106
2-34
MC_PT0_CONTEXT5_CNTL
MCIND:0x107
2-34
MC_PT0_CONTEXT6_CNTL
MCIND:0x108
2-34
MC_PT0_CONTEXT7_CNTL
MCIND:0x109
2-35
MC_PT0_SYSTEM_APERTURE_LOW_ADDR
MCIND:0x112
2-35
MC_PT0_SYSTEM_APERTURE_HIGH_ADDR
MCIND:0x114
2-35
MC_PT0_SURFACE_PROBE
MCIND:0x116
2-35
MC_PT0_SURFACE_PROBE_FAULT_STATUS
MCIND:0x118
2-36
MC_PT0_PROTECTION_FAULT_STATUS
MCIND:0x11A
2-36
MC_PT0_CONTEXT0_DEFAULT_READ_ADDR
MCIND:0x11C
2-36
MC_PT0_CONTEXT1_DEFAULT_READ_ADDR
MCIND:0x11D
2-36
MC_PT0_CONTEXT2_DEFAULT_READ_ADDR
MCIND:0x11E
2-37
MC_PT0_CONTEXT3_DEFAULT_READ_ADDR
MCIND:0x11F
2-37
MC_ARB_TIMERS
MCIND:0x12
2-8
MC_PT0_CONTEXT4_DEFAULT_READ_ADDR
MCIND:0x120
2-37
MC_PT0_CONTEXT5_DEFAULT_READ_ADDR
MCIND:0x121
2-37
MC_PT0_CONTEXT6_DEFAULT_READ_ADDR
MCIND:0x122
2-37
MC_PT0_CONTEXT7_DEFAULT_READ_ADDR
MCIND:0x123
2-37
MC_PT0_CONTEXT0_FLAT_BASE_ADDR
MCIND:0x12C
2-37
MC_PT0_CONTEXT1_FLAT_BASE_ADDR
MCIND:0x12D
2-38
MC_PT0_CONTEXT2_FLAT_BASE_ADDR
MCIND:0x12E
2-38
MC_PT0_CONTEXT3_FLAT_BASE_ADDR
MCIND:0x12F
2-38
MC_ARB_DRAM_PENALTIES
MCIND:0x13
2-8
MC_PT0_CONTEXT4_FLAT_BASE_ADDR
MCIND:0x130
2-38
MC_PT0_CONTEXT5_FLAT_BASE_ADDR
MCIND:0x131
2-38
MC_PT0_CONTEXT6_FLAT_BASE_ADDR
MCIND:0x132
2-38
MC_PT0_CONTEXT7_FLAT_BASE_ADDR
MCIND:0x133
2-39
MC_PT0_CONTEXT0_FLAT_START_ADDR
MCIND:0x13C
2-39
MC_PT0_CONTEXT1_FLAT_START_ADDR
MCIND:0x13D
2-39
MC_PT0_CONTEXT2_FLAT_START_ADDR
MCIND:0x13E
2-39
MC_PT0_CONTEXT3_FLAT_START_ADDR
MCIND:0x13F
2-39
MC_ARB_DRAM_PENALTIES2
MCIND:0x14
2-8
MC_PT0_CONTEXT4_FLAT_START_ADDR
MCIND:0x140
2-39
MC_PT0_CONTEXT5_FLAT_START_ADDR
MCIND:0x141
2-40
MC_PT0_CONTEXT6_FLAT_START_ADDR
MCIND:0x142
2-40
MC_PT0_CONTEXT7_FLAT_START_ADDR
MCIND:0x143
2-40
MC_PT0_CONTEXT0_FLAT_END_ADDR
MCIND:0x14C
2-40
MC_PT0_CONTEXT1_FLAT_END_ADDR
MCIND:0x14D
2-40
MC_PT0_CONTEXT2_FLAT_END_ADDR
MCIND:0x14E
2-40
MC_PT0_CONTEXT3_FLAT_END_ADDR
MCIND:0x14F
2-41
MC_ARB_DRAM_PENALTIES3
MCIND:0x15
2-9
MC_PT0_CONTEXT4_FLAT_END_ADDR
MCIND:0x150
2-41
MC_PT0_CONTEXT5_FLAT_END_ADDR
MCIND:0x151
2-41
MC_PT0_CONTEXT6_FLAT_END_ADDR
MCIND:0x152
2-41
MC_PT0_CONTEXT7_FLAT_END_ADDR
MCIND:0x153
2-41
MC_PT0_CONTEXT0_MULTI_LEVEL_BASE_ADDR
MCIND:0x15C
2-41
MC_PT0_CONTEXT1_MULTI_LEVEL_BASE_ADDR
MCIND:0x15D
2-42
MC_PT0_CONTEXT2_MULTI_LEVEL_BASE_ADDR
MCIND:0x15E
2-42
MC_PT0_CONTEXT3_MULTI_LEVEL_BASE_ADDR
MCIND:0x15F
2-42
MC_ARB_RATIO_CLK_SEQ
MCIND:0x16
2-9
MC_PT0_CONTEXT4_MULTI_LEVEL_BASE_ADDR
MCIND:0x160
2-42
MC_PT0_CONTEXT5_MULTI_LEVEL_BASE_ADDR
MCIND:0x161
2-42
MC_PT0_CONTEXT6_MULTI_LEVEL_BASE_ADDR
MCIND:0x162
2-42
MC_PT0_CONTEXT7_MULTI_LEVEL_BASE_ADDR
MCIND:0x163
2-42
MC_PT0_CLIENT0_CNTL
MCIND:0x16C
2-43
MC_PT0_CLIENT1_CNTL
MCIND:0x16D
2-43
MC_PT0_CLIENT2_CNTL
MCIND:0x16E
2-44
MC_PT0_CLIENT3_CNTL
MCIND:0x16F
2-45
MC_ARB_RDWR_SWITCH
MCIND:0x17
2-9
MC_PT0_CLIENT4_CNTL
MCIND:0x170
2-46
MC_PT0_CLIENT5_CNTL
MCIND:0x171
2-47
MC_PT0_CLIENT6_CNTL
MCIND:0x172
2-48
MC_PT0_CLIENT7_CNTL
MCIND:0x173
2-49
MC_PT0_CLIENT8_CNTL
MCIND:0x174
2-49
MC_PT0_CLIENT9_CNTL
MCIND:0x175
2-50
MC_PT0_CLIENT10_CNTL
MCIND:0x176
2-51
MC_PT0_CLIENT11_CNTL
MCIND:0x177
2-52
MC_PT0_CLIENT12_CNTL
MCIND:0x178
2-53
MC_PT0_CLIENT13_CNTL
MCIND:0x179
2-54
MC_PT0_CLIENT14_CNTL
MCIND:0x17A
2-55
MC_PT0_CLIENT15_CNTL
MCIND:0x17B
2-55
MC_PT0_CLIENT16_CNTL
MCIND:0x17C
2-56
MC_SW_CNTL
MCIND:0x18
2-9
MC_TIMING_CNTL_2
MCIND:0x3
2-3
MC_WRITE_AGE1
MCIND:0x37
2-9
MC_WRITE_AGE2
MCIND:0x38
2-10
MC_FB_LOCATION
MCIND:0x4
2-3
MC_AGP_LOCATION
MCIND:0x5
2-3
AGP_BASE
MCIND:0x6
2-3
MC_SEQ_DRAM
MCIND:0x60
2-10
MC_SEQ_RAS_TIMING
MCIND:0x61
2-11
MC_SEQ_CAS_TIMING
MCIND:0x62
2-11
MC_SEQ_MISC_TIMING
MCIND:0x63
2-12
MC_SEQ_RD_CTL_I0
MCIND:0x64
2-12
MC_SEQ_RD_CTL_I1
MCIND:0x65
2-13
MC_SEQ_WR_CTL_I0
MCIND:0x66
2-14
MC_SEQ_WR_CTL_I1
MCIND:0x67
2-15
MC_SEQ_IO_CTL_I0
MCIND:0x68
2-15
MC_SEQ_IO_CTL_I1
MCIND:0x69
2-15
MC_SEQ_NPL_CTL_I0
MCIND:0x6A
2-16
MC_SEQ_NPL_CTL_I1
MCIND:0x6B
2-16
MC_SEQ_CK_PAD_CNTL_I0
MCIND:0x6C
2-16
MC_SEQ_CK_PAD_CNTL_I1
MCIND:0x6D
2-16
MC_SEQ_CMD_PAD_CNTL_I0
MCIND:0x6E
2-17
MC_SEQ_CMD_PAD_CNTL_I1
MCIND:0x6F
2-17
AGP_BASE_2
MCIND:0x7
2-3
MC_SEQ_DQ_PAD_CNTL_I0
MCIND:0x70
2-17
MC_SEQ_DQ_PAD_CNTL_I1
MCIND:0x71
2-17
MC_SEQ_QS_PAD_CNTL_I0
MCIND:0x72
2-18
MC_SEQ_QS_PAD_CNTL_I1
MCIND:0x73
2-18
MC_SEQ_A_PAD_CNTL_I0
MCIND:0x74
2-18
MC_SEQ_A_PAD_CNTL_I1
MCIND:0x75
2-18
MC_SEQ_CMD
MCIND:0x76
2-19
MC_SEQ_STATUS
MCIND:0x77
2-19
MC_CNTL0
MCIND:0x8
2-4
MC_IO_PAD_CNTL_I0
MCIND:0x80
2-19
MC_IO_PAD_CNTL_I1
MCIND:0x81
2-20
MC_IO_PAD_CNTL
MCIND:0x82
2-21
MC_IO_RD_DQ_CNTL_I0
MCIND:0x84
2-22
MC_IO_RD_DQ_CNTL_I1
MCIND:0x85
2-22
MC_IO_RD_QS_CNTL_I0
MCIND:0x86
2-22
MC_IO_RD_QS_CNTL_I1
MCIND:0x87
2-22
MC_IO_WR_CNTL_I0
MCIND:0x88
2-22
MC_IO_WR_CNTL_I1
MCIND:0x89
2-23
MC_IO_CK_PAD_CNTL_I0
MCIND:0x8A
2-23
MC_IO_CK_PAD_CNTL_I1
MCIND:0x8B
2-23
MC_IO_CMD_PAD_CNTL_I0
MCIND:0x8C
2-23
MC_IO_CMD_PAD_CNTL_I1
MCIND:0x8D
2-24
MC_IO_DQ_PAD_CNTL_I0
MCIND:0x8E
2-24
MC_IO_DQ_PAD_CNTL_I1
MCIND:0x8F
2-24
MC_CNTL1
MCIND:0x9
2-6
MC_IO_QS_PAD_CNTL_I0
MCIND:0x90
2-25
MC_IO_QS_PAD_CNTL_I1
MCIND:0x91
2-25
MC_IO_A_PAD_CNTL_I0
MCIND:0x92
2-25
MC_IO_A_PAD_CNTL_I1
MCIND:0x93
2-26
MC_IO_WR_DQ_CNTL_I0
MCIND:0x94
2-26
MC_IO_WR_DQ_CNTL_I1
MCIND:0x95
2-26
MC_IO_WR_QS_CNTL_I0
MCIND:0x96
2-26
MC_IO_WR_QS_CNTL_I1
MCIND:0x97
2-27
MC_VENDOR_ID_I0
MCIND:0x98
2-27
MC_VENDOR_ID_I1
MCIND:0x99
2-27
MC_NPL_STATUS_I0
MCIND:0x9A
2-27
MC_NPL_STATUS_I1
MCIND:0x9B
2-27
MC_IO_RD_QS2_CNTL_I0
MCIND:0x9C
2-28
MC_IO_RD_QS2_CNTL_I1
MCIND:0x9D
2-28
MC_RFSH_CNTL
MCIND:0xA
2-8
MC_IMP_CNTL
MCIND:0xA0
2-28
MC_IMP_DEBUG
MCIND:0xA1
2-28
MC_IMP_STATUS
MCIND:0xA2
2-28
MC_RBS_MAP
MCIND:0xB0
2-29
MC_RBS_CZT_HWM
MCIND:0xB1
2-30
MC_RBS_SUN_HWM
MCIND:0xB2
2-30
MC_RBS_MISC
MCIND:0xB3
2-30
MC_PMG_CMD
MCIND:0xE0
2-31
MC_PMG_CFG
MCIND:0xE1
2-31
MC_MISC_0
MCIND:0xF0
2-31
MC_MISC_1
MCIND:0xF1
2-31
MC_DEBUG
MCIND:0xFE
2-32

648
regs/pcie_registers.inc Normal file
View File

@ -0,0 +1,648 @@
{
.name = "PCIE_TX_CNTL",
.address = 0x1,
},
{
.name = "PCIE_TX_GART_CNTL",
.address = 0x10,
},
{
.name = "PCIE_TX_GART_DISCARD_RD_ADDR_LO",
.address = 0x11,
},
{
.name = "PCIE_TX_GART_DISCARD_RD_ADDR_HI",
.address = 0x12,
},
{
.name = "PCIE_TX_GART_BASE",
.address = 0x13,
},
{
.name = "PCIE_TX_GART_START_LO",
.address = 0x14,
},
{
.name = "PCIE_TX_GART_START_HI",
.address = 0x15,
},
{
.name = "PCIE_TX_GART_END_LO",
.address = 0x16,
},
{
.name = "PCIE_TX_GART_END_HI",
.address = 0x17,
},
{
.name = "PCIE_TX_GART_ERROR",
.address = 0x18,
},
{
.name = "PCIE_TX_SEQ",
.address = 0x2,
},
{
.name = "PCIE_TX_GART_LRU_MRU_PTR",
.address = 0x20,
},
{
.name = "PCIE_TX_GART_STATUS",
.address = 0x21,
},
{
.name = "PCIE_TX_GART_TLB_VALID",
.address = 0x22,
},
{
.name = "PCIE_TX_GART_TLB0_DATA",
.address = 0x23,
},
{
.name = "PCIE_TX_GART_TLB1_DATA",
.address = 0x24,
},
{
.name = "PCIE_TX_GART_TLB2_DATA",
.address = 0x25,
},
{
.name = "PCIE_TX_GART_TLB3_DATA",
.address = 0x26,
},
{
.name = "PCIE_TX_GART_TLB4_DATA",
.address = 0x27,
},
{
.name = "PCIE_TX_GART_TLB5_DATA",
.address = 0x28,
},
{
.name = "PCIE_TX_GART_TLB6_DATA",
.address = 0x29,
},
{
.name = "PCIE_TX_GART_TLB7_DATA",
.address = 0x2a,
},
{
.name = "PCIE_TX_GART_TLB8_DATA",
.address = 0x2b,
},
{
.name = "PCIE_TX_GART_TLB9_DATA",
.address = 0x2c,
},
{
.name = "PCIE_TX_GART_TLB10_DATA",
.address = 0x2d,
},
{
.name = "PCIE_TX_GART_TLB11_DATA",
.address = 0x2e,
},
{
.name = "PCIE_TX_GART_TLB12_DATA",
.address = 0x2f,
},
{
.name = "PCIE_TX_REPLAY",
.address = 0x3,
},
{
.name = "PCIE_TX_GART_TLB13_DATA",
.address = 0x30,
},
{
.name = "PCIE_TX_GART_TLB14_DATA",
.address = 0x31,
},
{
.name = "PCIE_TX_GART_TLB15_DATA",
.address = 0x32,
},
{
.name = "PCIE_TX_GART_TLB16_DATA",
.address = 0x33,
},
{
.name = "PCIE_TX_GART_TLB17_DATA",
.address = 0x34,
},
{
.name = "PCIE_TX_GART_TLB18_DATA",
.address = 0x35,
},
{
.name = "PCIE_TX_GART_TLB19_DATA",
.address = 0x36,
},
{
.name = "PCIE_TX_GART_TLB20_DATA",
.address = 0x37,
},
{
.name = "PCIE_TX_GART_TLB21_DATA",
.address = 0x38,
},
{
.name = "PCIE_TX_GART_TLB22_DATA",
.address = 0x39,
},
{
.name = "PCIE_TX_GART_TLB23_DATA",
.address = 0x3a,
},
{
.name = "PCIE_TX_GART_TLB24_DATA",
.address = 0x3b,
},
{
.name = "PCIE_TX_GART_TLB25_DATA",
.address = 0x3c,
},
{
.name = "PCIE_TX_GART_TLB26_DATA",
.address = 0x3d,
},
{
.name = "PCIE_TX_GART_TLB27_DATA",
.address = 0x3e,
},
{
.name = "PCIE_TX_GART_TLB28_DATA",
.address = 0x3f,
},
{
.name = "PCIE_TX_CREDITS_CONSUMED",
.address = 0x4,
},
{
.name = "PCIE_TX_GART_TLB29_DATA",
.address = 0x40,
},
{
.name = "PCIE_CLK_CNTL",
.address = 0x400,
},
{
.name = "PCIE_PRBS10",
.address = 0x401,
},
{
.name = "PCIE_PRBS23_BITCNT0",
.address = 0x402,
},
{
.name = "PCIE_PRBS23_BITCNT1",
.address = 0x403,
},
{
.name = "PCIE_PRBS23_BITCNT2",
.address = 0x404,
},
{
.name = "PCIE_PRBS23_BITCNT3",
.address = 0x405,
},
{
.name = "PCIE_PRBS23_BITCNT4",
.address = 0x406,
},
{
.name = "PCIE_PRBS23_BITCNT5",
.address = 0x407,
},
{
.name = "PCIE_PRBS23_BITCNT6",
.address = 0x408,
},
{
.name = "PCIE_PRBS23_BITCNT7",
.address = 0x409,
},
{
.name = "PCIE_PRBS23_BITCNT8",
.address = 0x40a,
},
{
.name = "PCIE_PRBS23_BITCNT9",
.address = 0x40b,
},
{
.name = "PCIE_PRBS23_BITCNT10",
.address = 0x40c,
},
{
.name = "PCIE_PRBS23_BITCNT11",
.address = 0x40d,
},
{
.name = "PCIE_PRBS23_BITCNT12",
.address = 0x40e,
},
{
.name = "PCIE_PRBS23_BITCNT13",
.address = 0x40f,
},
{
.name = "PCIE_TX_GART_TLB30_DATA",
.address = 0x41,
},
{
.name = "PCIE_PRBS23_BITCNT14",
.address = 0x410,
},
{
.name = "PCIE_PRBS23_BITCNT15",
.address = 0x411,
},
{
.name = "PCIE_PRBS23_ERRCNT0",
.address = 0x412,
},
{
.name = "PCIE_PRBS23_ERRCNT1",
.address = 0x413,
},
{
.name = "PCIE_PRBS23_ERRCNT2",
.address = 0x414,
},
{
.name = "PCIE_PRBS23_ERRCNT3",
.address = 0x415,
},
{
.name = "PCIE_PRBS23_ERRCNT4",
.address = 0x416,
},
{
.name = "PCIE_PRBS23_ERRCNT5",
.address = 0x417,
},
{
.name = "PCIE_PRBS23_ERRCNT6",
.address = 0x418,
},
{
.name = "PCIE_PRBS23_ERRCNT7",
.address = 0x419,
},
{
.name = "PCIE_PRBS23_ERRCNT8",
.address = 0x41a,
},
{
.name = "PCIE_PRBS23_ERRCNT9",
.address = 0x41b,
},
{
.name = "PCIE_PRBS23_ERRCNT10",
.address = 0x41c,
},
{
.name = "PCIE_PRBS23_ERRCNT11",
.address = 0x41d,
},
{
.name = "PCIE_PRBS23_ERRCNT12",
.address = 0x41e,
},
{
.name = "PCIE_PRBS23_ERRCNT13",
.address = 0x41f,
},
{
.name = "PCIE_TX_GART_TLB31_DATA",
.address = 0x42,
},
{
.name = "PCIE_PRBS23_ERRCNT14",
.address = 0x420,
},
{
.name = "PCIE_PRBS23_ERRCNT15",
.address = 0x421,
},
{
.name = "PCIE_PRBS23_CTRL0",
.address = 0x422,
},
{
.name = "PCIE_PRBS23_CTRL1",
.address = 0x423,
},
{
.name = "PCIE_PRBS_EN",
.address = 0x424,
},
{
.name = "PCIE_XSTRAP1",
.address = 0x425,
},
{
.name = "PCIE_XSTRAP2",
.address = 0x426,
},
{
.name = "PCIE_XSTRAP5",
.address = 0x429,
},
{
.name = "PCIE_TX_CREDITS_CONSUMED_D",
.address = 0x5,
},
{
.name = "PCIE_TX_CREDITS_CONSUMED_CPLD",
.address = 0x6,
},
{
.name = "PCIE_FLOW_CNTL",
.address = 0x60,
},
{
.name = "PCIE_TXRX_DEBUG_SEQNUM",
.address = 0x61,
},
{
.name = "PCIE_TXRX_TEST_MODE",
.address = 0x62,
},
{
.name = "PCIE_TX_CREDITS_LIMIT",
.address = 0x7,
},
{
.name = "PCIE_RX_CNTL",
.address = 0x70,
},
{
.name = "PCIE_RX_NUM_NACK",
.address = 0x71,
},
{
.name = "PCIE_RX_NUM_NACK_GENERATED",
.address = 0x72,
},
{
.name = "PCIE_RX_ACK_NACK_LATENCY",
.address = 0x73,
},
{
.name = "PCIE_RX_ACK_NACK_LATENCY_THRESHOLD",
.address = 0x74,
},
{
.name = "PCIE_RX_TLP_HDR0",
.address = 0x75,
},
{
.name = "PCIE_RX_TLP_HDR1",
.address = 0x76,
},
{
.name = "PCIE_RX_TLP_HDR2",
.address = 0x77,
},
{
.name = "PCIE_RX_TLP_HDR3",
.address = 0x78,
},
{
.name = "PCIE_RX_TLP_HDR4",
.address = 0x79,
},
{
.name = "PCIE_RX_TLP_CRC",
.address = 0x7a,
},
{
.name = "PCIE_RX_DLP0",
.address = 0x7b,
},
{
.name = "PCIE_RX_DLP1",
.address = 0x7c,
},
{
.name = "PCIE_RX_DLP_CRC",
.address = 0x7d,
},
{
.name = "PCIE_RX_CREDITS_ALLOCATED",
.address = 0x7e,
},
{
.name = "PCIE_RX_CREDITS_ALLOCATED_D",
.address = 0x7f,
},
{
.name = "PCIE_TX_CREDITS_LIMIT_D",
.address = 0x8,
},
{
.name = "PCIE_RX_CREDITS_ALLOCATED_CPLD",
.address = 0x80,
},
{
.name = "PCIE_RX_CREDITS_RECEIVED",
.address = 0x81,
},
{
.name = "PCIE_RX_CREDITS_RECEIVED_D",
.address = 0x82,
},
{
.name = "PCIE_RX_CREDITS_RECEIVED_CPLD",
.address = 0x83,
},
{
.name = "PCIE_RX_MAL_TLP_COUNT",
.address = 0x84,
},
{
.name = "PCIE_RX_ERR_LOG",
.address = 0x85,
},
{
.name = "PCIE_RX_EXPECTED_SEQNUM",
.address = 0x86,
},
{
.name = "PCIE_TX_CREDITS_LIMIT_CPLD",
.address = 0x9,
},
{
.name = "PCIE_CI_CNTL",
.address = 0x90,
},
{
.name = "PCIE_CI_FLUSH_CNTL",
.address = 0x91,
},
{
.name = "PCIE_CI_PANIC",
.address = 0x92,
},
{
.name = "PCIE_CI_HANG",
.address = 0x93,
},
{
.name = "PCIE_LC_CNTL",
.address = 0xa0,
},
{
.name = "PCIE_LC_N_FTS_CNTL",
.address = 0xa1,
},
{
.name = "PCIE_LC_LINK_WIDTH_CNTL",
.address = 0xa2,
},
{
.name = "PCIE_LC_STATE0",
.address = 0xa5,
},
{
.name = "PCIE_LC_STATE1",
.address = 0xa6,
},
{
.name = "PCIE_LC_STATE2",
.address = 0xa7,
},
{
.name = "PCIE_LC_STATE3",
.address = 0xa8,
},
{
.name = "PCIE_LC_STATE4",
.address = 0xa9,
},
{
.name = "PCIE_LC_STATE5",
.address = 0xaa,
},
{
.name = "PCIE_LC_FORCE_SYNC_LOSS_CNTL",
.address = 0xab,
},
{
.name = "PCIE_P_CNTL",
.address = 0xb0,
},
{
.name = "PCIE_P_CNTL2",
.address = 0xb1,
},
{
.name = "PCIE_P_BUF_STATUS",
.address = 0xb2,
},
{
.name = "PCIE_P_DECODER_STATUS",
.address = 0xb3,
},
{
.name = "PCIE_P_MISC_DEBUG_STATUS",
.address = 0xb4,
},
{
.name = "PCIE_P_IMP_CNTL_STRENGTH",
.address = 0xc0,
},
{
.name = "PCIE_P_IMP_CNTL_UPDATE",
.address = 0xc1,
},
{
.name = "PCIE_P_STR_CNTL_UPDATE",
.address = 0xc2,
},
{
.name = "PCIE_P_PAD_MISC_CNTL",
.address = 0xc3,
},
{
.name = "PCIE_P_SYMSYNC_CTL",
.address = 0xc4,
},
{
.name = "PCIE_P_DECODE_ERR_CNTL",
.address = 0xc5,
},
{
.name = "PCIE_ERR_CNTL",
.address = 0xe0,
},
{
.name = "PCIE_CLK_RST_CNTL",
.address = 0xe1,
},
{
.name = "PCIE_P_DECODE_ERR_CNT_0",
.address = 0xf0,
},
{
.name = "PCIE_P_DECODE_ERR_CNT_1",
.address = 0xf1,
},
{
.name = "PCIE_P_DECODE_ERR_CNT_2",
.address = 0xf2,
},
{
.name = "PCIE_P_DECODE_ERR_CNT_3",
.address = 0xf3,
},
{
.name = "PCIE_P_DECODE_ERR_CNT_4",
.address = 0xf4,
},
{
.name = "PCIE_P_DECODE_ERR_CNT_5",
.address = 0xf5,
},
{
.name = "PCIE_P_DECODE_ERR_CNT_6",
.address = 0xf6,
},
{
.name = "PCIE_P_DECODE_ERR_CNT_7",
.address = 0xf7,
},
{
.name = "PCIE_P_DECODE_ERR_CNT_8",
.address = 0xf8,
},
{
.name = "PCIE_P_DECODE_ERR_CNT_9",
.address = 0xf9,
},
{
.name = "PCIE_P_DECODE_ERR_CNT_10",
.address = 0xfa,
},
{
.name = "PCIE_P_DECODE_ERR_CNT_11",
.address = 0xfb,
},
{
.name = "PCIE_P_DECODE_ERR_CNT_12",
.address = 0xfc,
},
{
.name = "PCIE_P_DECODE_ERR_CNT_13",
.address = 0xfd,
},
{
.name = "PCIE_P_DECODE_ERR_CNT_14",
.address = 0xfe,
},
{
.name = "PCIE_P_DECODE_ERR_CNT_15",
.address = 0xff,
},

486
regs/pcie_registers.txt Normal file
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@ -0,0 +1,486 @@
PCIE_TX_CNTL
PCIEIND:0x1
2-80
PCIE_TX_GART_CNTL
PCIEIND:0x10
2-82
PCIE_TX_GART_DISCARD_RD_ADDR_LO
PCIEIND:0x11
2-82
PCIE_TX_GART_DISCARD_RD_ADDR_HI
PCIEIND:0x12
2-82
PCIE_TX_GART_BASE
PCIEIND:0x13
2-83
PCIE_TX_GART_START_LO
PCIEIND:0x14
2-83
PCIE_TX_GART_START_HI
PCIEIND:0x15
2-83
PCIE_TX_GART_END_LO
PCIEIND:0x16
2-83
PCIE_TX_GART_END_HI
PCIEIND:0x17
2-83
PCIE_TX_GART_ERROR
PCIEIND:0x18
2-83
PCIE_TX_SEQ
PCIEIND:0x2
2-80
PCIE_TX_GART_LRU_MRU_PTR
PCIEIND:0x20
2-84
PCIE_TX_GART_STATUS
PCIEIND:0x21
2-84
PCIE_TX_GART_TLB_VALID
PCIEIND:0x22
2-84
PCIE_TX_GART_TLB0_DATA
PCIEIND:0x23
2-84
PCIE_TX_GART_TLB1_DATA
PCIEIND:0x24
2-84
PCIE_TX_GART_TLB2_DATA
PCIEIND:0x25
2-84
PCIE_TX_GART_TLB3_DATA
PCIEIND:0x26
2-85
PCIE_TX_GART_TLB4_DATA
PCIEIND:0x27
2-85
PCIE_TX_GART_TLB5_DATA
PCIEIND:0x28
2-85
PCIE_TX_GART_TLB6_DATA
PCIEIND:0x29
2-85
PCIE_TX_GART_TLB7_DATA
PCIEIND:0x2A
2-85
PCIE_TX_GART_TLB8_DATA
PCIEIND:0x2B
2-85
PCIE_TX_GART_TLB9_DATA
PCIEIND:0x2C
2-85
PCIE_TX_GART_TLB10_DATA
PCIEIND:0x2D
2-86
PCIE_TX_GART_TLB11_DATA
PCIEIND:0x2E
2-86
PCIE_TX_GART_TLB12_DATA
PCIEIND:0x2F
2-86
PCIE_TX_REPLAY
PCIEIND:0x3
2-80
PCIE_TX_GART_TLB13_DATA
PCIEIND:0x30
2-86
PCIE_TX_GART_TLB14_DATA
PCIEIND:0x31
2-86
PCIE_TX_GART_TLB15_DATA
PCIEIND:0x32
2-86
PCIE_TX_GART_TLB16_DATA
PCIEIND:0x33
2-87
PCIE_TX_GART_TLB17_DATA
PCIEIND:0x34
2-87
PCIE_TX_GART_TLB18_DATA
PCIEIND:0x35
2-87
PCIE_TX_GART_TLB19_DATA
PCIEIND:0x36
2-87
PCIE_TX_GART_TLB20_DATA
PCIEIND:0x37
2-87
PCIE_TX_GART_TLB21_DATA
PCIEIND:0x38
2-87
PCIE_TX_GART_TLB22_DATA
PCIEIND:0x39
2-88
PCIE_TX_GART_TLB23_DATA
PCIEIND:0x3A
2-88
PCIE_TX_GART_TLB24_DATA
PCIEIND:0x3B
2-88
PCIE_TX_GART_TLB25_DATA
PCIEIND:0x3C
2-88
PCIE_TX_GART_TLB26_DATA
PCIEIND:0x3D
2-88
PCIE_TX_GART_TLB27_DATA
PCIEIND:0x3E
2-88
PCIE_TX_GART_TLB28_DATA
PCIEIND:0x3F
2-89
PCIE_TX_CREDITS_CONSUMED
PCIEIND:0x4
2-81
PCIE_TX_GART_TLB29_DATA
PCIEIND:0x40
2-89
PCIE_CLK_CNTL
PCIEIND:0x400
2-107
PCIE_PRBS10
PCIEIND:0x401
2-107
PCIE_PRBS23_BITCNT0
PCIEIND:0x402
2-107
PCIE_PRBS23_BITCNT1
PCIEIND:0x403
2-107
PCIE_PRBS23_BITCNT2
PCIEIND:0x404
2-107
PCIE_PRBS23_BITCNT3
PCIEIND:0x405
2-108
PCIE_PRBS23_BITCNT4
PCIEIND:0x406
2-108
PCIE_PRBS23_BITCNT5
PCIEIND:0x407
2-108
PCIE_PRBS23_BITCNT6
PCIEIND:0x408
2-108
PCIE_PRBS23_BITCNT7
PCIEIND:0x409
2-108
PCIE_PRBS23_BITCNT8
PCIEIND:0x40A
2-108
PCIE_PRBS23_BITCNT9
PCIEIND:0x40B
2-108
PCIE_PRBS23_BITCNT10
PCIEIND:0x40C
2-109
PCIE_PRBS23_BITCNT11
PCIEIND:0x40D
2-109
PCIE_PRBS23_BITCNT12
PCIEIND:0x40E
2-109
PCIE_PRBS23_BITCNT13
PCIEIND:0x40F
2-109
PCIE_TX_GART_TLB30_DATA
PCIEIND:0x41
2-89
PCIE_PRBS23_BITCNT14
PCIEIND:0x410
2-109
PCIE_PRBS23_BITCNT15
PCIEIND:0x411
2-109
PCIE_PRBS23_ERRCNT0
PCIEIND:0x412
2-110
PCIE_PRBS23_ERRCNT1
PCIEIND:0x413
2-110
PCIE_PRBS23_ERRCNT2
PCIEIND:0x414
2-110
PCIE_PRBS23_ERRCNT3
PCIEIND:0x415
2-110
PCIE_PRBS23_ERRCNT4
PCIEIND:0x416
2-110
PCIE_PRBS23_ERRCNT5
PCIEIND:0x417
2-110
PCIE_PRBS23_ERRCNT6
PCIEIND:0x418
2-110
PCIE_PRBS23_ERRCNT7
PCIEIND:0x419
2-111
PCIE_PRBS23_ERRCNT8
PCIEIND:0x41A
2-111
PCIE_PRBS23_ERRCNT9
PCIEIND:0x41B
2-111
PCIE_PRBS23_ERRCNT10
PCIEIND:0x41C
2-111
PCIE_PRBS23_ERRCNT11
PCIEIND:0x41D
2-111
PCIE_PRBS23_ERRCNT12
PCIEIND:0x41E
2-111
PCIE_PRBS23_ERRCNT13
PCIEIND:0x41F
2-111
PCIE_TX_GART_TLB31_DATA
PCIEIND:0x42
2-89
PCIE_PRBS23_ERRCNT14
PCIEIND:0x420
2-112
PCIE_PRBS23_ERRCNT15
PCIEIND:0x421
2-112
PCIE_PRBS23_CTRL0
PCIEIND:0x422
2-112
PCIE_PRBS23_CTRL1
PCIEIND:0x423
2-113
PCIE_PRBS_EN
PCIEIND:0x424
2-113
PCIE_XSTRAP1
PCIEIND:0x425
2-113
PCIE_XSTRAP2
PCIEIND:0x426
2-114
PCIE_XSTRAP5
PCIEIND:0x429
2-114
PCIE_TX_CREDITS_CONSUMED_D
PCIEIND:0x5
2-81
PCIE_TX_CREDITS_CONSUMED_CPLD
PCIEIND:0x6
2-81
PCIE_FLOW_CNTL
PCIEIND:0x60
2-89
PCIE_TXRX_DEBUG_SEQNUM
PCIEIND:0x61
2-90
PCIE_TXRX_TEST_MODE
PCIEIND:0x62
2-90
PCIE_TX_CREDITS_LIMIT
PCIEIND:0x7
2-81
PCIE_RX_CNTL
PCIEIND:0x70
2-90
PCIE_RX_NUM_NACK
PCIEIND:0x71
2-91
PCIE_RX_NUM_NACK_GENERATED
PCIEIND:0x72
2-91
PCIE_RX_ACK_NACK_LATENCY
PCIEIND:0x73
2-91
PCIE_RX_ACK_NACK_LATENCY_THRESHOLD
PCIEIND:0x74
2-91
PCIE_RX_TLP_HDR0
PCIEIND:0x75
2-91
PCIE_RX_TLP_HDR1
PCIEIND:0x76
2-91
PCIE_RX_TLP_HDR2
PCIEIND:0x77
2-91
PCIE_RX_TLP_HDR3
PCIEIND:0x78
2-92
PCIE_RX_TLP_HDR4
PCIEIND:0x79
2-92
PCIE_RX_TLP_CRC
PCIEIND:0x7A
2-92
PCIE_RX_DLP0
PCIEIND:0x7B
2-92
PCIE_RX_DLP1
PCIEIND:0x7C
2-92
PCIE_RX_DLP_CRC
PCIEIND:0x7D
2-92
PCIE_RX_CREDITS_ALLOCATED
PCIEIND:0x7E
2-92
PCIE_RX_CREDITS_ALLOCATED_D
PCIEIND:0x7F
2-93
PCIE_TX_CREDITS_LIMIT_D
PCIEIND:0x8
2-81
PCIE_RX_CREDITS_ALLOCATED_CPLD
PCIEIND:0x80
2-93
PCIE_RX_CREDITS_RECEIVED
PCIEIND:0x81
2-93
PCIE_RX_CREDITS_RECEIVED_D
PCIEIND:0x82
2-93
PCIE_RX_CREDITS_RECEIVED_CPLD
PCIEIND:0x83
2-93
PCIE_RX_MAL_TLP_COUNT
PCIEIND:0x84
2-93
PCIE_RX_ERR_LOG
PCIEIND:0x85
2-94
PCIE_RX_EXPECTED_SEQNUM
PCIEIND:0x86
2-94
PCIE_TX_CREDITS_LIMIT_CPLD
PCIEIND:0x9
2-82
PCIE_CI_CNTL
PCIEIND:0x90
2-94
PCIE_CI_FLUSH_CNTL
PCIEIND:0x91
2-94
PCIE_CI_PANIC
PCIEIND:0x92
2-94
PCIE_CI_HANG
PCIEIND:0x93
2-95
PCIE_LC_CNTL
PCIEIND:0xA0
2-95
PCIE_LC_N_FTS_CNTL
PCIEIND:0xA1
2-95
PCIE_LC_LINK_WIDTH_CNTL
PCIEIND:0xA2
2-97
PCIE_LC_STATE0
PCIEIND:0xA5
2-95
PCIE_LC_STATE1
PCIEIND:0xA6
2-96
PCIE_LC_STATE2
PCIEIND:0xA7
2-96
PCIE_LC_STATE3
PCIEIND:0xA8
2-96
PCIE_LC_STATE4
PCIEIND:0xA9
2-96
PCIE_LC_STATE5
PCIEIND:0xAA
2-96
PCIE_LC_FORCE_SYNC_LOSS_CNTL
PCIEIND:0xAB
2-97
PCIE_P_CNTL
PCIEIND:0xB0
2-97
PCIE_P_CNTL2
PCIEIND:0xB1
2-98
PCIE_P_BUF_STATUS
PCIEIND:0xB2
2-98
PCIE_P_DECODER_STATUS
PCIEIND:0xB3
2-99
PCIE_P_MISC_DEBUG_STATUS
PCIEIND:0xB4
2-100
PCIE_P_IMP_CNTL_STRENGTH
PCIEIND:0xC0
2-101
PCIE_P_IMP_CNTL_UPDATE
PCIEIND:0xC1
2-102
PCIE_P_STR_CNTL_UPDATE
PCIEIND:0xC2
2-102
PCIE_P_PAD_MISC_CNTL
PCIEIND:0xC3
2-102
PCIE_P_SYMSYNC_CTL
PCIEIND:0xC4
2-102
PCIE_P_DECODE_ERR_CNTL
PCIEIND:0xC5
2-103
PCIE_ERR_CNTL
PCIEIND:0xE0
2-105
PCIE_CLK_RST_CNTL
PCIEIND:0xE1
2-105
PCIE_P_DECODE_ERR_CNT_0
PCIEIND:0xF0
2-103
PCIE_P_DECODE_ERR_CNT_1
PCIEIND:0xF1
2-103
PCIE_P_DECODE_ERR_CNT_2
PCIEIND:0xF2
2-103
PCIE_P_DECODE_ERR_CNT_3
PCIEIND:0xF3
2-103
PCIE_P_DECODE_ERR_CNT_4
PCIEIND:0xF4
2-103
PCIE_P_DECODE_ERR_CNT_5
PCIEIND:0xF5
2-103
PCIE_P_DECODE_ERR_CNT_6
PCIEIND:0xF6
2-104
PCIE_P_DECODE_ERR_CNT_7
PCIEIND:0xF7
2-104
PCIE_P_DECODE_ERR_CNT_8
PCIEIND:0xF8
2-104
PCIE_P_DECODE_ERR_CNT_9
PCIEIND:0xF9
2-104
PCIE_P_DECODE_ERR_CNT_10
PCIEIND:0xFA
2-104
PCIE_P_DECODE_ERR_CNT_11
PCIEIND:0xFB
2-104
PCIE_P_DECODE_ERR_CNT_12
PCIEIND:0xFC
2-105
PCIE_P_DECODE_ERR_CNT_13
PCIEIND:0xFD
2-105
PCIE_P_DECODE_ERR_CNT_14
PCIEIND:0xFE
2-105
PCIE_P_DECODE_ERR_CNT_15
PCIEIND:0xFF
2-105

37
regs/rrg_registers.py Normal file
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@ -0,0 +1,37 @@
import sys
with open(sys.argv[1]) as f:
buf = f.read()
prefixes = sys.argv[2:]
assert len(prefixes) >= 1
lines = [line.strip() for line in buf.strip().split()]
assert len(lines) % 3 == 0
def parse(lines):
for i in range(len(lines) // 3):
name = lines[i * 3 + 0]
address = lines[i * 3 + 1]
page = lines[i * 3 + 2]
assert '-' in page, page
orig_address = address
for prefix in prefixes:
if address.startswith(f"{prefix}:"):
address = address.removeprefix(f"{prefix}:")
assert address != orig_address
assert address.startswith("0x")
address = address.removeprefix("0x")
address = int(address, 16)
yield name, address, page
for name, address, page in parse(lines):
print("{")
print(f" .name = \"{name}\",")
print(f" .address = {hex(address)},")
print("},")
#print(f"#define {name} {hex(address)}")