diff --git a/pci_user/main.c b/pci_user/main.c index 3015d37..108d857 100644 --- a/pci_user/main.c +++ b/pci_user/main.c @@ -21,6 +21,41 @@ static inline void wreg(void * rmmio, uint32_t offset, uint32_t value) asm volatile ("" ::: "memory"); } +static inline void wreg_slow(void * rmmio, uint32_t offset, uint32_t value) +{ + #define MM_INDEX 0x0 + #define MM_DATA 0x4 + wreg(rmmio, MM_INDEX, offset); + wreg(rmmio, MM_DATA, value); +} + +static inline uint32_t rreg_slow(void * rmmio, uint32_t offset) +{ + wreg(rmmio, MM_INDEX, offset); + uint32_t value = rreg(rmmio, MM_DATA); + return value; +} + +struct name_address { + const char * name; + const int address; +}; + +const struct name_address display_addresses[] = { + #include "../regs/display_registers.inc" +}; +const int display_addresses_length = (sizeof (display_addresses)) / (sizeof (display_addresses[0])); + +const struct name_address memory_controller_addresses[] = { + #include "../regs/memory_controller_registers.inc" +}; +const int memory_controller_addresses_length = (sizeof (memory_controller_addresses)) / (sizeof (memory_controller_addresses[0])); + +const struct name_address pcie_addresses[] = { + #include "../regs/pcie_registers.inc" +}; +const int pcie_addresses_length = (sizeof (pcie_addresses)) / (sizeof (pcie_addresses[0])); + int main() { //////////////////////////////////////////////////////////////////////// @@ -36,16 +71,47 @@ int main() void * rmmio = resource2_base; - uint32_t value1 = rreg(rmmio, 0x6110); - printf("[r500] D1GRPH_PRIMARY_SURFACE_ADDRESS %08x\n", value1); - uint32_t value2 = rreg(rmmio, 0x6110 + 0x800); - printf("[r500] D2GRPH_PRIMARY_SURFACE_ADDRESS %08x\n", value2); + if (1) { + for (int i = 0; i < display_addresses_length; i++) { + uint32_t value = rreg(rmmio, display_addresses[i].address); + printf("%s %x %08x\n", display_addresses[i].name, display_addresses[i].address, value); + } + } - uint32_t value3 = rreg(rmmio, 0x6118); - printf("[r500] D1GRPH_SECONDARY_SURFACE_ADDRESS %08x\n", value3); - uint32_t value4 = rreg(rmmio, 0x6118 + 0x800); - printf("[r500] D2GRPH_SECONDARY_SURFACE_ADDRESS %08x\n", value4); + if (0) { +#define MC_IND_INDEX 0x70 +#define MC_IND_INDEX__MC_IND_ADDR(x) (((x) & 0xffff) << 0) +#define MC_IND_INDEX__MC_IND_ADDR__CLEAR (~0xffff) +#define MC_IND_DATA 0x74 + // skip MC_IND_INDEX/MC_IND_DATA + const int masks[] = { + (1 << 16), + (1 << 17), + (1 << 20), + (1 << 21), + (1 << 22), + }; - wreg(rmmio, 0x6110, 0x813000); - wreg(rmmio, 0x6118, 0x813000); + for (int i = 2; i < memory_controller_addresses_length; i++) { + const char * name = memory_controller_addresses[i].name; + int address = memory_controller_addresses[i].address; + int mask = (1 << 16) | (1 << 17) | (1 << 20) | (1 << 21) | (1 << 22); + wreg(rmmio, MC_IND_INDEX, MC_IND_INDEX__MC_IND_ADDR(address) | mask); + uint32_t value = rreg(rmmio, MC_IND_DATA); + wreg(rmmio, MC_IND_INDEX, MC_IND_INDEX__MC_IND_ADDR__CLEAR); + printf("%s %x %08x\n", name, address, value); + } + } + + if (0) { +#define PCIE_INDEX 0x30 +#define PCIE_DATA 0x38 + for (int i = 0; i < pcie_addresses_length; i++) { + const char * name = pcie_addresses[i].name; + int address = pcie_addresses[i].address; + wreg_slow(rmmio, PCIE_INDEX, address); + uint32_t value = rreg_slow(rmmio, PCIE_DATA); + printf("%s %x %08x\n", name, address, value); + } + } } diff --git a/regs/display_registers.inc b/regs/display_registers.inc new file mode 100644 index 0000000..ccdfa7d --- /dev/null +++ b/regs/display_registers.inc @@ -0,0 +1,2336 @@ +{ + .name = "GEN_INT_STATUS", + .address = 0x104, +}, +{ + .name = "VGA_RENDER_CONTROL", + .address = 0x300, +}, +{ + .name = "VGA_SEQUENCER_RESET_CONTROL", + .address = 0x304, +}, +{ + .name = "VGA_MODE_CONTROL", + .address = 0x308, +}, +{ + .name = "VGA_SURFACE_PITCH_SELECT", + .address = 0x30c, +}, +{ + .name = "VGA_MEMORY_BASE_ADDRESS", + .address = 0x310, +}, +{ + .name = "VGA_DISPBUF1_SURFACE_ADDR", + .address = 0x318, +}, +{ + .name = "VGA_DISPBUF2_SURFACE_ADDR", + .address = 0x320, +}, +{ + .name = "VGA_HDP_CONTROL", + .address = 0x328, +}, +{ + .name = "VGA_CACHE_CONTROL", + .address = 0x32c, +}, +{ + .name = "D1VGA_CONTROL", + .address = 0x330, +}, +{ + .name = "D2VGA_CONTROL", + .address = 0x338, +}, +{ + .name = "VGA_STATUS", + .address = 0x340, +}, +{ + .name = "VGA_INTERRUPT_CONTROL", + .address = 0x344, +}, +{ + .name = "VGA_STATUS_CLEAR", + .address = 0x348, +}, +{ + .name = "VGA_INTERRUPT_STATUS", + .address = 0x34c, +}, +{ + .name = "VGA_MAIN_CONTROL", + .address = 0x350, +}, +{ + .name = "VGA_TEST_CONTROL", + .address = 0x354, +}, +{ + .name = "VGA_DEBUG_READBACK_INDEX", + .address = 0x358, +}, +{ + .name = "VGA_DEBUG_READBACK_DATA", + .address = 0x35c, +}, +{ + .name = "VGA_MEM_WRITE_PAGE_ADDR", + .address = 0x38, +}, +{ + .name = "CRTC8_IDX", + .address = 0x3b4, +}, +{ + .name = "CRTC8_IDX", + .address = 0x3b4, +}, +{ + .name = "CRTC8_DATA", + .address = 0x3b5, +}, +{ + .name = "CRTC8_DATA", + .address = 0x3b5, +}, +{ + .name = "GENFC_WT", + .address = 0x3ba, +}, +{ + .name = "GENS1", + .address = 0x3ba, +}, +{ + .name = "VGA_MEM_READ_PAGE_ADDR", + .address = 0x3c, +}, +{ + .name = "ATTRDW", + .address = 0x3c0, +}, +{ + .name = "ATTRX", + .address = 0x3c0, +}, +{ + .name = "ATTRDR", + .address = 0x3c1, +}, +{ + .name = "GENMO_WT", + .address = 0x3c2, +}, +{ + .name = "GENMO_WT", + .address = 0x3c2, +}, +{ + .name = "GENS0", + .address = 0x3c2, +}, +{ + .name = "SEQ8_IDX", + .address = 0x3c4, +}, +{ + .name = "SEQ8_IDX", + .address = 0x3c4, +}, +{ + .name = "SEQ8_DATA", + .address = 0x3c5, +}, +{ + .name = "SEQ8_DATA", + .address = 0x3c5, +}, +{ + .name = "DAC_MASK", + .address = 0x3c6, +}, +{ + .name = "DAC_R_INDEX", + .address = 0x3c7, +}, +{ + .name = "DAC_W_INDEX", + .address = 0x3c8, +}, +{ + .name = "DAC_DATA", + .address = 0x3c9, +}, +{ + .name = "GENFC_RD", + .address = 0x3ca, +}, +{ + .name = "GENMO_RD", + .address = 0x3cc, +}, +{ + .name = "GENMO_RD", + .address = 0x3cc, +}, +{ + .name = "GRPH8_IDX", + .address = 0x3ce, +}, +{ + .name = "GRPH8_IDX", + .address = 0x3ce, +}, +{ + .name = "GRPH8_DATA", + .address = 0x3cf, +}, +{ + .name = "GRPH8_DATA", + .address = 0x3cf, +}, +{ + .name = "D1CRTC_H_TOTAL", + .address = 0x6000, +}, +{ + .name = "D1CRTC_H_BLANK_START_END", + .address = 0x6004, +}, +{ + .name = "D1CRTC_H_SYNC_A", + .address = 0x6008, +}, +{ + .name = "D1CRTC_H_SYNC_A_CNTL", + .address = 0x600c, +}, +{ + .name = "D1CRTC_H_SYNC_B", + .address = 0x6010, +}, +{ + .name = "D1CRTC_H_SYNC_B_CNTL", + .address = 0x6014, +}, +{ + .name = "D1CRTC_V_TOTAL", + .address = 0x6020, +}, +{ + .name = "D1CRTC_V_BLANK_START_END", + .address = 0x6024, +}, +{ + .name = "D1CRTC_V_SYNC_A", + .address = 0x6028, +}, +{ + .name = "D1CRTC_V_SYNC_A_CNTL", + .address = 0x602c, +}, +{ + .name = "D1CRTC_V_SYNC_B", + .address = 0x6030, +}, +{ + .name = "D1CRTC_V_SYNC_B_CNTL", + .address = 0x6034, +}, +{ + .name = "D1CRTC_TRIGA_CNTL", + .address = 0x6060, +}, +{ + .name = "D1CRTC_TRIGA_MANUAL_TRIG", + .address = 0x6064, +}, +{ + .name = "D1CRTC_TRIGB_CNTL", + .address = 0x6068, +}, +{ + .name = "D1CRTC_TRIGB_MANUAL_TRIG", + .address = 0x606c, +}, +{ + .name = "D1CRTC_FORCE_COUNT_NOW_CNTL", + .address = 0x6070, +}, +{ + .name = "D1CRTC_FLOW_CONTROL", + .address = 0x6074, +}, +{ + .name = "D1CRTC_PIXEL_DATA_READBACK", + .address = 0x6078, +}, +{ + .name = "D1CRTC_STEREO_FORCE_NEXT_EYE", + .address = 0x607c, +}, +{ + .name = "D1CRTC_CONTROL", + .address = 0x6080, +}, +{ + .name = "D1CRTC_BLANK_CONTROL", + .address = 0x6084, +}, +{ + .name = "D1CRTC_INTERLACE_CONTROL", + .address = 0x6088, +}, +{ + .name = "D1CRTC_INTERLACE_STATUS", + .address = 0x608c, +}, +{ + .name = "D1CRTC_BLANK_DATA_COLOR", + .address = 0x6090, +}, +{ + .name = "D1CRTC_OVERSCAN_COLOR", + .address = 0x6094, +}, +{ + .name = "D1CRTC_BLACK_COLOR", + .address = 0x6098, +}, +{ + .name = "D1CRTC_STATUS", + .address = 0x609c, +}, +{ + .name = "D1CRTC_STATUS_POSITION", + .address = 0x60a0, +}, +{ + .name = "D1CRTC_STATUS_FRAME_COUNT", + .address = 0x60a4, +}, +{ + .name = "D1CRTC_STATUS_VF_COUNT", + .address = 0x60a8, +}, +{ + .name = "D1CRTC_STATUS_HV_COUNT", + .address = 0x60ac, +}, +{ + .name = "D1CRTC_COUNT_RESET", + .address = 0x60b0, +}, +{ + .name = "D1CRTC_COUNT_CONTROL", + .address = 0x60b4, +}, +{ + .name = "D1CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE", + .address = 0x60b8, +}, +{ + .name = "D1CRTC_VERT_SYNC_CONTROL", + .address = 0x60bc, +}, +{ + .name = "D1CRTC_STEREO_STATUS", + .address = 0x60c0, +}, +{ + .name = "D1CRTC_STEREO_CONTROL", + .address = 0x60c4, +}, +{ + .name = "D1CRTC_SNAPSHOT_STATUS", + .address = 0x60c8, +}, +{ + .name = "D1CRTC_SNAPSHOT_CONTROL", + .address = 0x60cc, +}, +{ + .name = "D1CRTC_SNAPSHOT_POSITION", + .address = 0x60d0, +}, +{ + .name = "D1CRTC_SNAPSHOT_FRAME", + .address = 0x60d4, +}, +{ + .name = "D1CRTC_START_LINE_CONTROL", + .address = 0x60d8, +}, +{ + .name = "D1CRTC_INTERRUPT_CONTROL", + .address = 0x60dc, +}, +{ + .name = "D1MODE_MASTER_UPDATE_LOCK", + .address = 0x60e0, +}, +{ + .name = "D1MODE_MASTER_UPDATE_MODE", + .address = 0x60e4, +}, +{ + .name = "D1CRTC_UPDATE_LOCK", + .address = 0x60e8, +}, +{ + .name = "D1CRTC_DOUBLE_BUFFER_CONTROL", + .address = 0x60ec, +}, +{ + .name = "D1CRTC_VGA_PARAMETER_CAPTURE_MODE", + .address = 0x60f0, +}, +{ + .name = "DC_CRTC_MASTER_EN", + .address = 0x60f8, +}, +{ + .name = "DC_CRTC_TV_CONTROL", + .address = 0x60fc, +}, +{ + .name = "D1GRPH_ENABLE", + .address = 0x6100, +}, +{ + .name = "D1GRPH_CONTROL", + .address = 0x6104, +}, +{ + .name = "D1GRPH_LUT_SEL", + .address = 0x6108, +}, +{ + .name = "D1GRPH_PRIMARY_SURFACE_ADDRESS", + .address = 0x6110, +}, +{ + .name = "D1GRPH_SECONDARY_SURFACE_ADDRESS", + .address = 0x6118, +}, +{ + .name = "D1GRPH_PITCH", + .address = 0x6120, +}, +{ + .name = "D1GRPH_SURFACE_OFFSET_X", + .address = 0x6124, +}, +{ + .name = "D1GRPH_SURFACE_OFFSET_Y", + .address = 0x6128, +}, +{ + .name = "D1GRPH_X_START", + .address = 0x612c, +}, +{ + .name = "D1GRPH_Y_START", + .address = 0x6130, +}, +{ + .name = "D1GRPH_X_END", + .address = 0x6134, +}, +{ + .name = "D1GRPH_Y_END", + .address = 0x6138, +}, +{ + .name = "D1COLOR_SPACE_CONVERT", + .address = 0x613c, +}, +{ + .name = "D1OVL_COLOR_MATRIX_TRANSFORMATION_CNTL", + .address = 0x6140, +}, +{ + .name = "D1GRPH_UPDATE", + .address = 0x6144, +}, +{ + .name = "D1GRPH_FLIP_CONTROL", + .address = 0x6148, +}, +{ + .name = "D1GRPH_SURFACE_ADDRESS_INUSE", + .address = 0x614c, +}, +{ + .name = "D1OVL_ENABLE", + .address = 0x6180, +}, +{ + .name = "D1OVL_CONTROL1", + .address = 0x6184, +}, +{ + .name = "D1OVL_CONTROL2", + .address = 0x6188, +}, +{ + .name = "D1OVL_SURFACE_ADDRESS", + .address = 0x6190, +}, +{ + .name = "D1OVL_PITCH", + .address = 0x6198, +}, +{ + .name = "D1OVL_SURFACE_OFFSET_X", + .address = 0x619c, +}, +{ + .name = "D1OVL_SURFACE_OFFSET_Y", + .address = 0x61a0, +}, +{ + .name = "D1OVL_START", + .address = 0x61a4, +}, +{ + .name = "D1OVL_END", + .address = 0x61a8, +}, +{ + .name = "D1OVL_UPDATE", + .address = 0x61ac, +}, +{ + .name = "D1OVL_SURFACE_ADDRESS_INUSE", + .address = 0x61b0, +}, +{ + .name = "D1OVL_MATRIX_TRANSFORM_EN", + .address = 0x6200, +}, +{ + .name = "D1OVL_MATRIX_COEF_1_1", + .address = 0x6204, +}, +{ + .name = "D1OVL_MATRIX_COEF_1_2", + .address = 0x6208, +}, +{ + .name = "D1OVL_MATRIX_COEF_1_3", + .address = 0x620c, +}, +{ + .name = "D1OVL_MATRIX_COEF_1_4", + .address = 0x6210, +}, +{ + .name = "D1OVL_MATRIX_COEF_2_1", + .address = 0x6214, +}, +{ + .name = "D1OVL_MATRIX_COEF_2_2", + .address = 0x6218, +}, +{ + .name = "D1OVL_MATRIX_COEF_2_3", + .address = 0x621c, +}, +{ + .name = "D1OVL_MATRIX_COEF_2_4", + .address = 0x6220, +}, +{ + .name = "D1OVL_MATRIX_COEF_3_1", + .address = 0x6224, +}, +{ + .name = "D1OVL_MATRIX_COEF_3_2", + .address = 0x6228, +}, +{ + .name = "D1OVL_MATRIX_COEF_3_3", + .address = 0x622c, +}, +{ + .name = "D1OVL_MATRIX_COEF_3_4", + .address = 0x6230, +}, +{ + .name = "D1OVL_PWL_TRANSFORM_EN", + .address = 0x6280, +}, +{ + .name = "D1OVL_PWL_0TOF", + .address = 0x6284, +}, +{ + .name = "D1OVL_PWL_10TO1F", + .address = 0x6288, +}, +{ + .name = "D1OVL_PWL_20TO3F", + .address = 0x628c, +}, +{ + .name = "D1OVL_PWL_40TO7F", + .address = 0x6290, +}, +{ + .name = "D1OVL_PWL_80TOBF", + .address = 0x6294, +}, +{ + .name = "D1OVL_PWL_C0TOFF", + .address = 0x6298, +}, +{ + .name = "D1OVL_PWL_100TO13F", + .address = 0x629c, +}, +{ + .name = "D1OVL_PWL_140TO17F", + .address = 0x62a0, +}, +{ + .name = "D1OVL_PWL_180TO1BF", + .address = 0x62a4, +}, +{ + .name = "D1OVL_PWL_1C0TO1FF", + .address = 0x62a8, +}, +{ + .name = "D1OVL_PWL_200TO23F", + .address = 0x62ac, +}, +{ + .name = "D1OVL_PWL_240TO27F", + .address = 0x62b0, +}, +{ + .name = "D1OVL_PWL_280TO2BF", + .address = 0x62b4, +}, +{ + .name = "D1OVL_PWL_2C0TO2FF", + .address = 0x62b8, +}, +{ + .name = "D1OVL_PWL_300TO33F", + .address = 0x62bc, +}, +{ + .name = "D1OVL_PWL_340TO37F", + .address = 0x62c0, +}, +{ + .name = "D1OVL_PWL_380TO3BF", + .address = 0x62c4, +}, +{ + .name = "D1OVL_PWL_3C0TO3FF", + .address = 0x62c8, +}, +{ + .name = "D1OVL_KEY_CONTROL", + .address = 0x6300, +}, +{ + .name = "D1GRPH_ALPHA", + .address = 0x6304, +}, +{ + .name = "D1OVL_ALPHA", + .address = 0x6308, +}, +{ + .name = "D1OVL_ALPHA_CONTROL", + .address = 0x630c, +}, +{ + .name = "D1GRPH_KEY_RANGE_RED", + .address = 0x6310, +}, +{ + .name = "D1GRPH_KEY_RANGE_GREEN", + .address = 0x6314, +}, +{ + .name = "D1GRPH_KEY_RANGE_BLUE", + .address = 0x6318, +}, +{ + .name = "D1GRPH_KEY_RANGE_ALPHA", + .address = 0x631c, +}, +{ + .name = "D1OVL_KEY_RANGE_RED_CR", + .address = 0x6320, +}, +{ + .name = "D1OVL_KEY_RANGE_GREEN_Y", + .address = 0x6324, +}, +{ + .name = "D1OVL_KEY_RANGE_BLUE_CB", + .address = 0x6328, +}, +{ + .name = "D1OVL_KEY_ALPHA", + .address = 0x632c, +}, +{ + .name = "D1GRPH_COLOR_MATRIX_TRANSFORMATION_CNTL", + .address = 0x6380, +}, +{ + .name = "D1COLOR_MATRIX_COEF_1_1", + .address = 0x6384, +}, +{ + .name = "D1COLOR_MATRIX_COEF_1_2", + .address = 0x6388, +}, +{ + .name = "D1COLOR_MATRIX_COEF_1_3", + .address = 0x638c, +}, +{ + .name = "D1COLOR_MATRIX_COEF_1_4", + .address = 0x6390, +}, +{ + .name = "D1COLOR_MATRIX_COEF_2_1", + .address = 0x6394, +}, +{ + .name = "D1COLOR_MATRIX_COEF_2_2", + .address = 0x6398, +}, +{ + .name = "D1COLOR_MATRIX_COEF_2_3", + .address = 0x639c, +}, +{ + .name = "D1COLOR_MATRIX_COEF_2_4", + .address = 0x63a0, +}, +{ + .name = "D1COLOR_MATRIX_COEF_3_1", + .address = 0x63a4, +}, +{ + .name = "D1COLOR_MATRIX_COEF_3_2", + .address = 0x63a8, +}, +{ + .name = "D1COLOR_MATRIX_COEF_3_3", + .address = 0x63ac, +}, +{ + .name = "D1COLOR_MATRIX_COEF_3_4", + .address = 0x63b0, +}, +{ + .name = "D1CUR_CONTROL", + .address = 0x6400, +}, +{ + .name = "D1CUR_SURFACE_ADDRESS", + .address = 0x6408, +}, +{ + .name = "D1CUR_SIZE", + .address = 0x6410, +}, +{ + .name = "D1CUR_POSITION", + .address = 0x6414, +}, +{ + .name = "D1CUR_HOT_SPOT", + .address = 0x6418, +}, +{ + .name = "D1CUR_COLOR1", + .address = 0x641c, +}, +{ + .name = "D1CUR_COLOR2", + .address = 0x6420, +}, +{ + .name = "D1CUR_UPDATE", + .address = 0x6424, +}, +{ + .name = "D1ICON_CONTROL", + .address = 0x6440, +}, +{ + .name = "D1ICON_SURFACE_ADDRESS", + .address = 0x6448, +}, +{ + .name = "D1ICON_SIZE", + .address = 0x6450, +}, +{ + .name = "D1ICON_START_POSITION", + .address = 0x6454, +}, +{ + .name = "D1ICON_COLOR1", + .address = 0x6458, +}, +{ + .name = "D1ICON_COLOR2", + .address = 0x645c, +}, +{ + .name = "D1ICON_UPDATE", + .address = 0x6460, +}, +{ + .name = "DC_LUT_RW_SELECT", + .address = 0x6480, +}, +{ + .name = "DC_LUT_RW_MODE", + .address = 0x6484, +}, +{ + .name = "DC_LUT_RW_INDEX", + .address = 0x6488, +}, +{ + .name = "DC_LUT_SEQ_COLOR", + .address = 0x648c, +}, +{ + .name = "DC_LUT_PWL_DATA", + .address = 0x6490, +}, +{ + .name = "DC_LUT_30_COLOR", + .address = 0x6494, +}, +{ + .name = "DC_LUT_READ_PIPE_SELECT", + .address = 0x6498, +}, +{ + .name = "DC_LUT_WRITE_EN_MASK", + .address = 0x649c, +}, +{ + .name = "DC_LUT_AUTOFILL", + .address = 0x64a0, +}, +{ + .name = "DC_LUTA_CONTROL", + .address = 0x64c0, +}, +{ + .name = "DC_LUTA_BLACK_OFFSET_BLUE", + .address = 0x64c4, +}, +{ + .name = "DC_LUTA_BLACK_OFFSET_GREEN", + .address = 0x64c8, +}, +{ + .name = "DC_LUTA_BLACK_OFFSET_RED", + .address = 0x64cc, +}, +{ + .name = "DC_LUTA_WHITE_OFFSET_BLUE", + .address = 0x64d0, +}, +{ + .name = "DC_LUTA_WHITE_OFFSET_GREEN", + .address = 0x64d4, +}, +{ + .name = "DC_LUTA_WHITE_OFFSET_RED", + .address = 0x64d8, +}, +{ + .name = "D2CRTC_H_TOTAL", + .address = 0x6800, +}, +{ + .name = "D2CRTC_H_BLANK_START_END", + .address = 0x6804, +}, +{ + .name = "D2CRTC_H_SYNC_A", + .address = 0x6808, +}, +{ + .name = "D2CRTC_H_SYNC_A_CNTL", + .address = 0x680c, +}, +{ + .name = "D2CRTC_H_SYNC_B", + .address = 0x6810, +}, +{ + .name = "D2CRTC_H_SYNC_B_CNTL", + .address = 0x6814, +}, +{ + .name = "D2CRTC_V_TOTAL", + .address = 0x6820, +}, +{ + .name = "D2CRTC_V_BLANK_START_END", + .address = 0x6824, +}, +{ + .name = "D2CRTC_V_SYNC_A", + .address = 0x6828, +}, +{ + .name = "D2CRTC_V_SYNC_A_CNTL", + .address = 0x682c, +}, +{ + .name = "D2CRTC_V_SYNC_B", + .address = 0x6830, +}, +{ + .name = "D2CRTC_V_SYNC_B_CNTL", + .address = 0x6834, +}, +{ + .name = "D2CRTC_TRIGA_CNTL", + .address = 0x6860, +}, +{ + .name = "D2CRTC_TRIGA_MANUAL_TRIG", + .address = 0x6864, +}, +{ + .name = "D2CRTC_TRIGB_CNTL", + .address = 0x6868, +}, +{ + .name = "D2CRTC_TRIGB_MANUAL_TRIG", + .address = 0x686c, +}, +{ + .name = "D2CRTC_FORCE_COUNT_NOW_CNTL", + .address = 0x6870, +}, +{ + .name = "D2CRTC_FLOW_CONTROL", + .address = 0x6874, +}, +{ + .name = "D2CRTC_PIXEL_DATA_READBACK", + .address = 0x6878, +}, +{ + .name = "D2CRTC_STEREO_FORCE_NEXT_EYE", + .address = 0x687c, +}, +{ + .name = "D2CRTC_CONTROL", + .address = 0x6880, +}, +{ + .name = "D2CRTC_BLANK_CONTROL", + .address = 0x6884, +}, +{ + .name = "D2CRTC_INTERLACE_CONTROL", + .address = 0x6888, +}, +{ + .name = "D2CRTC_INTERLACE_STATUS", + .address = 0x688c, +}, +{ + .name = "D2CRTC_BLANK_DATA_COLOR", + .address = 0x6890, +}, +{ + .name = "D2CRTC_OVERSCAN_COLOR", + .address = 0x6894, +}, +{ + .name = "D2CRTC_BLACK_COLOR", + .address = 0x6898, +}, +{ + .name = "D2CRTC_STATUS", + .address = 0x689c, +}, +{ + .name = "D2CRTC_STATUS_POSITION", + .address = 0x68a0, +}, +{ + .name = "D2CRTC_STATUS_FRAME_COUNT", + .address = 0x68a4, +}, +{ + .name = "D2CRTC_STATUS_VF_COUNT", + .address = 0x68a8, +}, +{ + .name = "D2CRTC_STATUS_HV_COUNT", + .address = 0x68ac, +}, +{ + .name = "D2CRTC_COUNT_RESET", + .address = 0x68b0, +}, +{ + .name = "D2CRTC_COUNT_CONTROL", + .address = 0x68b4, +}, +{ + .name = "D2CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE", + .address = 0x68b8, +}, +{ + .name = "D2CRTC_VERT_SYNC_CONTROL", + .address = 0x68bc, +}, +{ + .name = "D2CRTC_STEREO_STATUS", + .address = 0x68c0, +}, +{ + .name = "D2CRTC_STEREO_CONTROL", + .address = 0x68c4, +}, +{ + .name = "D2CRTC_SNAPSHOT_STATUS", + .address = 0x68c8, +}, +{ + .name = "D2CRTC_SNAPSHOT_CONTROL", + .address = 0x68cc, +}, +{ + .name = "D2CRTC_SNAPSHOT_POSITION", + .address = 0x68d0, +}, +{ + .name = "D2CRTC_SNAPSHOT_FRAME", + .address = 0x68d4, +}, +{ + .name = "D2CRTC_START_LINE_CONTROL", + .address = 0x68d8, +}, +{ + .name = "D2CRTC_INTERRUPT_CONTROL", + .address = 0x68dc, +}, +{ + .name = "D2MODE_MASTER_UPDATE_LOCK", + .address = 0x68e0, +}, +{ + .name = "D2MODE_MASTER_UPDATE_MODE", + .address = 0x68e4, +}, +{ + .name = "D2CRTC_UPDATE_LOCK", + .address = 0x68e8, +}, +{ + .name = "D2CRTC_DOUBLE_BUFFER_CONTROL", + .address = 0x68ec, +}, +{ + .name = "D2CRTC_VGA_PARAMETER_CAPTURE_MODE", + .address = 0x68f0, +}, +{ + .name = "D2GRPH_ENABLE", + .address = 0x6900, +}, +{ + .name = "D2GRPH_CONTROL", + .address = 0x6904, +}, +{ + .name = "D2GRPH_LUT_SEL", + .address = 0x6908, +}, +{ + .name = "D2GRPH_PRIMARY_SURFACE_ADDRESS", + .address = 0x6910, +}, +{ + .name = "D2GRPH_SECONDARY_SURFACE_ADDRESS", + .address = 0x6918, +}, +{ + .name = "D2GRPH_PITCH", + .address = 0x6920, +}, +{ + .name = "D2GRPH_SURFACE_OFFSET_X", + .address = 0x6924, +}, +{ + .name = "D2GRPH_SURFACE_OFFSET_Y", + .address = 0x6928, +}, +{ + .name = "D2GRPH_X_START", + .address = 0x692c, +}, +{ + .name = "D2GRPH_Y_START", + .address = 0x6930, +}, +{ + .name = "D2GRPH_X_END", + .address = 0x6934, +}, +{ + .name = "D2GRPH_Y_END", + .address = 0x6938, +}, +{ + .name = "D2COLOR_SPACE_CONVERT", + .address = 0x693c, +}, +{ + .name = "D2OVL_COLOR_MATRIX_TRANSFORMATION_CNTL", + .address = 0x6940, +}, +{ + .name = "D2GRPH_UPDATE", + .address = 0x6944, +}, +{ + .name = "D2GRPH_FLIP_CONTROL", + .address = 0x6948, +}, +{ + .name = "D2GRPH_SURFACE_ADDRESS_INUSE", + .address = 0x694c, +}, +{ + .name = "D2OVL_ENABLE", + .address = 0x6980, +}, +{ + .name = "D2OVL_CONTROL1", + .address = 0x6984, +}, +{ + .name = "D2OVL_CONTROL2", + .address = 0x6988, +}, +{ + .name = "D2OVL_SURFACE_ADDRESS", + .address = 0x6990, +}, +{ + .name = "D2OVL_PITCH", + .address = 0x6998, +}, +{ + .name = "D2OVL_SURFACE_OFFSET_X", + .address = 0x699c, +}, +{ + .name = "D2OVL_SURFACE_OFFSET_Y", + .address = 0x69a0, +}, +{ + .name = "D2OVL_START", + .address = 0x69a4, +}, +{ + .name = "D2OVL_END", + .address = 0x69a8, +}, +{ + .name = "D2OVL_UPDATE", + .address = 0x69ac, +}, +{ + .name = "D2OVL_SURFACE_ADDRESS_INUSE", + .address = 0x69b0, +}, +{ + .name = "D2OVL_MATRIX_TRANSFORM_EN", + .address = 0x6a00, +}, +{ + .name = "D2OVL_MATRIX_COEF_1_1", + .address = 0x6a04, +}, +{ + .name = "D2OVL_MATRIX_COEF_1_2", + .address = 0x6a08, +}, +{ + .name = "D2OVL_MATRIX_COEF_1_3", + .address = 0x6a0c, +}, +{ + .name = "D2OVL_MATRIX_COEF_1_4", + .address = 0x6a10, +}, +{ + .name = "D2OVL_MATRIX_COEF_2_1", + .address = 0x6a14, +}, +{ + .name = "D2OVL_MATRIX_COEF_2_2", + .address = 0x6a18, +}, +{ + .name = "D2OVL_MATRIX_COEF_2_3", + .address = 0x6a1c, +}, +{ + .name = "D2OVL_MATRIX_COEF_2_4", + .address = 0x6a20, +}, +{ + .name = "D2OVL_MATRIX_COEF_3_1", + .address = 0x6a24, +}, +{ + .name = "D2OVL_MATRIX_COEF_3_2", + .address = 0x6a28, +}, +{ + .name = "D2OVL_MATRIX_COEF_3_3", + .address = 0x6a2c, +}, +{ + .name = "D2OVL_MATRIX_COEF_3_4", + .address = 0x6a30, +}, +{ + .name = "D2OVL_PWL_TRANSFORM_EN", + .address = 0x6a80, +}, +{ + .name = "D2OVL_PWL_0TOF", + .address = 0x6a84, +}, +{ + .name = "D2OVL_PWL_10TO1F", + .address = 0x6a88, +}, +{ + .name = "D2OVL_PWL_20TO3F", + .address = 0x6a8c, +}, +{ + .name = "D2OVL_PWL_40TO7F", + .address = 0x6a90, +}, +{ + .name = "D2OVL_PWL_80TOBF", + .address = 0x6a94, +}, +{ + .name = "D2OVL_PWL_C0TOFF", + .address = 0x6a98, +}, +{ + .name = "D2OVL_PWL_100TO13F", + .address = 0x6a9c, +}, +{ + .name = "D2OVL_PWL_140TO17F", + .address = 0x6aa0, +}, +{ + .name = "D2OVL_PWL_180TO1BF", + .address = 0x6aa4, +}, +{ + .name = "D2OVL_PWL_1C0TO1FF", + .address = 0x6aa8, +}, +{ + .name = "D2OVL_PWL_200TO23F", + .address = 0x6aac, +}, +{ + .name = "D2OVL_PWL_240TO27F", + .address = 0x6ab0, +}, +{ + .name = "D2OVL_PWL_280TO2BF", + .address = 0x6ab4, +}, +{ + .name = "D2OVL_PWL_2C0TO2FF", + .address = 0x6ab8, +}, +{ + .name = "D2OVL_PWL_300TO33F", + .address = 0x6abc, +}, +{ + .name = "D2OVL_PWL_340TO37F", + .address = 0x6ac0, +}, +{ + .name = "D2OVL_PWL_380TO3BF", + .address = 0x6ac4, +}, +{ + .name = "D2OVL_PWL_3C0TO3FF", + .address = 0x6ac8, +}, +{ + .name = "D2OVL_KEY_CONTROL", + .address = 0x6b00, +}, +{ + .name = "D2GRPH_ALPHA", + .address = 0x6b04, +}, +{ + .name = "D2OVL_ALPHA", + .address = 0x6b08, +}, +{ + .name = "D2OVL_ALPHA_CONTROL", + .address = 0x6b0c, +}, +{ + .name = "D2GRPH_KEY_RANGE_RED", + .address = 0x6b10, +}, +{ + .name = "D2GRPH_KEY_RANGE_GREEN", + .address = 0x6b14, +}, +{ + .name = "D2GRPH_KEY_RANGE_BLUE", + .address = 0x6b18, +}, +{ + .name = "D2GRPH_KEY_RANGE_ALPHA", + .address = 0x6b1c, +}, +{ + .name = "D2OVL_KEY_RANGE_RED_CR", + .address = 0x6b20, +}, +{ + .name = "D2OVL_KEY_RANGE_GREEN_Y", + .address = 0x6b24, +}, +{ + .name = "D2OVL_KEY_RANGE_BLUE_CB", + .address = 0x6b28, +}, +{ + .name = "D2OVL_KEY_ALPHA", + .address = 0x6b2c, +}, +{ + .name = "D2GRPH_COLOR_MATRIX_TRANSFORMATION_CNTL", + .address = 0x6b80, +}, +{ + .name = "D2COLOR_MATRIX_COEF_1_1", + .address = 0x6b84, +}, +{ + .name = "D2COLOR_MATRIX_COEF_1_2", + .address = 0x6b88, +}, +{ + .name = "D2COLOR_MATRIX_COEF_1_3", + .address = 0x6b8c, +}, +{ + .name = "D2COLOR_MATRIX_COEF_1_4", + .address = 0x6b90, +}, +{ + .name = "D2COLOR_MATRIX_COEF_2_1", + .address = 0x6b94, +}, +{ + .name = "D2COLOR_MATRIX_COEF_2_2", + .address = 0x6b98, +}, +{ + .name = "D2COLOR_MATRIX_COEF_2_3", + .address = 0x6b9c, +}, +{ + .name = "D2COLOR_MATRIX_COEF_2_4", + .address = 0x6ba0, +}, +{ + .name = "D2COLOR_MATRIX_COEF_3_1", + .address = 0x6ba4, +}, +{ + .name = "D2COLOR_MATRIX_COEF_3_2", + .address = 0x6ba8, +}, +{ + .name = "D2COLOR_MATRIX_COEF_3_3", + .address = 0x6bac, +}, +{ + .name = "D2COLOR_MATRIX_COEF_3_4", + .address = 0x6bb0, +}, +{ + .name = "D2CUR_CONTROL", + .address = 0x6c00, +}, +{ + .name = "D2CUR_SURFACE_ADDRESS", + .address = 0x6c08, +}, +{ + .name = "D2CUR_SIZE", + .address = 0x6c10, +}, +{ + .name = "D2CUR_POSITION", + .address = 0x6c14, +}, +{ + .name = "D2CUR_HOT_SPOT", + .address = 0x6c18, +}, +{ + .name = "D2CUR_COLOR1", + .address = 0x6c1c, +}, +{ + .name = "D2CUR_COLOR2", + .address = 0x6c20, +}, +{ + .name = "D2CUR_UPDATE", + .address = 0x6c24, +}, +{ + .name = "D2ICON_CONTROL", + .address = 0x6c40, +}, +{ + .name = "D2ICON_SURFACE_ADDRESS", + .address = 0x6c48, +}, +{ + .name = "D2ICON_SIZE", + .address = 0x6c50, +}, +{ + .name = "D2ICON_START_POSITION", + .address = 0x6c54, +}, +{ + .name = "D2ICON_COLOR1", + .address = 0x6c58, +}, +{ + .name = "D2ICON_COLOR2", + .address = 0x6c5c, +}, +{ + .name = "D2ICON_UPDATE", + .address = 0x6c60, +}, +{ + .name = "DCP_CRC_CONTROL", + .address = 0x6c80, +}, +{ + .name = "DCP_CRC_MASK", + .address = 0x6c84, +}, +{ + .name = "DCP_CRC_P0_CURRENT", + .address = 0x6c88, +}, +{ + .name = "DCP_CRC_P1_CURRENT", + .address = 0x6c8c, +}, +{ + .name = "DCP_CRC_P0_LAST", + .address = 0x6c90, +}, +{ + .name = "DCP_CRC_P1_LAST", + .address = 0x6c94, +}, +{ + .name = "DMIF_CONTROL", + .address = 0x6cb0, +}, +{ + .name = "DMIF_STATUS", + .address = 0x6cb4, +}, +{ + .name = "MCIF_CONTROL", + .address = 0x6cb8, +}, +{ + .name = "DCP_LB_DATA_GAP_BETWEEN_CHUNK", + .address = 0x6cbc, +}, +{ + .name = "DC_LUTB_CONTROL", + .address = 0x6cc0, +}, +{ + .name = "DC_LUTB_BLACK_OFFSET_BLUE", + .address = 0x6cc4, +}, +{ + .name = "DC_LUTB_BLACK_OFFSET_GREEN", + .address = 0x6cc8, +}, +{ + .name = "DC_LUTB_BLACK_OFFSET_RED", + .address = 0x6ccc, +}, +{ + .name = "DC_LUTB_WHITE_OFFSET_BLUE", + .address = 0x6cd0, +}, +{ + .name = "DC_LUTB_WHITE_OFFSET_GREEN", + .address = 0x6cd4, +}, +{ + .name = "DC_LUTB_WHITE_OFFSET_RED", + .address = 0x6cd8, +}, +{ + .name = "DACA_ENABLE", + .address = 0x7800, +}, +{ + .name = "DACA_SOURCE_SELECT", + .address = 0x7804, +}, +{ + .name = "DACA_CRC_EN", + .address = 0x7808, +}, +{ + .name = "DACA_CRC_CONTROL", + .address = 0x780c, +}, +{ + .name = "DACA_CRC_SIG_RGB_MASK", + .address = 0x7810, +}, +{ + .name = "DACA_CRC_SIG_CONTROL_MASK", + .address = 0x7814, +}, +{ + .name = "DACA_CRC_SIG_RGB", + .address = 0x7818, +}, +{ + .name = "DACA_CRC_SIG_CONTROL", + .address = 0x781c, +}, +{ + .name = "DACA_SYNC_TRISTATE_CONTROL", + .address = 0x7820, +}, +{ + .name = "DACA_SYNC_SELECT", + .address = 0x7824, +}, +{ + .name = "DACA_AUTODETECT_CONTROL", + .address = 0x7828, +}, +{ + .name = "DACA_AUTODETECT_CONTROL2", + .address = 0x782c, +}, +{ + .name = "DACA_AUTODETECT_STATUS", + .address = 0x7834, +}, +{ + .name = "DACA_AUTODETECT_INT_CONTROL", + .address = 0x7838, +}, +{ + .name = "DACA_FORCE_OUTPUT_CNTL", + .address = 0x783c, +}, +{ + .name = "DACA_FORCE_DATA", + .address = 0x7840, +}, +{ + .name = "DACA_POWERDOWN", + .address = 0x7850, +}, +{ + .name = "DACA_CONTROL1", + .address = 0x7854, +}, +{ + .name = "DACA_CONTROL2", + .address = 0x7858, +}, +{ + .name = "DACA_COMPARATOR_ENABLE", + .address = 0x785c, +}, +{ + .name = "DACA_COMPARATOR_OUTPUT", + .address = 0x7860, +}, +{ + .name = "DACA_TEST_ENABLE", + .address = 0x7864, +}, +{ + .name = "DACA_PWR_CNTL", + .address = 0x7868, +}, +{ + .name = "TMDSA_CNTL", + .address = 0x7880, +}, +{ + .name = "TMDSA_SOURCE_SELECT", + .address = 0x7884, +}, +{ + .name = "TMDSA_COLOR_FORMAT", + .address = 0x7888, +}, +{ + .name = "TMDSA_FORCE_OUTPUT_CNTL", + .address = 0x788c, +}, +{ + .name = "TMDSA_FORCE_DATA", + .address = 0x7890, +}, +{ + .name = "TMDSA_BIT_DEPTH_CONTROL", + .address = 0x7894, +}, +{ + .name = "TMDSA_CONTROL_CHAR", + .address = 0x7898, +}, +{ + .name = "TMDSA_CONTROL0_FEEDBACK", + .address = 0x789c, +}, +{ + .name = "TMDSA_STEREOSYNC_CTL_SEL", + .address = 0x78a0, +}, +{ + .name = "TMDSA_SYNC_CHAR_PATTERN_SEL", + .address = 0x78a4, +}, +{ + .name = "TMDSA_SYNC_CHAR_PATTERN_0_1", + .address = 0x78a8, +}, +{ + .name = "TMDSA_SYNC_CHAR_PATTERN_2_3", + .address = 0x78ac, +}, +{ + .name = "TMDSA_CRC_CNTL", + .address = 0x78b0, +}, +{ + .name = "TMDSA_CRC_SIG_MASK", + .address = 0x78b4, +}, +{ + .name = "TMDSA_CRC_SIG_RGB", + .address = 0x78b8, +}, +{ + .name = "TMDSA_2ND_CRC_RESULT", + .address = 0x78bc, +}, +{ + .name = "TMDSA_TEST_PATTERN", + .address = 0x78c0, +}, +{ + .name = "TMDSA_RANDOM_PATTERN_SEED", + .address = 0x78c4, +}, +{ + .name = "TMDSA_DEBUG", + .address = 0x78c8, +}, +{ + .name = "TMDSA_CTL_BITS", + .address = 0x78cc, +}, +{ + .name = "TMDSA_DCBALANCER_CONTROL", + .address = 0x78d0, +}, +{ + .name = "TMDSA_RED_BLUE_SWITCH", + .address = 0x78d4, +}, +{ + .name = "TMDSA_DATA_SYNCHRONIZATION", + .address = 0x78d8, +}, +{ + .name = "TMDSA_CTL0_1_GEN_CNTL", + .address = 0x78dc, +}, +{ + .name = "TMDSA_CTL2_3_GEN_CNTL", + .address = 0x78e0, +}, +{ + .name = "TMDSA_TRANSMITTER_ENABLE", + .address = 0x7904, +}, +{ + .name = "TMDSA_LOAD_DETECT", + .address = 0x7908, +}, +{ + .name = "TMDSA_MACRO_CONTROL", + .address = 0x790c, +}, +{ + .name = "TMDSA_TRANSMITTER_CONTROL", + .address = 0x7910, +}, +{ + .name = "TMDSA_REG_TEST_OUTPUT", + .address = 0x7914, +}, +{ + .name = "TMDSA_TRANSMITTER_DEBUG", + .address = 0x7918, +}, +{ + .name = "DVOA_ENABLE", + .address = 0x7980, +}, +{ + .name = "DVOA_SOURCE_SELECT", + .address = 0x7984, +}, +{ + .name = "DVOA_BIT_DEPTH_CONTROL", + .address = 0x7988, +}, +{ + .name = "DVOA_OUTPUT", + .address = 0x798c, +}, +{ + .name = "DVOA_CONTROL", + .address = 0x7990, +}, +{ + .name = "DVOA_CRC_EN", + .address = 0x7994, +}, +{ + .name = "DVOA_CRC_CONTROL", + .address = 0x7998, +}, +{ + .name = "DVOA_CRC_SIG_MASK1", + .address = 0x799c, +}, +{ + .name = "DVOA_CRC_SIG_MASK2", + .address = 0x79a0, +}, +{ + .name = "DVOA_CRC_SIG_RESULT1", + .address = 0x79a4, +}, +{ + .name = "DVOA_CRC_SIG_RESULT2", + .address = 0x79a8, +}, +{ + .name = "DVOA_CRC2_SIG_MASK", + .address = 0x79ac, +}, +{ + .name = "DVOA_CRC2_SIG_RESULT", + .address = 0x79b0, +}, +{ + .name = "DVOA_STRENGTH_CONTROL", + .address = 0x79b4, +}, +{ + .name = "DVOA_FORCE_OUTPUT_CNTL", + .address = 0x79b8, +}, +{ + .name = "DVOA_FORCE_DATA", + .address = 0x79bc, +}, +{ + .name = "DACB_ENABLE", + .address = 0x7a00, +}, +{ + .name = "DACB_SOURCE_SELECT", + .address = 0x7a04, +}, +{ + .name = "DACB_CRC_EN", + .address = 0x7a08, +}, +{ + .name = "DACB_CRC_CONTROL", + .address = 0x7a0c, +}, +{ + .name = "DACB_CRC_SIG_RGB_MASK", + .address = 0x7a10, +}, +{ + .name = "DACB_CRC_SIG_CONTROL_MASK", + .address = 0x7a14, +}, +{ + .name = "DACB_CRC_SIG_RGB", + .address = 0x7a18, +}, +{ + .name = "DACB_CRC_SIG_CONTROL", + .address = 0x7a1c, +}, +{ + .name = "DACB_SYNC_TRISTATE_CONTROL", + .address = 0x7a20, +}, +{ + .name = "DACB_SYNC_SELECT", + .address = 0x7a24, +}, +{ + .name = "DACB_AUTODETECT_CONTROL", + .address = 0x7a28, +}, +{ + .name = "DACB_AUTODETECT_CONTROL2", + .address = 0x7a2c, +}, +{ + .name = "DACB_AUTODETECT_STATUS", + .address = 0x7a34, +}, +{ + .name = "DACB_AUTODETECT_INT_CONTROL", + .address = 0x7a38, +}, +{ + .name = "DACB_FORCE_OUTPUT_CNTL", + .address = 0x7a3c, +}, +{ + .name = "DACB_FORCE_DATA", + .address = 0x7a40, +}, +{ + .name = "DACB_POWERDOWN", + .address = 0x7a50, +}, +{ + .name = "DACB_CONTROL1", + .address = 0x7a54, +}, +{ + .name = "DACB_CONTROL2", + .address = 0x7a58, +}, +{ + .name = "DACB_COMPARATOR_ENABLE", + .address = 0x7a5c, +}, +{ + .name = "DACB_COMPARATOR_OUTPUT", + .address = 0x7a60, +}, +{ + .name = "DACB_TEST_ENABLE", + .address = 0x7a64, +}, +{ + .name = "DACB_PWR_CNTL", + .address = 0x7a68, +}, +{ + .name = "LVTMA_CNTL", + .address = 0x7a80, +}, +{ + .name = "LVTMA_SOURCE_SELECT", + .address = 0x7a84, +}, +{ + .name = "LVTMA_COLOR_FORMAT", + .address = 0x7a88, +}, +{ + .name = "LVTMA_FORCE_OUTPUT_CNTL", + .address = 0x7a8c, +}, +{ + .name = "LVTMA_FORCE_DATA", + .address = 0x7a90, +}, +{ + .name = "LVTMA_BIT_DEPTH_CONTROL", + .address = 0x7a94, +}, +{ + .name = "LVTMA_CONTROL_CHAR", + .address = 0x7a98, +}, +{ + .name = "LVTMA_CONTROL0_FEEDBACK", + .address = 0x7a9c, +}, +{ + .name = "LVTMA_STEREOSYNC_CTL_SEL", + .address = 0x7aa0, +}, +{ + .name = "LVTMA_SYNC_CHAR_PATTERN_SEL", + .address = 0x7aa4, +}, +{ + .name = "LVTMA_SYNC_CHAR_PATTERN_0_1", + .address = 0x7aa8, +}, +{ + .name = "LVTMA_SYNC_CHAR_PATTERN_2_3", + .address = 0x7aac, +}, +{ + .name = "LVTMA_CRC_CNTL", + .address = 0x7ab0, +}, +{ + .name = "LVTMA_CRC_SIG_MASK", + .address = 0x7ab4, +}, +{ + .name = "LVTMA_CRC_SIG_RGB", + .address = 0x7ab8, +}, +{ + .name = "LVTMA_2ND_CRC_RESULT", + .address = 0x7abc, +}, +{ + .name = "LVTMA_TEST_PATTERN", + .address = 0x7ac0, +}, +{ + .name = "LVTMA_RANDOM_PATTERN_SEED", + .address = 0x7ac4, +}, +{ + .name = "LVTMA_DEBUG", + .address = 0x7ac8, +}, +{ + .name = "LVTMA_CTL_BITS", + .address = 0x7acc, +}, +{ + .name = "LVTMA_DCBALANCER_CONTROL", + .address = 0x7ad0, +}, +{ + .name = "LVTMA_RED_BLUE_SWITCH", + .address = 0x7ad4, +}, +{ + .name = "LVTMA_DATA_SYNCHRONIZATION", + .address = 0x7ad8, +}, +{ + .name = "LVTMA_CTL0_1_GEN_CNTL", + .address = 0x7adc, +}, +{ + .name = "LVTMA_CTL2_3_GEN_CNTL", + .address = 0x7ae0, +}, +{ + .name = "LVTMA_PWRSEQ_REF_DIV", + .address = 0x7ae4, +}, +{ + .name = "LVTMA_PWRSEQ_DELAY1", + .address = 0x7ae8, +}, +{ + .name = "LVTMA_PWRSEQ_DELAY2", + .address = 0x7aec, +}, +{ + .name = "LVTMA_PWRSEQ_CNTL", + .address = 0x7af0, +}, +{ + .name = "LVTMA_PWRSEQ_STATE", + .address = 0x7af4, +}, +{ + .name = "LVTMA_BL_MOD_CNTL", + .address = 0x7af8, +}, +{ + .name = "LVTMA_LVDS_DATA_CNTL", + .address = 0x7afc, +}, +{ + .name = "LVTMA_MODE", + .address = 0x7b00, +}, +{ + .name = "LVTMA_TRANSMITTER_ENABLE", + .address = 0x7b04, +}, +{ + .name = "LVTMA_LOAD_DETECT", + .address = 0x7b08, +}, +{ + .name = "LVTMA_MACRO_CONTROL", + .address = 0x7b0c, +}, +{ + .name = "LVTMA_TRANSMITTER_CONTROL", + .address = 0x7b10, +}, +{ + .name = "LVTMA_REG_TEST_OUTPUT", + .address = 0x7b14, +}, +{ + .name = "LVTMA_TRANSMITTER_DEBUG", + .address = 0x7b18, +}, +{ + .name = "DC_HOT_PLUG_DETECT1_CONTROL", + .address = 0x7d00, +}, +{ + .name = "DC_HOT_PLUG_DETECT1_INT_STATUS", + .address = 0x7d04, +}, +{ + .name = "DC_HOT_PLUG_DETECT1_INT_CONTROL", + .address = 0x7d08, +}, +{ + .name = "DC_HOT_PLUG_DETECT2_CONTROL", + .address = 0x7d10, +}, +{ + .name = "DC_HOT_PLUG_DETECT2_INT_STATUS", + .address = 0x7d14, +}, +{ + .name = "DC_HOT_PLUG_DETECT2_INT_CONTROL", + .address = 0x7d18, +}, +{ + .name = "DC_HOT_PLUG_DETECT_CLOCK_CONTROL", + .address = 0x7d20, +}, +{ + .name = "DC_I2C_STATUS1", + .address = 0x7d30, +}, +{ + .name = "DC_I2C_RESET", + .address = 0x7d34, +}, +{ + .name = "DC_I2C_CONTROL1", + .address = 0x7d38, +}, +{ + .name = "DC_I2C_CONTROL2", + .address = 0x7d3c, +}, +{ + .name = "DC_I2C_CONTROL3", + .address = 0x7d40, +}, +{ + .name = "DC_I2C_DATA", + .address = 0x7d44, +}, +{ + .name = "DC_I2C_INTERRUPT_CONTROL", + .address = 0x7d48, +}, +{ + .name = "DC_I2C_ARBITRATION", + .address = 0x7d50, +}, +{ + .name = "DC_GENERICA", + .address = 0x7dc0, +}, +{ + .name = "DC_GENERICB", + .address = 0x7dc4, +}, +{ + .name = "DC_PAD_EXTERN_SIG", + .address = 0x7dcc, +}, +{ + .name = "DC_REF_CLK_CNTL", + .address = 0x7dd4, +}, +{ + .name = "DC_GPIO_GENERIC_MASK", + .address = 0x7de0, +}, +{ + .name = "DC_GPIO_GENERIC_A", + .address = 0x7de4, +}, +{ + .name = "DC_GPIO_GENERIC_EN", + .address = 0x7de8, +}, +{ + .name = "DC_GPIO_GENERIC_Y", + .address = 0x7dec, +}, +{ + .name = "DC_GPIO_VIP_DEBUG", + .address = 0x7e2c, +}, +{ + .name = "DC_GPIO_DVODATA_MASK", + .address = 0x7e30, +}, +{ + .name = "DC_GPIO_DVODATA_A", + .address = 0x7e34, +}, +{ + .name = "DC_GPIO_DVODATA_EN", + .address = 0x7e38, +}, +{ + .name = "DC_GPIO_DVODATA_Y", + .address = 0x7e3c, +}, +{ + .name = "DC_GPIO_DDC1_MASK", + .address = 0x7e40, +}, +{ + .name = "DC_GPIO_DDC1_A", + .address = 0x7e44, +}, +{ + .name = "DC_GPIO_DDC1_EN", + .address = 0x7e48, +}, +{ + .name = "DC_GPIO_DDC1_Y", + .address = 0x7e4c, +}, +{ + .name = "DC_GPIO_DDC2_MASK", + .address = 0x7e50, +}, +{ + .name = "DC_GPIO_DDC2_A", + .address = 0x7e54, +}, +{ + .name = "DC_GPIO_DDC2_EN", + .address = 0x7e58, +}, +{ + .name = "DC_GPIO_DDC2_Y", + .address = 0x7e5c, +}, +{ + .name = "DC_GPIO_DDC3_MASK", + .address = 0x7e60, +}, +{ + .name = "DC_GPIO_DDC3_A", + .address = 0x7e64, +}, +{ + .name = "DC_GPIO_DDC3_EN", + .address = 0x7e68, +}, +{ + .name = "DC_GPIO_DDC3_Y", + .address = 0x7e6c, +}, +{ + .name = "DC_GPIO_SYNCA_MASK", + .address = 0x7e70, +}, +{ + .name = "DC_GPIO_SYNCA_A", + .address = 0x7e74, +}, +{ + .name = "DC_GPIO_SYNCA_EN", + .address = 0x7e78, +}, +{ + .name = "DC_GPIO_SYNCA_Y", + .address = 0x7e7c, +}, +{ + .name = "DC_GPIO_SYNCB_MASK", + .address = 0x7e80, +}, +{ + .name = "DC_GPIO_SYNCB_A", + .address = 0x7e84, +}, +{ + .name = "DC_GPIO_SYNCB_EN", + .address = 0x7e88, +}, +{ + .name = "DC_GPIO_SYNCB_Y", + .address = 0x7e8c, +}, +{ + .name = "DC_GPIO_HPD_MASK", + .address = 0x7e90, +}, +{ + .name = "DC_GPIO_HPD_A", + .address = 0x7e94, +}, +{ + .name = "DC_GPIO_HPD_EN", + .address = 0x7e98, +}, +{ + .name = "DC_GPIO_HPD_Y", + .address = 0x7e9c, +}, +{ + .name = "DC_GPIO_PWRSEQ_MASK", + .address = 0x7ea0, +}, +{ + .name = "DC_GPIO_PWRSEQ_A", + .address = 0x7ea4, +}, +{ + .name = "DC_GPIO_PWRSEQ_EN", + .address = 0x7ea8, +}, +{ + .name = "DC_GPIO_PWRSEQ_Y", + .address = 0x7eac, +}, +{ + .name = "CAPTURE_START_STATUS", + .address = 0x7ed0, +}, +{ + .name = "DC_GPIO_PAD_STRENGTH_1", + .address = 0x7ed4, +}, +{ + .name = "DC_GPIO_PAD_STRENGTH_2", + .address = 0x7ed8, +}, +{ + .name = "DISP_INTERRUPT_STATUS", + .address = 0x7edc, +}, +{ + .name = "DOUT_POWER_MANAGEMENT_CNTL", + .address = 0x7ee0, +}, +{ + .name = "DISP_TIMER_CONTROL", + .address = 0x7ef0, +}, +{ + .name = "DO_PERFCOUNTER0_SELECT", + .address = 0x7f00, +}, +{ + .name = "DO_PERFCOUNTER0_HI", + .address = 0x7f04, +}, +{ + .name = "DO_PERFCOUNTER0_LOW", + .address = 0x7f08, +}, +{ + .name = "DO_PERFCOUNTER1_SELECT", + .address = 0x7f0c, +}, +{ + .name = "DO_PERFCOUNTER1_HI", + .address = 0x7f10, +}, +{ + .name = "DO_PERFCOUNTER1_LOW", + .address = 0x7f14, +}, +{ + .name = "DCO_PERFMON_CNTL_R", + .address = 0x7f18, +}, +{ + .name = "CRTC_EXT_CNTL", + .address = 0xe054, +}, diff --git a/regs/display_registers.txt b/regs/display_registers.txt new file mode 100644 index 0000000..57d2f6a --- /dev/null +++ b/regs/display_registers.txt @@ -0,0 +1,1752 @@ +GEN_INT_STATUS +DISPDEC:0x104 +2-339 +VGA_RENDER_CONTROL +DISPDEC:0x300 +2-186 +VGA_SEQUENCER_RESET_CONTROL +DISPDEC:0x304 +2-187 +VGA_MODE_CONTROL +DISPDEC:0x308 +2-187 +VGA_SURFACE_PITCH_SELECT +DISPDEC:0x30C +2-187 +VGA_MEMORY_BASE_ADDRESS +DISPDEC:0x310 +2-188 +VGA_DISPBUF1_SURFACE_ADDR +DISPDEC:0x318 +2-188 +VGA_DISPBUF2_SURFACE_ADDR +DISPDEC:0x320 +2-188 +VGA_HDP_CONTROL +DISPDEC:0x328 +2-188 +VGA_CACHE_CONTROL +DISPDEC:0x32C +2-189 +D1VGA_CONTROL +DISPDEC:0x330 +2-189 +D2VGA_CONTROL +DISPDEC:0x338 +2-190 +VGA_STATUS +DISPDEC:0x340 +2-190 +VGA_INTERRUPT_CONTROL +DISPDEC:0x344 +2-191 +VGA_STATUS_CLEAR +DISPDEC:0x348 +2-191 +VGA_INTERRUPT_STATUS +DISPDEC:0x34C +2-191 +VGA_MAIN_CONTROL +DISPDEC:0x350 +2-192 +VGA_TEST_CONTROL +DISPDEC:0x354 +2-193 +VGA_DEBUG_READBACK_INDEX +DISPDEC:0x358 +2-193 +VGA_DEBUG_READBACK_DATA +DISPDEC:0x35C +2-194 +VGA_MEM_WRITE_PAGE_ADDR +DISPDEC:0x38 +2-197 +CRTC8_IDX +DISPDEC:0x3B4 +2-171 +CRTC8_IDX +DISPDEC:0x3B4 +2-196 +CRTC8_DATA +DISPDEC:0x3B5 +2-171 +CRTC8_DATA +DISPDEC:0x3B5 +2-196 +GENFC_WT +DISPDEC:0x3BA +2-165 +GENS1 +DISPDEC:0x3BA +2-167 +VGA_MEM_READ_PAGE_ADDR +DISPDEC:0x3C +2-197 +ATTRDW +DISPDEC:0x3C0 +2-181 +ATTRX +DISPDEC:0x3C0 +2-181 +ATTRDR +DISPDEC:0x3C1 +2-181 +GENMO_WT +DISPDEC:0x3C2 +2-165 +GENMO_WT +DISPDEC:0x3C2 +2-194 +GENS0 +DISPDEC:0x3C2 +2-166 +SEQ8_IDX +DISPDEC:0x3C4 +2-170 +SEQ8_IDX +DISPDEC:0x3C4 +2-195 +SEQ8_DATA +DISPDEC:0x3C5 +2-170 +SEQ8_DATA +DISPDEC:0x3C5 +2-195 +DAC_MASK +DISPDEC:0x3C6 +2-168 +DAC_R_INDEX +DISPDEC:0x3C7 +2-168 +DAC_W_INDEX +DISPDEC:0x3C8 +2-168 +DAC_DATA +DISPDEC:0x3C9 +2-168 +GENFC_RD +DISPDEC:0x3CA +2-165 +GENMO_RD +DISPDEC:0x3CC +2-166 +GENMO_RD +DISPDEC:0x3CC +2-195 +GRPH8_IDX +DISPDEC:0x3CE +2-178 +GRPH8_IDX +DISPDEC:0x3CE +2-196 +GRPH8_DATA +DISPDEC:0x3CF +2-178 +GRPH8_DATA +DISPDEC:0x3CF +2-196 +D1CRTC_H_TOTAL +DISPDEC:0x6000 +2-267 +D1CRTC_H_BLANK_START_END +DISPDEC:0x6004 +2-267 +D1CRTC_H_SYNC_A +DISPDEC:0x6008 +2-267 +D1CRTC_H_SYNC_A_CNTL +DISPDEC:0x600C +2-267 +D1CRTC_H_SYNC_B +DISPDEC:0x6010 +2-268 +D1CRTC_H_SYNC_B_CNTL +DISPDEC:0x6014 +2-268 +D1CRTC_V_TOTAL +DISPDEC:0x6020 +2-268 +D1CRTC_V_BLANK_START_END +DISPDEC:0x6024 +2-268 +D1CRTC_V_SYNC_A +DISPDEC:0x6028 +2-269 +D1CRTC_V_SYNC_A_CNTL +DISPDEC:0x602C +2-269 +D1CRTC_V_SYNC_B +DISPDEC:0x6030 +2-269 +D1CRTC_V_SYNC_B_CNTL +DISPDEC:0x6034 +2-269 +D1CRTC_TRIGA_CNTL +DISPDEC:0x6060 +2-270 +D1CRTC_TRIGA_MANUAL_TRIG +DISPDEC:0x6064 +2-271 +D1CRTC_TRIGB_CNTL +DISPDEC:0x6068 +2-271 +D1CRTC_TRIGB_MANUAL_TRIG +DISPDEC:0x606C +2-272 +D1CRTC_FORCE_COUNT_NOW_CNTL +DISPDEC:0x6070 +2-272 +D1CRTC_FLOW_CONTROL +DISPDEC:0x6074 +2-272 +D1CRTC_PIXEL_DATA_READBACK +DISPDEC:0x6078 +2-273 +D1CRTC_STEREO_FORCE_NEXT_EYE +DISPDEC:0x607C +2-273 +D1CRTC_CONTROL +DISPDEC:0x6080 +2-273 +D1CRTC_BLANK_CONTROL +DISPDEC:0x6084 +2-274 +D1CRTC_INTERLACE_CONTROL +DISPDEC:0x6088 +2-274 +D1CRTC_INTERLACE_STATUS +DISPDEC:0x608C +2-274 +D1CRTC_BLANK_DATA_COLOR +DISPDEC:0x6090 +2-275 +D1CRTC_OVERSCAN_COLOR +DISPDEC:0x6094 +2-275 +D1CRTC_BLACK_COLOR +DISPDEC:0x6098 +2-275 +D1CRTC_STATUS +DISPDEC:0x609C +2-275 +D1CRTC_STATUS_POSITION +DISPDEC:0x60A0 +2-276 +D1CRTC_STATUS_FRAME_COUNT +DISPDEC:0x60A4 +2-276 +D1CRTC_STATUS_VF_COUNT +DISPDEC:0x60A8 +2-276 +D1CRTC_STATUS_HV_COUNT +DISPDEC:0x60AC +2-276 +D1CRTC_COUNT_RESET +DISPDEC:0x60B0 +2-276 +D1CRTC_COUNT_CONTROL +DISPDEC:0x60B4 +2-276 +D1CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE +DISPDEC:0x60B8 +2-276 +D1CRTC_VERT_SYNC_CONTROL +DISPDEC:0x60BC +2-277 +D1CRTC_STEREO_STATUS +DISPDEC:0x60C0 +2-277 +D1CRTC_STEREO_CONTROL +DISPDEC:0x60C4 +2-277 +D1CRTC_SNAPSHOT_STATUS +DISPDEC:0x60C8 +2-278 +D1CRTC_SNAPSHOT_CONTROL +DISPDEC:0x60CC +2-278 +D1CRTC_SNAPSHOT_POSITION +DISPDEC:0x60D0 +2-278 +D1CRTC_SNAPSHOT_FRAME +DISPDEC:0x60D4 +2-278 +D1CRTC_START_LINE_CONTROL +DISPDEC:0x60D8 +2-278 +D1CRTC_INTERRUPT_CONTROL +DISPDEC:0x60DC +2-278 +D1MODE_MASTER_UPDATE_LOCK +DISPDEC:0x60E0 +2-279 +D1MODE_MASTER_UPDATE_MODE +DISPDEC:0x60E4 +2-279 +D1CRTC_UPDATE_LOCK +DISPDEC:0x60E8 +2-279 +D1CRTC_DOUBLE_BUFFER_CONTROL +DISPDEC:0x60EC +2-280 +D1CRTC_VGA_PARAMETER_CAPTURE_MODE +DISPDEC:0x60F0 +2-280 +DC_CRTC_MASTER_EN +DISPDEC:0x60F8 +2-280 +DC_CRTC_TV_CONTROL +DISPDEC:0x60FC +2-280 +D1GRPH_ENABLE +DISPDEC:0x6100 +2-198 +D1GRPH_CONTROL +DISPDEC:0x6104 +2-198 +D1GRPH_LUT_SEL +DISPDEC:0x6108 +2-199 +D1GRPH_PRIMARY_SURFACE_ADDRESS +DISPDEC:0x6110 +2-199 +D1GRPH_SECONDARY_SURFACE_ADDRESS +DISPDEC:0x6118 +2-200 +D1GRPH_PITCH +DISPDEC:0x6120 +2-200 +D1GRPH_SURFACE_OFFSET_X +DISPDEC:0x6124 +2-200 +D1GRPH_SURFACE_OFFSET_Y +DISPDEC:0x6128 +2-200 +D1GRPH_X_START +DISPDEC:0x612C +2-200 +D1GRPH_Y_START +DISPDEC:0x6130 +2-201 +D1GRPH_X_END +DISPDEC:0x6134 +2-201 +D1GRPH_Y_END +DISPDEC:0x6138 +2-201 +D1COLOR_SPACE_CONVERT +DISPDEC:0x613C +2-221 +D1OVL_COLOR_MATRIX_TRANSFORMATION_CNTL +DISPDEC:0x6140 +2-217 +D1GRPH_UPDATE +DISPDEC:0x6144 +2-201 +D1GRPH_FLIP_CONTROL +DISPDEC:0x6148 +2-202 +D1GRPH_SURFACE_ADDRESS_INUSE +DISPDEC:0x614C +2-202 +D1OVL_ENABLE +DISPDEC:0x6180 +2-203 +D1OVL_CONTROL1 +DISPDEC:0x6184 +2-203 +D1OVL_CONTROL2 +DISPDEC:0x6188 +2-203 +D1OVL_SURFACE_ADDRESS +DISPDEC:0x6190 +2-204 +D1OVL_PITCH +DISPDEC:0x6198 +2-204 +D1OVL_SURFACE_OFFSET_X +DISPDEC:0x619C +2-204 +D1OVL_SURFACE_OFFSET_Y +DISPDEC:0x61A0 +2-204 +D1OVL_START +DISPDEC:0x61A4 +2-204 +D1OVL_END +DISPDEC:0x61A8 +2-205 +D1OVL_UPDATE +DISPDEC:0x61AC +2-205 +D1OVL_SURFACE_ADDRESS_INUSE +DISPDEC:0x61B0 +2-205 +D1OVL_MATRIX_TRANSFORM_EN +DISPDEC:0x6200 +2-206 +D1OVL_MATRIX_COEF_1_1 +DISPDEC:0x6204 +2-206 +D1OVL_MATRIX_COEF_1_2 +DISPDEC:0x6208 +2-206 +D1OVL_MATRIX_COEF_1_3 +DISPDEC:0x620C +2-206 +D1OVL_MATRIX_COEF_1_4 +DISPDEC:0x6210 +2-206 +D1OVL_MATRIX_COEF_2_1 +DISPDEC:0x6214 +2-207 +D1OVL_MATRIX_COEF_2_2 +DISPDEC:0x6218 +2-207 +D1OVL_MATRIX_COEF_2_3 +DISPDEC:0x621C +2-207 +D1OVL_MATRIX_COEF_2_4 +DISPDEC:0x6220 +2-207 +D1OVL_MATRIX_COEF_3_1 +DISPDEC:0x6224 +2-207 +D1OVL_MATRIX_COEF_3_2 +DISPDEC:0x6228 +2-208 +D1OVL_MATRIX_COEF_3_3 +DISPDEC:0x622C +2-208 +D1OVL_MATRIX_COEF_3_4 +DISPDEC:0x6230 +2-208 +D1OVL_PWL_TRANSFORM_EN +DISPDEC:0x6280 +2-209 +D1OVL_PWL_0TOF +DISPDEC:0x6284 +2-209 +D1OVL_PWL_10TO1F +DISPDEC:0x6288 +2-209 +D1OVL_PWL_20TO3F +DISPDEC:0x628C +2-209 +D1OVL_PWL_40TO7F +DISPDEC:0x6290 +2-209 +D1OVL_PWL_80TOBF +DISPDEC:0x6294 +2-210 +D1OVL_PWL_C0TOFF +DISPDEC:0x6298 +2-210 +D1OVL_PWL_100TO13F +DISPDEC:0x629C +2-210 +D1OVL_PWL_140TO17F +DISPDEC:0x62A0 +2-210 +D1OVL_PWL_180TO1BF +DISPDEC:0x62A4 +2-210 +D1OVL_PWL_1C0TO1FF +DISPDEC:0x62A8 +2-210 +D1OVL_PWL_200TO23F +DISPDEC:0x62AC +2-211 +D1OVL_PWL_240TO27F +DISPDEC:0x62B0 +2-211 +D1OVL_PWL_280TO2BF +DISPDEC:0x62B4 +2-211 +D1OVL_PWL_2C0TO2FF +DISPDEC:0x62B8 +2-211 +D1OVL_PWL_300TO33F +DISPDEC:0x62BC +2-211 +D1OVL_PWL_340TO37F +DISPDEC:0x62C0 +2-212 +D1OVL_PWL_380TO3BF +DISPDEC:0x62C4 +2-212 +D1OVL_PWL_3C0TO3FF +DISPDEC:0x62C8 +2-212 +D1OVL_KEY_CONTROL +DISPDEC:0x6300 +2-213 +D1GRPH_ALPHA +DISPDEC:0x6304 +2-213 +D1OVL_ALPHA +DISPDEC:0x6308 +2-213 +D1OVL_ALPHA_CONTROL +DISPDEC:0x630C +2-214 +D1GRPH_KEY_RANGE_RED +DISPDEC:0x6310 +2-214 +D1GRPH_KEY_RANGE_GREEN +DISPDEC:0x6314 +2-214 +D1GRPH_KEY_RANGE_BLUE +DISPDEC:0x6318 +2-215 +D1GRPH_KEY_RANGE_ALPHA +DISPDEC:0x631C +2-215 +D1OVL_KEY_RANGE_RED_CR +DISPDEC:0x6320 +2-215 +D1OVL_KEY_RANGE_GREEN_Y +DISPDEC:0x6324 +2-215 +D1OVL_KEY_RANGE_BLUE_CB +DISPDEC:0x6328 +2-216 +D1OVL_KEY_ALPHA +DISPDEC:0x632C +2-216 +D1GRPH_COLOR_MATRIX_TRANSFORMATION_CNTL +DISPDEC:0x6380 +2-217 +D1COLOR_MATRIX_COEF_1_1 +DISPDEC:0x6384 +2-217 +D1COLOR_MATRIX_COEF_1_2 +DISPDEC:0x6388 +2-217 +D1COLOR_MATRIX_COEF_1_3 +DISPDEC:0x638C +2-218 +D1COLOR_MATRIX_COEF_1_4 +DISPDEC:0x6390 +2-218 +D1COLOR_MATRIX_COEF_2_1 +DISPDEC:0x6394 +2-218 +D1COLOR_MATRIX_COEF_2_2 +DISPDEC:0x6398 +2-218 +D1COLOR_MATRIX_COEF_2_3 +DISPDEC:0x639C +2-218 +D1COLOR_MATRIX_COEF_2_4 +DISPDEC:0x63A0 +2-219 +D1COLOR_MATRIX_COEF_3_1 +DISPDEC:0x63A4 +2-219 +D1COLOR_MATRIX_COEF_3_2 +DISPDEC:0x63A8 +2-219 +D1COLOR_MATRIX_COEF_3_3 +DISPDEC:0x63AC +2-219 +D1COLOR_MATRIX_COEF_3_4 +DISPDEC:0x63B0 +2-220 +D1CUR_CONTROL +DISPDEC:0x6400 +2-222 +D1CUR_SURFACE_ADDRESS +DISPDEC:0x6408 +2-222 +D1CUR_SIZE +DISPDEC:0x6410 +2-222 +D1CUR_POSITION +DISPDEC:0x6414 +2-222 +D1CUR_HOT_SPOT +DISPDEC:0x6418 +2-223 +D1CUR_COLOR1 +DISPDEC:0x641C +2-223 +D1CUR_COLOR2 +DISPDEC:0x6420 +2-223 +D1CUR_UPDATE +DISPDEC:0x6424 +2-223 +D1ICON_CONTROL +DISPDEC:0x6440 +2-224 +D1ICON_SURFACE_ADDRESS +DISPDEC:0x6448 +2-224 +D1ICON_SIZE +DISPDEC:0x6450 +2-224 +D1ICON_START_POSITION +DISPDEC:0x6454 +2-224 +D1ICON_COLOR1 +DISPDEC:0x6458 +2-224 +D1ICON_COLOR2 +DISPDEC:0x645C +2-225 +D1ICON_UPDATE +DISPDEC:0x6460 +2-225 +DC_LUT_RW_SELECT +DISPDEC:0x6480 +2-226 +DC_LUT_RW_MODE +DISPDEC:0x6484 +2-226 +DC_LUT_RW_INDEX +DISPDEC:0x6488 +2-226 +DC_LUT_SEQ_COLOR +DISPDEC:0x648C +2-226 +DC_LUT_PWL_DATA +DISPDEC:0x6490 +2-226 +DC_LUT_30_COLOR +DISPDEC:0x6494 +2-227 +DC_LUT_READ_PIPE_SELECT +DISPDEC:0x6498 +2-227 +DC_LUT_WRITE_EN_MASK +DISPDEC:0x649C +2-227 +DC_LUT_AUTOFILL +DISPDEC:0x64A0 +2-227 +DC_LUTA_CONTROL +DISPDEC:0x64C0 +2-228 +DC_LUTA_BLACK_OFFSET_BLUE +DISPDEC:0x64C4 +2-229 +DC_LUTA_BLACK_OFFSET_GREEN +DISPDEC:0x64C8 +2-229 +DC_LUTA_BLACK_OFFSET_RED +DISPDEC:0x64CC +2-229 +DC_LUTA_WHITE_OFFSET_BLUE +DISPDEC:0x64D0 +2-230 +DC_LUTA_WHITE_OFFSET_GREEN +DISPDEC:0x64D4 +2-230 +DC_LUTA_WHITE_OFFSET_RED +DISPDEC:0x64D8 +2-230 +D2CRTC_H_TOTAL +DISPDEC:0x6800 +2-280 +D2CRTC_H_BLANK_START_END +DISPDEC:0x6804 +2-281 +D2CRTC_H_SYNC_A +DISPDEC:0x6808 +2-281 +D2CRTC_H_SYNC_A_CNTL +DISPDEC:0x680C +2-281 +D2CRTC_H_SYNC_B +DISPDEC:0x6810 +2-281 +D2CRTC_H_SYNC_B_CNTL +DISPDEC:0x6814 +2-282 +D2CRTC_V_TOTAL +DISPDEC:0x6820 +2-282 +D2CRTC_V_BLANK_START_END +DISPDEC:0x6824 +2-282 +D2CRTC_V_SYNC_A +DISPDEC:0x6828 +2-282 +D2CRTC_V_SYNC_A_CNTL +DISPDEC:0x682C +2-283 +D2CRTC_V_SYNC_B +DISPDEC:0x6830 +2-283 +D2CRTC_V_SYNC_B_CNTL +DISPDEC:0x6834 +2-283 +D2CRTC_TRIGA_CNTL +DISPDEC:0x6860 +2-283 +D2CRTC_TRIGA_MANUAL_TRIG +DISPDEC:0x6864 +2-284 +D2CRTC_TRIGB_CNTL +DISPDEC:0x6868 +2-285 +D2CRTC_TRIGB_MANUAL_TRIG +DISPDEC:0x686C +2-286 +D2CRTC_FORCE_COUNT_NOW_CNTL +DISPDEC:0x6870 +2-286 +D2CRTC_FLOW_CONTROL +DISPDEC:0x6874 +2-286 +D2CRTC_PIXEL_DATA_READBACK +DISPDEC:0x6878 +2-287 +D2CRTC_STEREO_FORCE_NEXT_EYE +DISPDEC:0x687C +2-287 +D2CRTC_CONTROL +DISPDEC:0x6880 +2-287 +D2CRTC_BLANK_CONTROL +DISPDEC:0x6884 +2-287 +D2CRTC_INTERLACE_CONTROL +DISPDEC:0x6888 +2-288 +D2CRTC_INTERLACE_STATUS +DISPDEC:0x688C +2-288 +D2CRTC_BLANK_DATA_COLOR +DISPDEC:0x6890 +2-288 +D2CRTC_OVERSCAN_COLOR +DISPDEC:0x6894 +2-288 +D2CRTC_BLACK_COLOR +DISPDEC:0x6898 +2-289 +D2CRTC_STATUS +DISPDEC:0x689C +2-289 +D2CRTC_STATUS_POSITION +DISPDEC:0x68A0 +2-289 +D2CRTC_STATUS_FRAME_COUNT +DISPDEC:0x68A4 +2-290 +D2CRTC_STATUS_VF_COUNT +DISPDEC:0x68A8 +2-290 +D2CRTC_STATUS_HV_COUNT +DISPDEC:0x68AC +2-290 +D2CRTC_COUNT_RESET +DISPDEC:0x68B0 +2-290 +D2CRTC_COUNT_CONTROL +DISPDEC:0x68B4 +2-290 +D2CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE +DISPDEC:0x68B8 +2-290 +D2CRTC_VERT_SYNC_CONTROL +DISPDEC:0x68BC +2-290 +D2CRTC_STEREO_STATUS +DISPDEC:0x68C0 +2-291 +D2CRTC_STEREO_CONTROL +DISPDEC:0x68C4 +2-291 +D2CRTC_SNAPSHOT_STATUS +DISPDEC:0x68C8 +2-291 +D2CRTC_SNAPSHOT_CONTROL +DISPDEC:0x68CC +2-292 +D2CRTC_SNAPSHOT_POSITION +DISPDEC:0x68D0 +2-292 +D2CRTC_SNAPSHOT_FRAME +DISPDEC:0x68D4 +2-292 +D2CRTC_START_LINE_CONTROL +DISPDEC:0x68D8 +2-292 +D2CRTC_INTERRUPT_CONTROL +DISPDEC:0x68DC +2-292 +D2MODE_MASTER_UPDATE_LOCK +DISPDEC:0x68E0 +2-293 +D2MODE_MASTER_UPDATE_MODE +DISPDEC:0x68E4 +2-293 +D2CRTC_UPDATE_LOCK +DISPDEC:0x68E8 +2-293 +D2CRTC_DOUBLE_BUFFER_CONTROL +DISPDEC:0x68EC +2-293 +D2CRTC_VGA_PARAMETER_CAPTURE_MODE +DISPDEC:0x68F0 +2-294 +D2GRPH_ENABLE +DISPDEC:0x6900 +2-231 +D2GRPH_CONTROL +DISPDEC:0x6904 +2-231 +D2GRPH_LUT_SEL +DISPDEC:0x6908 +2-232 +D2GRPH_PRIMARY_SURFACE_ADDRESS +DISPDEC:0x6910 +2-232 +D2GRPH_SECONDARY_SURFACE_ADDRESS +DISPDEC:0x6918 +2-233 +D2GRPH_PITCH +DISPDEC:0x6920 +2-233 +D2GRPH_SURFACE_OFFSET_X +DISPDEC:0x6924 +2-233 +D2GRPH_SURFACE_OFFSET_Y +DISPDEC:0x6928 +2-233 +D2GRPH_X_START +DISPDEC:0x692C +2-233 +D2GRPH_Y_START +DISPDEC:0x6930 +2-234 +D2GRPH_X_END +DISPDEC:0x6934 +2-234 +D2GRPH_Y_END +DISPDEC:0x6938 +2-234 +D2COLOR_SPACE_CONVERT +DISPDEC:0x693C +2-254 +D2OVL_COLOR_MATRIX_TRANSFORMATION_CNTL +DISPDEC:0x6940 +2-250 +D2GRPH_UPDATE +DISPDEC:0x6944 +2-234 +D2GRPH_FLIP_CONTROL +DISPDEC:0x6948 +2-235 +D2GRPH_SURFACE_ADDRESS_INUSE +DISPDEC:0x694C +2-235 +D2OVL_ENABLE +DISPDEC:0x6980 +2-236 +D2OVL_CONTROL1 +DISPDEC:0x6984 +2-236 +D2OVL_CONTROL2 +DISPDEC:0x6988 +2-236 +D2OVL_SURFACE_ADDRESS +DISPDEC:0x6990 +2-237 +D2OVL_PITCH +DISPDEC:0x6998 +2-237 +D2OVL_SURFACE_OFFSET_X +DISPDEC:0x699C +2-237 +D2OVL_SURFACE_OFFSET_Y +DISPDEC:0x69A0 +2-237 +D2OVL_START +DISPDEC:0x69A4 +2-237 +D2OVL_END +DISPDEC:0x69A8 +2-238 +D2OVL_UPDATE +DISPDEC:0x69AC +2-238 +D2OVL_SURFACE_ADDRESS_INUSE +DISPDEC:0x69B0 +2-238 +D2OVL_MATRIX_TRANSFORM_EN +DISPDEC:0x6A00 +2-239 +D2OVL_MATRIX_COEF_1_1 +DISPDEC:0x6A04 +2-239 +D2OVL_MATRIX_COEF_1_2 +DISPDEC:0x6A08 +2-239 +D2OVL_MATRIX_COEF_1_3 +DISPDEC:0x6A0C +2-239 +D2OVL_MATRIX_COEF_1_4 +DISPDEC:0x6A10 +2-239 +D2OVL_MATRIX_COEF_2_1 +DISPDEC:0x6A14 +2-240 +D2OVL_MATRIX_COEF_2_2 +DISPDEC:0x6A18 +2-240 +D2OVL_MATRIX_COEF_2_3 +DISPDEC:0x6A1C +2-240 +D2OVL_MATRIX_COEF_2_4 +DISPDEC:0x6A20 +2-240 +D2OVL_MATRIX_COEF_3_1 +DISPDEC:0x6A24 +2-240 +D2OVL_MATRIX_COEF_3_2 +DISPDEC:0x6A28 +2-241 +D2OVL_MATRIX_COEF_3_3 +DISPDEC:0x6A2C +2-241 +D2OVL_MATRIX_COEF_3_4 +DISPDEC:0x6A30 +2-241 +D2OVL_PWL_TRANSFORM_EN +DISPDEC:0x6A80 +2-242 +D2OVL_PWL_0TOF +DISPDEC:0x6A84 +2-242 +D2OVL_PWL_10TO1F +DISPDEC:0x6A88 +2-242 +D2OVL_PWL_20TO3F +DISPDEC:0x6A8C +2-242 +D2OVL_PWL_40TO7F +DISPDEC:0x6A90 +2-242 +D2OVL_PWL_80TOBF +DISPDEC:0x6A94 +2-243 +D2OVL_PWL_C0TOFF +DISPDEC:0x6A98 +2-243 +D2OVL_PWL_100TO13F +DISPDEC:0x6A9C +2-243 +D2OVL_PWL_140TO17F +DISPDEC:0x6AA0 +2-243 +D2OVL_PWL_180TO1BF +DISPDEC:0x6AA4 +2-243 +D2OVL_PWL_1C0TO1FF +DISPDEC:0x6AA8 +2-243 +D2OVL_PWL_200TO23F +DISPDEC:0x6AAC +2-244 +D2OVL_PWL_240TO27F +DISPDEC:0x6AB0 +2-244 +D2OVL_PWL_280TO2BF +DISPDEC:0x6AB4 +2-244 +D2OVL_PWL_2C0TO2FF +DISPDEC:0x6AB8 +2-244 +D2OVL_PWL_300TO33F +DISPDEC:0x6ABC +2-244 +D2OVL_PWL_340TO37F +DISPDEC:0x6AC0 +2-245 +D2OVL_PWL_380TO3BF +DISPDEC:0x6AC4 +2-245 +D2OVL_PWL_3C0TO3FF +DISPDEC:0x6AC8 +2-245 +D2OVL_KEY_CONTROL +DISPDEC:0x6B00 +2-246 +D2GRPH_ALPHA +DISPDEC:0x6B04 +2-246 +D2OVL_ALPHA +DISPDEC:0x6B08 +2-246 +D2OVL_ALPHA_CONTROL +DISPDEC:0x6B0C +2-247 +D2GRPH_KEY_RANGE_RED +DISPDEC:0x6B10 +2-247 +D2GRPH_KEY_RANGE_GREEN +DISPDEC:0x6B14 +2-247 +D2GRPH_KEY_RANGE_BLUE +DISPDEC:0x6B18 +2-248 +D2GRPH_KEY_RANGE_ALPHA +DISPDEC:0x6B1C +2-248 +D2OVL_KEY_RANGE_RED_CR +DISPDEC:0x6B20 +2-248 +D2OVL_KEY_RANGE_GREEN_Y +DISPDEC:0x6B24 +2-248 +D2OVL_KEY_RANGE_BLUE_CB +DISPDEC:0x6B28 +2-248 +D2OVL_KEY_ALPHA +DISPDEC:0x6B2C +2-249 +D2GRPH_COLOR_MATRIX_TRANSFORMATION_CNTL +DISPDEC:0x6B80 +2-250 +D2COLOR_MATRIX_COEF_1_1 +DISPDEC:0x6B84 +2-250 +D2COLOR_MATRIX_COEF_1_2 +DISPDEC:0x6B88 +2-250 +D2COLOR_MATRIX_COEF_1_3 +DISPDEC:0x6B8C +2-250 +D2COLOR_MATRIX_COEF_1_4 +DISPDEC:0x6B90 +2-251 +D2COLOR_MATRIX_COEF_2_1 +DISPDEC:0x6B94 +2-251 +D2COLOR_MATRIX_COEF_2_2 +DISPDEC:0x6B98 +2-251 +D2COLOR_MATRIX_COEF_2_3 +DISPDEC:0x6B9C +2-251 +D2COLOR_MATRIX_COEF_2_4 +DISPDEC:0x6BA0 +2-252 +D2COLOR_MATRIX_COEF_3_1 +DISPDEC:0x6BA4 +2-252 +D2COLOR_MATRIX_COEF_3_2 +DISPDEC:0x6BA8 +2-252 +D2COLOR_MATRIX_COEF_3_3 +DISPDEC:0x6BAC +2-252 +D2COLOR_MATRIX_COEF_3_4 +DISPDEC:0x6BB0 +2-253 +D2CUR_CONTROL +DISPDEC:0x6C00 +2-255 +D2CUR_SURFACE_ADDRESS +DISPDEC:0x6C08 +2-255 +D2CUR_SIZE +DISPDEC:0x6C10 +2-255 +D2CUR_POSITION +DISPDEC:0x6C14 +2-255 +D2CUR_HOT_SPOT +DISPDEC:0x6C18 +2-256 +D2CUR_COLOR1 +DISPDEC:0x6C1C +2-256 +D2CUR_COLOR2 +DISPDEC:0x6C20 +2-256 +D2CUR_UPDATE +DISPDEC:0x6C24 +2-256 +D2ICON_CONTROL +DISPDEC:0x6C40 +2-257 +D2ICON_SURFACE_ADDRESS +DISPDEC:0x6C48 +2-257 +D2ICON_SIZE +DISPDEC:0x6C50 +2-257 +D2ICON_START_POSITION +DISPDEC:0x6C54 +2-257 +D2ICON_COLOR1 +DISPDEC:0x6C58 +2-257 +D2ICON_COLOR2 +DISPDEC:0x6C5C +2-258 +D2ICON_UPDATE +DISPDEC:0x6C60 +2-258 +DCP_CRC_CONTROL +DISPDEC:0x6C80 +2-262 +DCP_CRC_MASK +DISPDEC:0x6C84 +2-262 +DCP_CRC_P0_CURRENT +DISPDEC:0x6C88 +2-262 +DCP_CRC_P1_CURRENT +DISPDEC:0x6C8C +2-262 +DCP_CRC_P0_LAST +DISPDEC:0x6C90 +2-262 +DCP_CRC_P1_LAST +DISPDEC:0x6C94 +2-263 +DMIF_CONTROL +DISPDEC:0x6CB0 +2-264 +DMIF_STATUS +DISPDEC:0x6CB4 +2-264 +MCIF_CONTROL +DISPDEC:0x6CB8 +2-265 +DCP_LB_DATA_GAP_BETWEEN_CHUNK +DISPDEC:0x6CBC +2-266 +DC_LUTB_CONTROL +DISPDEC:0x6CC0 +2-259 +DC_LUTB_BLACK_OFFSET_BLUE +DISPDEC:0x6CC4 +2-260 +DC_LUTB_BLACK_OFFSET_GREEN +DISPDEC:0x6CC8 +2-260 +DC_LUTB_BLACK_OFFSET_RED +DISPDEC:0x6CCC +2-260 +DC_LUTB_WHITE_OFFSET_BLUE +DISPDEC:0x6CD0 +2-261 +DC_LUTB_WHITE_OFFSET_GREEN +DISPDEC:0x6CD4 +2-261 +DC_LUTB_WHITE_OFFSET_RED +DISPDEC:0x6CD8 +2-261 +DACA_ENABLE +DISPDEC:0x7800 +2-295 +DACA_SOURCE_SELECT +DISPDEC:0x7804 +2-295 +DACA_CRC_EN +DISPDEC:0x7808 +2-295 +DACA_CRC_CONTROL +DISPDEC:0x780C +2-295 +DACA_CRC_SIG_RGB_MASK +DISPDEC:0x7810 +2-295 +DACA_CRC_SIG_CONTROL_MASK +DISPDEC:0x7814 +2-296 +DACA_CRC_SIG_RGB +DISPDEC:0x7818 +2-296 +DACA_CRC_SIG_CONTROL +DISPDEC:0x781C +2-296 +DACA_SYNC_TRISTATE_CONTROL +DISPDEC:0x7820 +2-296 +DACA_SYNC_SELECT +DISPDEC:0x7824 +2-296 +DACA_AUTODETECT_CONTROL +DISPDEC:0x7828 +2-297 +DACA_AUTODETECT_CONTROL2 +DISPDEC:0x782C +2-297 +DACA_AUTODETECT_STATUS +DISPDEC:0x7834 +2-297 +DACA_AUTODETECT_INT_CONTROL +DISPDEC:0x7838 +2-298 +DACA_FORCE_OUTPUT_CNTL +DISPDEC:0x783C +2-298 +DACA_FORCE_DATA +DISPDEC:0x7840 +2-298 +DACA_POWERDOWN +DISPDEC:0x7850 +2-298 +DACA_CONTROL1 +DISPDEC:0x7854 +2-298 +DACA_CONTROL2 +DISPDEC:0x7858 +2-299 +DACA_COMPARATOR_ENABLE +DISPDEC:0x785C +2-299 +DACA_COMPARATOR_OUTPUT +DISPDEC:0x7860 +2-300 +DACA_TEST_ENABLE +DISPDEC:0x7864 +2-300 +DACA_PWR_CNTL +DISPDEC:0x7868 +2-300 +TMDSA_CNTL +DISPDEC:0x7880 +2-306 +TMDSA_SOURCE_SELECT +DISPDEC:0x7884 +2-306 +TMDSA_COLOR_FORMAT +DISPDEC:0x7888 +2-307 +TMDSA_FORCE_OUTPUT_CNTL +DISPDEC:0x788C +2-307 +TMDSA_FORCE_DATA +DISPDEC:0x7890 +2-307 +TMDSA_BIT_DEPTH_CONTROL +DISPDEC:0x7894 +2-307 +TMDSA_CONTROL_CHAR +DISPDEC:0x7898 +2-308 +TMDSA_CONTROL0_FEEDBACK +DISPDEC:0x789C +2-308 +TMDSA_STEREOSYNC_CTL_SEL +DISPDEC:0x78A0 +2-308 +TMDSA_SYNC_CHAR_PATTERN_SEL +DISPDEC:0x78A4 +2-308 +TMDSA_SYNC_CHAR_PATTERN_0_1 +DISPDEC:0x78A8 +2-308 +TMDSA_SYNC_CHAR_PATTERN_2_3 +DISPDEC:0x78AC +2-309 +TMDSA_CRC_CNTL +DISPDEC:0x78B0 +2-309 +TMDSA_CRC_SIG_MASK +DISPDEC:0x78B4 +2-309 +TMDSA_CRC_SIG_RGB +DISPDEC:0x78B8 +2-309 +TMDSA_2ND_CRC_RESULT +DISPDEC:0x78BC +2-310 +TMDSA_TEST_PATTERN +DISPDEC:0x78C0 +2-310 +TMDSA_RANDOM_PATTERN_SEED +DISPDEC:0x78C4 +2-310 +TMDSA_DEBUG +DISPDEC:0x78C8 +2-311 +TMDSA_CTL_BITS +DISPDEC:0x78CC +2-311 +TMDSA_DCBALANCER_CONTROL +DISPDEC:0x78D0 +2-311 +TMDSA_RED_BLUE_SWITCH +DISPDEC:0x78D4 +2-311 +TMDSA_DATA_SYNCHRONIZATION +DISPDEC:0x78D8 +2-311 +TMDSA_CTL0_1_GEN_CNTL +DISPDEC:0x78DC +2-312 +TMDSA_CTL2_3_GEN_CNTL +DISPDEC:0x78E0 +2-313 +TMDSA_TRANSMITTER_ENABLE +DISPDEC:0x7904 +2-314 +TMDSA_LOAD_DETECT +DISPDEC:0x7908 +2-315 +TMDSA_MACRO_CONTROL +DISPDEC:0x790C +2-315 +TMDSA_TRANSMITTER_CONTROL +DISPDEC:0x7910 +2-315 +TMDSA_REG_TEST_OUTPUT +DISPDEC:0x7914 +2-316 +TMDSA_TRANSMITTER_DEBUG +DISPDEC:0x7918 +2-316 +DVOA_ENABLE +DISPDEC:0x7980 +2-316 +DVOA_SOURCE_SELECT +DISPDEC:0x7984 +2-317 +DVOA_BIT_DEPTH_CONTROL +DISPDEC:0x7988 +2-317 +DVOA_OUTPUT +DISPDEC:0x798C +2-317 +DVOA_CONTROL +DISPDEC:0x7990 +2-318 +DVOA_CRC_EN +DISPDEC:0x7994 +2-318 +DVOA_CRC_CONTROL +DISPDEC:0x7998 +2-318 +DVOA_CRC_SIG_MASK1 +DISPDEC:0x799C +2-319 +DVOA_CRC_SIG_MASK2 +DISPDEC:0x79A0 +2-319 +DVOA_CRC_SIG_RESULT1 +DISPDEC:0x79A4 +2-319 +DVOA_CRC_SIG_RESULT2 +DISPDEC:0x79A8 +2-319 +DVOA_CRC2_SIG_MASK +DISPDEC:0x79AC +2-319 +DVOA_CRC2_SIG_RESULT +DISPDEC:0x79B0 +2-319 +DVOA_STRENGTH_CONTROL +DISPDEC:0x79B4 +2-320 +DVOA_FORCE_OUTPUT_CNTL +DISPDEC:0x79B8 +2-320 +DVOA_FORCE_DATA +DISPDEC:0x79BC +2-320 +DACB_ENABLE +DISPDEC:0x7A00 +2-300 +DACB_SOURCE_SELECT +DISPDEC:0x7A04 +2-300 +DACB_CRC_EN +DISPDEC:0x7A08 +2-301 +DACB_CRC_CONTROL +DISPDEC:0x7A0C +2-301 +DACB_CRC_SIG_RGB_MASK +DISPDEC:0x7A10 +2-301 +DACB_CRC_SIG_CONTROL_MASK +DISPDEC:0x7A14 +2-301 +DACB_CRC_SIG_RGB +DISPDEC:0x7A18 +2-301 +DACB_CRC_SIG_CONTROL +DISPDEC:0x7A1C +2-302 +DACB_SYNC_TRISTATE_CONTROL +DISPDEC:0x7A20 +2-302 +DACB_SYNC_SELECT +DISPDEC:0x7A24 +2-302 +DACB_AUTODETECT_CONTROL +DISPDEC:0x7A28 +2-302 +DACB_AUTODETECT_CONTROL2 +DISPDEC:0x7A2C +2-302 +DACB_AUTODETECT_STATUS +DISPDEC:0x7A34 +2-303 +DACB_AUTODETECT_INT_CONTROL +DISPDEC:0x7A38 +2-303 +DACB_FORCE_OUTPUT_CNTL +DISPDEC:0x7A3C +2-303 +DACB_FORCE_DATA +DISPDEC:0x7A40 +2-304 +DACB_POWERDOWN +DISPDEC:0x7A50 +2-304 +DACB_CONTROL1 +DISPDEC:0x7A54 +2-304 +DACB_CONTROL2 +DISPDEC:0x7A58 +2-304 +DACB_COMPARATOR_ENABLE +DISPDEC:0x7A5C +2-305 +DACB_COMPARATOR_OUTPUT +DISPDEC:0x7A60 +2-305 +DACB_TEST_ENABLE +DISPDEC:0x7A64 +2-305 +DACB_PWR_CNTL +DISPDEC:0x7A68 +2-306 +LVTMA_CNTL +DISPDEC:0x7A80 +2-340 +LVTMA_SOURCE_SELECT +DISPDEC:0x7A84 +2-340 +LVTMA_COLOR_FORMAT +DISPDEC:0x7A88 +2-341 +LVTMA_FORCE_OUTPUT_CNTL +DISPDEC:0x7A8C +2-341 +LVTMA_FORCE_DATA +DISPDEC:0x7A90 +2-341 +LVTMA_BIT_DEPTH_CONTROL +DISPDEC:0x7A94 +2-341 +LVTMA_CONTROL_CHAR +DISPDEC:0x7A98 +2-342 +LVTMA_CONTROL0_FEEDBACK +DISPDEC:0x7A9C +2-342 +LVTMA_STEREOSYNC_CTL_SEL +DISPDEC:0x7AA0 +2-342 +LVTMA_SYNC_CHAR_PATTERN_SEL +DISPDEC:0x7AA4 +2-342 +LVTMA_SYNC_CHAR_PATTERN_0_1 +DISPDEC:0x7AA8 +2-342 +LVTMA_SYNC_CHAR_PATTERN_2_3 +DISPDEC:0x7AAC +2-343 +LVTMA_CRC_CNTL +DISPDEC:0x7AB0 +2-343 +LVTMA_CRC_SIG_MASK +DISPDEC:0x7AB4 +2-343 +LVTMA_CRC_SIG_RGB +DISPDEC:0x7AB8 +2-344 +LVTMA_2ND_CRC_RESULT +DISPDEC:0x7ABC +2-344 +LVTMA_TEST_PATTERN +DISPDEC:0x7AC0 +2-344 +LVTMA_RANDOM_PATTERN_SEED +DISPDEC:0x7AC4 +2-345 +LVTMA_DEBUG +DISPDEC:0x7AC8 +2-345 +LVTMA_CTL_BITS +DISPDEC:0x7ACC +2-345 +LVTMA_DCBALANCER_CONTROL +DISPDEC:0x7AD0 +2-345 +LVTMA_RED_BLUE_SWITCH +DISPDEC:0x7AD4 +2-345 +LVTMA_DATA_SYNCHRONIZATION +DISPDEC:0x7AD8 +2-346 +LVTMA_CTL0_1_GEN_CNTL +DISPDEC:0x7ADC +2-346 +LVTMA_CTL2_3_GEN_CNTL +DISPDEC:0x7AE0 +2-347 +LVTMA_PWRSEQ_REF_DIV +DISPDEC:0x7AE4 +2-348 +LVTMA_PWRSEQ_DELAY1 +DISPDEC:0x7AE8 +2-348 +LVTMA_PWRSEQ_DELAY2 +DISPDEC:0x7AEC +2-349 +LVTMA_PWRSEQ_CNTL +DISPDEC:0x7AF0 +2-349 +LVTMA_PWRSEQ_STATE +DISPDEC:0x7AF4 +2-350 +LVTMA_BL_MOD_CNTL +DISPDEC:0x7AF8 +2-350 +LVTMA_LVDS_DATA_CNTL +DISPDEC:0x7AFC +2-351 +LVTMA_MODE +DISPDEC:0x7B00 +2-351 +LVTMA_TRANSMITTER_ENABLE +DISPDEC:0x7B04 +2-351 +LVTMA_LOAD_DETECT +DISPDEC:0x7B08 +2-352 +LVTMA_MACRO_CONTROL +DISPDEC:0x7B0C +2-352 +LVTMA_TRANSMITTER_CONTROL +DISPDEC:0x7B10 +2-353 +LVTMA_REG_TEST_OUTPUT +DISPDEC:0x7B14 +2-354 +LVTMA_TRANSMITTER_DEBUG +DISPDEC:0x7B18 +2-354 +DC_HOT_PLUG_DETECT1_CONTROL +DISPDEC:0x7D00 +2-320 +DC_HOT_PLUG_DETECT1_INT_STATUS +DISPDEC:0x7D04 +2-321 +DC_HOT_PLUG_DETECT1_INT_CONTROL +DISPDEC:0x7D08 +2-321 +DC_HOT_PLUG_DETECT2_CONTROL +DISPDEC:0x7D10 +2-321 +DC_HOT_PLUG_DETECT2_INT_STATUS +DISPDEC:0x7D14 +2-321 +DC_HOT_PLUG_DETECT2_INT_CONTROL +DISPDEC:0x7D18 +2-321 +DC_HOT_PLUG_DETECT_CLOCK_CONTROL +DISPDEC:0x7D20 +2-322 +DC_I2C_STATUS1 +DISPDEC:0x7D30 +2-322 +DC_I2C_RESET +DISPDEC:0x7D34 +2-322 +DC_I2C_CONTROL1 +DISPDEC:0x7D38 +2-322 +DC_I2C_CONTROL2 +DISPDEC:0x7D3C +2-323 +DC_I2C_CONTROL3 +DISPDEC:0x7D40 +2-323 +DC_I2C_DATA +DISPDEC:0x7D44 +2-323 +DC_I2C_INTERRUPT_CONTROL +DISPDEC:0x7D48 +2-323 +DC_I2C_ARBITRATION +DISPDEC:0x7D50 +2-324 +DC_GENERICA +DISPDEC:0x7DC0 +2-324 +DC_GENERICB +DISPDEC:0x7DC4 +2-325 +DC_PAD_EXTERN_SIG +DISPDEC:0x7DCC +2-325 +DC_REF_CLK_CNTL +DISPDEC:0x7DD4 +2-325 +DC_GPIO_GENERIC_MASK +DISPDEC:0x7DE0 +2-326 +DC_GPIO_GENERIC_A +DISPDEC:0x7DE4 +2-326 +DC_GPIO_GENERIC_EN +DISPDEC:0x7DE8 +2-326 +DC_GPIO_GENERIC_Y +DISPDEC:0x7DEC +2-326 +DC_GPIO_VIP_DEBUG +DISPDEC:0x7E2C +2-326 +DC_GPIO_DVODATA_MASK +DISPDEC:0x7E30 +2-327 +DC_GPIO_DVODATA_A +DISPDEC:0x7E34 +2-327 +DC_GPIO_DVODATA_EN +DISPDEC:0x7E38 +2-327 +DC_GPIO_DVODATA_Y +DISPDEC:0x7E3C +2-327 +DC_GPIO_DDC1_MASK +DISPDEC:0x7E40 +2-328 +DC_GPIO_DDC1_A +DISPDEC:0x7E44 +2-328 +DC_GPIO_DDC1_EN +DISPDEC:0x7E48 +2-328 +DC_GPIO_DDC1_Y +DISPDEC:0x7E4C +2-328 +DC_GPIO_DDC2_MASK +DISPDEC:0x7E50 +2-328 +DC_GPIO_DDC2_A +DISPDEC:0x7E54 +2-329 +DC_GPIO_DDC2_EN +DISPDEC:0x7E58 +2-329 +DC_GPIO_DDC2_Y +DISPDEC:0x7E5C +2-329 +DC_GPIO_DDC3_MASK +DISPDEC:0x7E60 +2-329 +DC_GPIO_DDC3_A +DISPDEC:0x7E64 +2-329 +DC_GPIO_DDC3_EN +DISPDEC:0x7E68 +2-330 +DC_GPIO_DDC3_Y +DISPDEC:0x7E6C +2-330 +DC_GPIO_SYNCA_MASK +DISPDEC:0x7E70 +2-330 +DC_GPIO_SYNCA_A +DISPDEC:0x7E74 +2-330 +DC_GPIO_SYNCA_EN +DISPDEC:0x7E78 +2-330 +DC_GPIO_SYNCA_Y +DISPDEC:0x7E7C +2-331 +DC_GPIO_SYNCB_MASK +DISPDEC:0x7E80 +2-331 +DC_GPIO_SYNCB_A +DISPDEC:0x7E84 +2-331 +DC_GPIO_SYNCB_EN +DISPDEC:0x7E88 +2-331 +DC_GPIO_SYNCB_Y +DISPDEC:0x7E8C +2-331 +DC_GPIO_HPD_MASK +DISPDEC:0x7E90 +2-331 +DC_GPIO_HPD_A +DISPDEC:0x7E94 +2-332 +DC_GPIO_HPD_EN +DISPDEC:0x7E98 +2-332 +DC_GPIO_HPD_Y +DISPDEC:0x7E9C +2-332 +DC_GPIO_PWRSEQ_MASK +DISPDEC:0x7EA0 +2-332 +DC_GPIO_PWRSEQ_A +DISPDEC:0x7EA4 +2-332 +DC_GPIO_PWRSEQ_EN +DISPDEC:0x7EA8 +2-333 +DC_GPIO_PWRSEQ_Y +DISPDEC:0x7EAC +2-333 +CAPTURE_START_STATUS +DISPDEC:0x7ED0 +2-333 +DC_GPIO_PAD_STRENGTH_1 +DISPDEC:0x7ED4 +2-334 +DC_GPIO_PAD_STRENGTH_2 +DISPDEC:0x7ED8 +2-334 +DISP_INTERRUPT_STATUS +DISPDEC:0x7EDC +2-335 +DOUT_POWER_MANAGEMENT_CNTL +DISPDEC:0x7EE0 +2-336 +DISP_TIMER_CONTROL +DISPDEC:0x7EF0 +2-337 +DO_PERFCOUNTER0_SELECT +DISPDEC:0x7F00 +2-338 +DO_PERFCOUNTER0_HI +DISPDEC:0x7F04 +2-338 +DO_PERFCOUNTER0_LOW +DISPDEC:0x7F08 +2-338 +DO_PERFCOUNTER1_SELECT +DISPDEC:0x7F0C +2-338 +DO_PERFCOUNTER1_HI +DISPDEC:0x7F10 +2-338 +DO_PERFCOUNTER1_LOW +DISPDEC:0x7F14 +2-338 +DCO_PERFMON_CNTL_R +DISPDEC:0x7F18 +2-339 +CRTC_EXT_CNTL +DISPDEC:0xE054 +2-196 diff --git a/regs/memory_controller_registers.inc b/regs/memory_controller_registers.inc new file mode 100644 index 0000000..036b48b --- /dev/null +++ b/regs/memory_controller_registers.inc @@ -0,0 +1,628 @@ +{ + .name = "MC_IND_INDEX", + .address = 0x70, +}, +{ + .name = "MC_IND_DATA", + .address = 0x74, +}, +{ + .name = "MC_STATUS", + .address = 0x0, +}, +{ + .name = "MC_ARB_MIN", + .address = 0x10, +}, +{ + .name = "MC_PT0_CNTL", + .address = 0x100, +}, +{ + .name = "MC_PT0_CONTEXT0_CNTL", + .address = 0x102, +}, +{ + .name = "MC_PT0_CONTEXT1_CNTL", + .address = 0x103, +}, +{ + .name = "MC_PT0_CONTEXT2_CNTL", + .address = 0x104, +}, +{ + .name = "MC_PT0_CONTEXT3_CNTL", + .address = 0x105, +}, +{ + .name = "MC_PT0_CONTEXT4_CNTL", + .address = 0x106, +}, +{ + .name = "MC_PT0_CONTEXT5_CNTL", + .address = 0x107, +}, +{ + .name = "MC_PT0_CONTEXT6_CNTL", + .address = 0x108, +}, +{ + .name = "MC_PT0_CONTEXT7_CNTL", + .address = 0x109, +}, +{ + .name = "MC_PT0_SYSTEM_APERTURE_LOW_ADDR", + .address = 0x112, +}, +{ + .name = "MC_PT0_SYSTEM_APERTURE_HIGH_ADDR", + .address = 0x114, +}, +{ + .name = "MC_PT0_SURFACE_PROBE", + .address = 0x116, +}, +{ + .name = "MC_PT0_SURFACE_PROBE_FAULT_STATUS", + .address = 0x118, +}, +{ + .name = "MC_PT0_PROTECTION_FAULT_STATUS", + .address = 0x11a, +}, +{ + .name = "MC_PT0_CONTEXT0_DEFAULT_READ_ADDR", + .address = 0x11c, +}, +{ + .name = "MC_PT0_CONTEXT1_DEFAULT_READ_ADDR", + .address = 0x11d, +}, +{ + .name = "MC_PT0_CONTEXT2_DEFAULT_READ_ADDR", + .address = 0x11e, +}, +{ + .name = "MC_PT0_CONTEXT3_DEFAULT_READ_ADDR", + .address = 0x11f, +}, +{ + .name = "MC_ARB_TIMERS", + .address = 0x12, +}, +{ + .name = "MC_PT0_CONTEXT4_DEFAULT_READ_ADDR", + .address = 0x120, +}, +{ + .name = "MC_PT0_CONTEXT5_DEFAULT_READ_ADDR", + .address = 0x121, +}, +{ + .name = "MC_PT0_CONTEXT6_DEFAULT_READ_ADDR", + .address = 0x122, +}, +{ + .name = "MC_PT0_CONTEXT7_DEFAULT_READ_ADDR", + .address = 0x123, +}, +{ + .name = "MC_PT0_CONTEXT0_FLAT_BASE_ADDR", + .address = 0x12c, +}, +{ + .name = "MC_PT0_CONTEXT1_FLAT_BASE_ADDR", + .address = 0x12d, +}, +{ + .name = "MC_PT0_CONTEXT2_FLAT_BASE_ADDR", + .address = 0x12e, +}, +{ + .name = "MC_PT0_CONTEXT3_FLAT_BASE_ADDR", + .address = 0x12f, +}, +{ + .name = "MC_ARB_DRAM_PENALTIES", + .address = 0x13, +}, +{ + .name = "MC_PT0_CONTEXT4_FLAT_BASE_ADDR", + .address = 0x130, +}, +{ + .name = "MC_PT0_CONTEXT5_FLAT_BASE_ADDR", + .address = 0x131, +}, +{ + .name = "MC_PT0_CONTEXT6_FLAT_BASE_ADDR", + .address = 0x132, +}, +{ + .name = "MC_PT0_CONTEXT7_FLAT_BASE_ADDR", + .address = 0x133, +}, +{ + .name = "MC_PT0_CONTEXT0_FLAT_START_ADDR", + .address = 0x13c, +}, +{ + .name = "MC_PT0_CONTEXT1_FLAT_START_ADDR", + .address = 0x13d, +}, +{ + .name = "MC_PT0_CONTEXT2_FLAT_START_ADDR", + .address = 0x13e, +}, +{ + .name = "MC_PT0_CONTEXT3_FLAT_START_ADDR", + .address = 0x13f, +}, +{ + .name = "MC_ARB_DRAM_PENALTIES2", + .address = 0x14, +}, +{ + .name = "MC_PT0_CONTEXT4_FLAT_START_ADDR", + .address = 0x140, +}, +{ + .name = "MC_PT0_CONTEXT5_FLAT_START_ADDR", + .address = 0x141, +}, +{ + .name = "MC_PT0_CONTEXT6_FLAT_START_ADDR", + .address = 0x142, +}, +{ + .name = "MC_PT0_CONTEXT7_FLAT_START_ADDR", + .address = 0x143, +}, +{ + .name = "MC_PT0_CONTEXT0_FLAT_END_ADDR", + .address = 0x14c, +}, +{ + .name = "MC_PT0_CONTEXT1_FLAT_END_ADDR", + .address = 0x14d, +}, +{ + .name = "MC_PT0_CONTEXT2_FLAT_END_ADDR", + .address = 0x14e, +}, +{ + .name = "MC_PT0_CONTEXT3_FLAT_END_ADDR", + .address = 0x14f, +}, +{ + .name = "MC_ARB_DRAM_PENALTIES3", + .address = 0x15, +}, +{ + .name = "MC_PT0_CONTEXT4_FLAT_END_ADDR", + .address = 0x150, +}, +{ + .name = "MC_PT0_CONTEXT5_FLAT_END_ADDR", + .address = 0x151, +}, +{ + .name = "MC_PT0_CONTEXT6_FLAT_END_ADDR", + .address = 0x152, +}, +{ + .name = "MC_PT0_CONTEXT7_FLAT_END_ADDR", + .address = 0x153, +}, +{ + .name = "MC_PT0_CONTEXT0_MULTI_LEVEL_BASE_ADDR", + .address = 0x15c, +}, +{ + .name = "MC_PT0_CONTEXT1_MULTI_LEVEL_BASE_ADDR", + .address = 0x15d, +}, +{ + .name = "MC_PT0_CONTEXT2_MULTI_LEVEL_BASE_ADDR", + .address = 0x15e, +}, +{ + .name = "MC_PT0_CONTEXT3_MULTI_LEVEL_BASE_ADDR", + .address = 0x15f, +}, +{ + .name = "MC_ARB_RATIO_CLK_SEQ", + .address = 0x16, +}, +{ + .name = "MC_PT0_CONTEXT4_MULTI_LEVEL_BASE_ADDR", + .address = 0x160, +}, +{ + .name = "MC_PT0_CONTEXT5_MULTI_LEVEL_BASE_ADDR", + .address = 0x161, +}, +{ + .name = "MC_PT0_CONTEXT6_MULTI_LEVEL_BASE_ADDR", + .address = 0x162, +}, +{ + .name = "MC_PT0_CONTEXT7_MULTI_LEVEL_BASE_ADDR", + .address = 0x163, +}, +{ + .name = "MC_PT0_CLIENT0_CNTL", + .address = 0x16c, +}, +{ + .name = "MC_PT0_CLIENT1_CNTL", + .address = 0x16d, +}, +{ + .name = "MC_PT0_CLIENT2_CNTL", + .address = 0x16e, +}, +{ + .name = "MC_PT0_CLIENT3_CNTL", + .address = 0x16f, +}, +{ + .name = "MC_ARB_RDWR_SWITCH", + .address = 0x17, +}, +{ + .name = "MC_PT0_CLIENT4_CNTL", + .address = 0x170, +}, +{ + .name = "MC_PT0_CLIENT5_CNTL", + .address = 0x171, +}, +{ + .name = "MC_PT0_CLIENT6_CNTL", + .address = 0x172, +}, +{ + .name = "MC_PT0_CLIENT7_CNTL", + .address = 0x173, +}, +{ + .name = "MC_PT0_CLIENT8_CNTL", + .address = 0x174, +}, +{ + .name = "MC_PT0_CLIENT9_CNTL", + .address = 0x175, +}, +{ + .name = "MC_PT0_CLIENT10_CNTL", + .address = 0x176, +}, +{ + .name = "MC_PT0_CLIENT11_CNTL", + .address = 0x177, +}, +{ + .name = "MC_PT0_CLIENT12_CNTL", + .address = 0x178, +}, +{ + .name = "MC_PT0_CLIENT13_CNTL", + .address = 0x179, +}, +{ + .name = "MC_PT0_CLIENT14_CNTL", + .address = 0x17a, +}, +{ + .name = "MC_PT0_CLIENT15_CNTL", + .address = 0x17b, +}, +{ + .name = "MC_PT0_CLIENT16_CNTL", + .address = 0x17c, +}, +{ + .name = "MC_SW_CNTL", + .address = 0x18, +}, +{ + .name = "MC_TIMING_CNTL_2", + .address = 0x3, +}, +{ + .name = "MC_WRITE_AGE1", + .address = 0x37, +}, +{ + .name = "MC_WRITE_AGE2", + .address = 0x38, +}, +{ + .name = "MC_FB_LOCATION", + .address = 0x4, +}, +{ + .name = "MC_AGP_LOCATION", + .address = 0x5, +}, +{ + .name = "AGP_BASE", + .address = 0x6, +}, +{ + .name = "MC_SEQ_DRAM", + .address = 0x60, +}, +{ + .name = "MC_SEQ_RAS_TIMING", + .address = 0x61, +}, +{ + .name = "MC_SEQ_CAS_TIMING", + .address = 0x62, +}, +{ + .name = "MC_SEQ_MISC_TIMING", + .address = 0x63, +}, +{ + .name = "MC_SEQ_RD_CTL_I0", + .address = 0x64, +}, +{ + .name = "MC_SEQ_RD_CTL_I1", + .address = 0x65, +}, +{ + .name = "MC_SEQ_WR_CTL_I0", + .address = 0x66, +}, +{ + .name = "MC_SEQ_WR_CTL_I1", + .address = 0x67, +}, +{ + .name = "MC_SEQ_IO_CTL_I0", + .address = 0x68, +}, +{ + .name = "MC_SEQ_IO_CTL_I1", + .address = 0x69, +}, +{ + .name = "MC_SEQ_NPL_CTL_I0", + .address = 0x6a, +}, +{ + .name = "MC_SEQ_NPL_CTL_I1", + .address = 0x6b, +}, +{ + .name = "MC_SEQ_CK_PAD_CNTL_I0", + .address = 0x6c, +}, +{ + .name = "MC_SEQ_CK_PAD_CNTL_I1", + .address = 0x6d, +}, +{ + .name = "MC_SEQ_CMD_PAD_CNTL_I0", + .address = 0x6e, +}, +{ + .name = "MC_SEQ_CMD_PAD_CNTL_I1", + .address = 0x6f, +}, +{ + .name = "AGP_BASE_2", + .address = 0x7, +}, +{ + .name = "MC_SEQ_DQ_PAD_CNTL_I0", + .address = 0x70, +}, +{ + .name = "MC_SEQ_DQ_PAD_CNTL_I1", + .address = 0x71, +}, +{ + .name = "MC_SEQ_QS_PAD_CNTL_I0", + .address = 0x72, +}, +{ + .name = "MC_SEQ_QS_PAD_CNTL_I1", + .address = 0x73, +}, +{ + .name = "MC_SEQ_A_PAD_CNTL_I0", + .address = 0x74, +}, +{ + .name = "MC_SEQ_A_PAD_CNTL_I1", + .address = 0x75, +}, +{ + .name = "MC_SEQ_CMD", + .address = 0x76, +}, +{ + .name = "MC_SEQ_STATUS", + .address = 0x77, +}, +{ + .name = "MC_CNTL0", + .address = 0x8, +}, +{ + .name = "MC_IO_PAD_CNTL_I0", + .address = 0x80, +}, +{ + .name = "MC_IO_PAD_CNTL_I1", + .address = 0x81, +}, +{ + .name = "MC_IO_PAD_CNTL", + .address = 0x82, +}, +{ + .name = "MC_IO_RD_DQ_CNTL_I0", + .address = 0x84, +}, +{ + .name = "MC_IO_RD_DQ_CNTL_I1", + .address = 0x85, +}, +{ + .name = "MC_IO_RD_QS_CNTL_I0", + .address = 0x86, +}, +{ + .name = "MC_IO_RD_QS_CNTL_I1", + .address = 0x87, +}, +{ + .name = "MC_IO_WR_CNTL_I0", + .address = 0x88, +}, +{ + .name = "MC_IO_WR_CNTL_I1", + .address = 0x89, +}, +{ + .name = "MC_IO_CK_PAD_CNTL_I0", + .address = 0x8a, +}, +{ + .name = "MC_IO_CK_PAD_CNTL_I1", + .address = 0x8b, +}, +{ + .name = "MC_IO_CMD_PAD_CNTL_I0", + .address = 0x8c, +}, +{ + .name = "MC_IO_CMD_PAD_CNTL_I1", + .address = 0x8d, +}, +{ + .name = "MC_IO_DQ_PAD_CNTL_I0", + .address = 0x8e, +}, +{ + .name = "MC_IO_DQ_PAD_CNTL_I1", + .address = 0x8f, +}, +{ + .name = "MC_CNTL1", + .address = 0x9, +}, +{ + .name = "MC_IO_QS_PAD_CNTL_I0", + .address = 0x90, +}, +{ + .name = "MC_IO_QS_PAD_CNTL_I1", + .address = 0x91, +}, +{ + .name = "MC_IO_A_PAD_CNTL_I0", + .address = 0x92, +}, +{ + .name = "MC_IO_A_PAD_CNTL_I1", + .address = 0x93, +}, +{ + .name = "MC_IO_WR_DQ_CNTL_I0", + .address = 0x94, +}, +{ + .name = "MC_IO_WR_DQ_CNTL_I1", + .address = 0x95, +}, +{ + .name = "MC_IO_WR_QS_CNTL_I0", + .address = 0x96, +}, +{ + .name = "MC_IO_WR_QS_CNTL_I1", + .address = 0x97, +}, +{ + .name = "MC_VENDOR_ID_I0", + .address = 0x98, +}, +{ + .name = "MC_VENDOR_ID_I1", + .address = 0x99, +}, +{ + .name = "MC_NPL_STATUS_I0", + .address = 0x9a, +}, +{ + .name = "MC_NPL_STATUS_I1", + .address = 0x9b, +}, +{ + .name = "MC_IO_RD_QS2_CNTL_I0", + .address = 0x9c, +}, +{ + .name = "MC_IO_RD_QS2_CNTL_I1", + .address = 0x9d, +}, +{ + .name = "MC_RFSH_CNTL", + .address = 0xa, +}, +{ + .name = "MC_IMP_CNTL", + .address = 0xa0, +}, +{ + .name = "MC_IMP_DEBUG", + .address = 0xa1, +}, +{ + .name = "MC_IMP_STATUS", + .address = 0xa2, +}, +{ + .name = "MC_RBS_MAP", + .address = 0xb0, +}, +{ + .name = "MC_RBS_CZT_HWM", + .address = 0xb1, +}, +{ + .name = "MC_RBS_SUN_HWM", + .address = 0xb2, +}, +{ + .name = "MC_RBS_MISC", + .address = 0xb3, +}, +{ + .name = "MC_PMG_CMD", + .address = 0xe0, +}, +{ + .name = "MC_PMG_CFG", + .address = 0xe1, +}, +{ + .name = "MC_MISC_0", + .address = 0xf0, +}, +{ + .name = "MC_MISC_1", + .address = 0xf1, +}, +{ + .name = "MC_DEBUG", + .address = 0xfe, +}, diff --git a/regs/memory_controller_registers.txt b/regs/memory_controller_registers.txt new file mode 100644 index 0000000..75050db --- /dev/null +++ b/regs/memory_controller_registers.txt @@ -0,0 +1,471 @@ +MC_IND_INDEX +MCDEC:0x70 +2-2 +MC_IND_DATA +MCDEC:0x74 +2-2 +MC_STATUS +MCIND:0x0 +2-2 +MC_ARB_MIN +MCIND:0x10 +2-8 +MC_PT0_CNTL +MCIND:0x100 +2-32 +MC_PT0_CONTEXT0_CNTL +MCIND:0x102 +2-33 +MC_PT0_CONTEXT1_CNTL +MCIND:0x103 +2-33 +MC_PT0_CONTEXT2_CNTL +MCIND:0x104 +2-33 +MC_PT0_CONTEXT3_CNTL +MCIND:0x105 +2-34 +MC_PT0_CONTEXT4_CNTL +MCIND:0x106 +2-34 +MC_PT0_CONTEXT5_CNTL +MCIND:0x107 +2-34 +MC_PT0_CONTEXT6_CNTL +MCIND:0x108 +2-34 +MC_PT0_CONTEXT7_CNTL +MCIND:0x109 +2-35 +MC_PT0_SYSTEM_APERTURE_LOW_ADDR +MCIND:0x112 +2-35 +MC_PT0_SYSTEM_APERTURE_HIGH_ADDR +MCIND:0x114 +2-35 +MC_PT0_SURFACE_PROBE +MCIND:0x116 +2-35 +MC_PT0_SURFACE_PROBE_FAULT_STATUS +MCIND:0x118 +2-36 +MC_PT0_PROTECTION_FAULT_STATUS +MCIND:0x11A +2-36 +MC_PT0_CONTEXT0_DEFAULT_READ_ADDR +MCIND:0x11C +2-36 +MC_PT0_CONTEXT1_DEFAULT_READ_ADDR +MCIND:0x11D +2-36 +MC_PT0_CONTEXT2_DEFAULT_READ_ADDR +MCIND:0x11E +2-37 +MC_PT0_CONTEXT3_DEFAULT_READ_ADDR +MCIND:0x11F +2-37 +MC_ARB_TIMERS +MCIND:0x12 +2-8 +MC_PT0_CONTEXT4_DEFAULT_READ_ADDR +MCIND:0x120 +2-37 +MC_PT0_CONTEXT5_DEFAULT_READ_ADDR +MCIND:0x121 +2-37 +MC_PT0_CONTEXT6_DEFAULT_READ_ADDR +MCIND:0x122 +2-37 +MC_PT0_CONTEXT7_DEFAULT_READ_ADDR +MCIND:0x123 +2-37 +MC_PT0_CONTEXT0_FLAT_BASE_ADDR +MCIND:0x12C +2-37 +MC_PT0_CONTEXT1_FLAT_BASE_ADDR +MCIND:0x12D +2-38 +MC_PT0_CONTEXT2_FLAT_BASE_ADDR +MCIND:0x12E +2-38 +MC_PT0_CONTEXT3_FLAT_BASE_ADDR +MCIND:0x12F +2-38 +MC_ARB_DRAM_PENALTIES +MCIND:0x13 +2-8 +MC_PT0_CONTEXT4_FLAT_BASE_ADDR +MCIND:0x130 +2-38 +MC_PT0_CONTEXT5_FLAT_BASE_ADDR +MCIND:0x131 +2-38 +MC_PT0_CONTEXT6_FLAT_BASE_ADDR +MCIND:0x132 +2-38 +MC_PT0_CONTEXT7_FLAT_BASE_ADDR +MCIND:0x133 +2-39 +MC_PT0_CONTEXT0_FLAT_START_ADDR +MCIND:0x13C +2-39 +MC_PT0_CONTEXT1_FLAT_START_ADDR +MCIND:0x13D +2-39 +MC_PT0_CONTEXT2_FLAT_START_ADDR +MCIND:0x13E +2-39 +MC_PT0_CONTEXT3_FLAT_START_ADDR +MCIND:0x13F +2-39 +MC_ARB_DRAM_PENALTIES2 +MCIND:0x14 +2-8 +MC_PT0_CONTEXT4_FLAT_START_ADDR +MCIND:0x140 +2-39 +MC_PT0_CONTEXT5_FLAT_START_ADDR +MCIND:0x141 +2-40 +MC_PT0_CONTEXT6_FLAT_START_ADDR +MCIND:0x142 +2-40 +MC_PT0_CONTEXT7_FLAT_START_ADDR +MCIND:0x143 +2-40 +MC_PT0_CONTEXT0_FLAT_END_ADDR +MCIND:0x14C +2-40 +MC_PT0_CONTEXT1_FLAT_END_ADDR +MCIND:0x14D +2-40 +MC_PT0_CONTEXT2_FLAT_END_ADDR +MCIND:0x14E +2-40 +MC_PT0_CONTEXT3_FLAT_END_ADDR +MCIND:0x14F +2-41 +MC_ARB_DRAM_PENALTIES3 +MCIND:0x15 +2-9 +MC_PT0_CONTEXT4_FLAT_END_ADDR +MCIND:0x150 +2-41 +MC_PT0_CONTEXT5_FLAT_END_ADDR +MCIND:0x151 +2-41 +MC_PT0_CONTEXT6_FLAT_END_ADDR +MCIND:0x152 +2-41 +MC_PT0_CONTEXT7_FLAT_END_ADDR +MCIND:0x153 +2-41 +MC_PT0_CONTEXT0_MULTI_LEVEL_BASE_ADDR +MCIND:0x15C +2-41 +MC_PT0_CONTEXT1_MULTI_LEVEL_BASE_ADDR +MCIND:0x15D +2-42 +MC_PT0_CONTEXT2_MULTI_LEVEL_BASE_ADDR +MCIND:0x15E +2-42 +MC_PT0_CONTEXT3_MULTI_LEVEL_BASE_ADDR +MCIND:0x15F +2-42 +MC_ARB_RATIO_CLK_SEQ +MCIND:0x16 +2-9 +MC_PT0_CONTEXT4_MULTI_LEVEL_BASE_ADDR +MCIND:0x160 +2-42 +MC_PT0_CONTEXT5_MULTI_LEVEL_BASE_ADDR +MCIND:0x161 +2-42 +MC_PT0_CONTEXT6_MULTI_LEVEL_BASE_ADDR +MCIND:0x162 +2-42 +MC_PT0_CONTEXT7_MULTI_LEVEL_BASE_ADDR +MCIND:0x163 +2-42 +MC_PT0_CLIENT0_CNTL +MCIND:0x16C +2-43 +MC_PT0_CLIENT1_CNTL +MCIND:0x16D +2-43 +MC_PT0_CLIENT2_CNTL +MCIND:0x16E +2-44 +MC_PT0_CLIENT3_CNTL +MCIND:0x16F +2-45 +MC_ARB_RDWR_SWITCH +MCIND:0x17 +2-9 +MC_PT0_CLIENT4_CNTL +MCIND:0x170 +2-46 +MC_PT0_CLIENT5_CNTL +MCIND:0x171 +2-47 +MC_PT0_CLIENT6_CNTL +MCIND:0x172 +2-48 +MC_PT0_CLIENT7_CNTL +MCIND:0x173 +2-49 +MC_PT0_CLIENT8_CNTL +MCIND:0x174 +2-49 +MC_PT0_CLIENT9_CNTL +MCIND:0x175 +2-50 +MC_PT0_CLIENT10_CNTL +MCIND:0x176 +2-51 +MC_PT0_CLIENT11_CNTL +MCIND:0x177 +2-52 +MC_PT0_CLIENT12_CNTL +MCIND:0x178 +2-53 +MC_PT0_CLIENT13_CNTL +MCIND:0x179 +2-54 +MC_PT0_CLIENT14_CNTL +MCIND:0x17A +2-55 +MC_PT0_CLIENT15_CNTL +MCIND:0x17B +2-55 +MC_PT0_CLIENT16_CNTL +MCIND:0x17C +2-56 +MC_SW_CNTL +MCIND:0x18 +2-9 +MC_TIMING_CNTL_2 +MCIND:0x3 +2-3 +MC_WRITE_AGE1 +MCIND:0x37 +2-9 +MC_WRITE_AGE2 +MCIND:0x38 +2-10 +MC_FB_LOCATION +MCIND:0x4 +2-3 +MC_AGP_LOCATION +MCIND:0x5 +2-3 +AGP_BASE +MCIND:0x6 +2-3 +MC_SEQ_DRAM +MCIND:0x60 +2-10 +MC_SEQ_RAS_TIMING +MCIND:0x61 +2-11 +MC_SEQ_CAS_TIMING +MCIND:0x62 +2-11 +MC_SEQ_MISC_TIMING +MCIND:0x63 +2-12 +MC_SEQ_RD_CTL_I0 +MCIND:0x64 +2-12 +MC_SEQ_RD_CTL_I1 +MCIND:0x65 +2-13 +MC_SEQ_WR_CTL_I0 +MCIND:0x66 +2-14 +MC_SEQ_WR_CTL_I1 +MCIND:0x67 +2-15 +MC_SEQ_IO_CTL_I0 +MCIND:0x68 +2-15 +MC_SEQ_IO_CTL_I1 +MCIND:0x69 +2-15 +MC_SEQ_NPL_CTL_I0 +MCIND:0x6A +2-16 +MC_SEQ_NPL_CTL_I1 +MCIND:0x6B +2-16 +MC_SEQ_CK_PAD_CNTL_I0 +MCIND:0x6C +2-16 +MC_SEQ_CK_PAD_CNTL_I1 +MCIND:0x6D +2-16 +MC_SEQ_CMD_PAD_CNTL_I0 +MCIND:0x6E +2-17 +MC_SEQ_CMD_PAD_CNTL_I1 +MCIND:0x6F +2-17 +AGP_BASE_2 +MCIND:0x7 +2-3 +MC_SEQ_DQ_PAD_CNTL_I0 +MCIND:0x70 +2-17 +MC_SEQ_DQ_PAD_CNTL_I1 +MCIND:0x71 +2-17 +MC_SEQ_QS_PAD_CNTL_I0 +MCIND:0x72 +2-18 +MC_SEQ_QS_PAD_CNTL_I1 +MCIND:0x73 +2-18 +MC_SEQ_A_PAD_CNTL_I0 +MCIND:0x74 +2-18 +MC_SEQ_A_PAD_CNTL_I1 +MCIND:0x75 +2-18 +MC_SEQ_CMD +MCIND:0x76 +2-19 +MC_SEQ_STATUS +MCIND:0x77 +2-19 +MC_CNTL0 +MCIND:0x8 +2-4 +MC_IO_PAD_CNTL_I0 +MCIND:0x80 +2-19 +MC_IO_PAD_CNTL_I1 +MCIND:0x81 +2-20 +MC_IO_PAD_CNTL +MCIND:0x82 +2-21 +MC_IO_RD_DQ_CNTL_I0 +MCIND:0x84 +2-22 +MC_IO_RD_DQ_CNTL_I1 +MCIND:0x85 +2-22 +MC_IO_RD_QS_CNTL_I0 +MCIND:0x86 +2-22 +MC_IO_RD_QS_CNTL_I1 +MCIND:0x87 +2-22 +MC_IO_WR_CNTL_I0 +MCIND:0x88 +2-22 +MC_IO_WR_CNTL_I1 +MCIND:0x89 +2-23 +MC_IO_CK_PAD_CNTL_I0 +MCIND:0x8A +2-23 +MC_IO_CK_PAD_CNTL_I1 +MCIND:0x8B +2-23 +MC_IO_CMD_PAD_CNTL_I0 +MCIND:0x8C +2-23 +MC_IO_CMD_PAD_CNTL_I1 +MCIND:0x8D +2-24 +MC_IO_DQ_PAD_CNTL_I0 +MCIND:0x8E +2-24 +MC_IO_DQ_PAD_CNTL_I1 +MCIND:0x8F +2-24 +MC_CNTL1 +MCIND:0x9 +2-6 +MC_IO_QS_PAD_CNTL_I0 +MCIND:0x90 +2-25 +MC_IO_QS_PAD_CNTL_I1 +MCIND:0x91 +2-25 +MC_IO_A_PAD_CNTL_I0 +MCIND:0x92 +2-25 +MC_IO_A_PAD_CNTL_I1 +MCIND:0x93 +2-26 +MC_IO_WR_DQ_CNTL_I0 +MCIND:0x94 +2-26 +MC_IO_WR_DQ_CNTL_I1 +MCIND:0x95 +2-26 +MC_IO_WR_QS_CNTL_I0 +MCIND:0x96 +2-26 +MC_IO_WR_QS_CNTL_I1 +MCIND:0x97 +2-27 +MC_VENDOR_ID_I0 +MCIND:0x98 +2-27 +MC_VENDOR_ID_I1 +MCIND:0x99 +2-27 +MC_NPL_STATUS_I0 +MCIND:0x9A +2-27 +MC_NPL_STATUS_I1 +MCIND:0x9B +2-27 +MC_IO_RD_QS2_CNTL_I0 +MCIND:0x9C +2-28 +MC_IO_RD_QS2_CNTL_I1 +MCIND:0x9D +2-28 +MC_RFSH_CNTL +MCIND:0xA +2-8 +MC_IMP_CNTL +MCIND:0xA0 +2-28 +MC_IMP_DEBUG +MCIND:0xA1 +2-28 +MC_IMP_STATUS +MCIND:0xA2 +2-28 +MC_RBS_MAP +MCIND:0xB0 +2-29 +MC_RBS_CZT_HWM +MCIND:0xB1 +2-30 +MC_RBS_SUN_HWM +MCIND:0xB2 +2-30 +MC_RBS_MISC +MCIND:0xB3 +2-30 +MC_PMG_CMD +MCIND:0xE0 +2-31 +MC_PMG_CFG +MCIND:0xE1 +2-31 +MC_MISC_0 +MCIND:0xF0 +2-31 +MC_MISC_1 +MCIND:0xF1 +2-31 +MC_DEBUG +MCIND:0xFE +2-32 diff --git a/regs/pcie_registers.inc b/regs/pcie_registers.inc new file mode 100644 index 0000000..baa71f5 --- /dev/null +++ b/regs/pcie_registers.inc @@ -0,0 +1,648 @@ +{ + .name = "PCIE_TX_CNTL", + .address = 0x1, +}, +{ + .name = "PCIE_TX_GART_CNTL", + .address = 0x10, +}, +{ + .name = "PCIE_TX_GART_DISCARD_RD_ADDR_LO", + .address = 0x11, +}, +{ + .name = "PCIE_TX_GART_DISCARD_RD_ADDR_HI", + .address = 0x12, +}, +{ + .name = "PCIE_TX_GART_BASE", + .address = 0x13, +}, +{ + .name = "PCIE_TX_GART_START_LO", + .address = 0x14, +}, +{ + .name = "PCIE_TX_GART_START_HI", + .address = 0x15, +}, +{ + .name = "PCIE_TX_GART_END_LO", + .address = 0x16, +}, +{ + .name = "PCIE_TX_GART_END_HI", + .address = 0x17, +}, +{ + .name = "PCIE_TX_GART_ERROR", + .address = 0x18, +}, +{ + .name = "PCIE_TX_SEQ", + .address = 0x2, +}, +{ + .name = "PCIE_TX_GART_LRU_MRU_PTR", + .address = 0x20, +}, +{ + .name = "PCIE_TX_GART_STATUS", + .address = 0x21, +}, +{ + .name = "PCIE_TX_GART_TLB_VALID", + .address = 0x22, +}, +{ + .name = "PCIE_TX_GART_TLB0_DATA", + .address = 0x23, +}, +{ + .name = "PCIE_TX_GART_TLB1_DATA", + .address = 0x24, +}, +{ + .name = "PCIE_TX_GART_TLB2_DATA", + .address = 0x25, +}, +{ + .name = "PCIE_TX_GART_TLB3_DATA", + .address = 0x26, +}, +{ + .name = "PCIE_TX_GART_TLB4_DATA", + .address = 0x27, +}, +{ + .name = "PCIE_TX_GART_TLB5_DATA", + .address = 0x28, +}, +{ + .name = "PCIE_TX_GART_TLB6_DATA", + .address = 0x29, +}, +{ + .name = "PCIE_TX_GART_TLB7_DATA", + .address = 0x2a, +}, +{ + .name = "PCIE_TX_GART_TLB8_DATA", + .address = 0x2b, +}, +{ + .name = "PCIE_TX_GART_TLB9_DATA", + .address = 0x2c, +}, +{ + .name = "PCIE_TX_GART_TLB10_DATA", + .address = 0x2d, +}, +{ + .name = "PCIE_TX_GART_TLB11_DATA", + .address = 0x2e, +}, +{ + .name = "PCIE_TX_GART_TLB12_DATA", + .address = 0x2f, +}, +{ + .name = "PCIE_TX_REPLAY", + .address = 0x3, +}, +{ + .name = "PCIE_TX_GART_TLB13_DATA", + .address = 0x30, +}, +{ + .name = "PCIE_TX_GART_TLB14_DATA", + .address = 0x31, +}, +{ + .name = "PCIE_TX_GART_TLB15_DATA", + .address = 0x32, +}, +{ + .name = "PCIE_TX_GART_TLB16_DATA", + .address = 0x33, +}, +{ + .name = "PCIE_TX_GART_TLB17_DATA", + .address = 0x34, +}, +{ + .name = "PCIE_TX_GART_TLB18_DATA", + .address = 0x35, +}, +{ + .name = "PCIE_TX_GART_TLB19_DATA", + .address = 0x36, +}, +{ + .name = "PCIE_TX_GART_TLB20_DATA", + .address = 0x37, +}, +{ + .name = "PCIE_TX_GART_TLB21_DATA", + .address = 0x38, +}, +{ + .name = "PCIE_TX_GART_TLB22_DATA", + .address = 0x39, +}, +{ + .name = "PCIE_TX_GART_TLB23_DATA", + .address = 0x3a, +}, +{ + .name = "PCIE_TX_GART_TLB24_DATA", + .address = 0x3b, +}, +{ + .name = "PCIE_TX_GART_TLB25_DATA", + .address = 0x3c, +}, +{ + .name = "PCIE_TX_GART_TLB26_DATA", + .address = 0x3d, +}, +{ + .name = "PCIE_TX_GART_TLB27_DATA", + .address = 0x3e, +}, +{ + .name = "PCIE_TX_GART_TLB28_DATA", + .address = 0x3f, +}, +{ + .name = "PCIE_TX_CREDITS_CONSUMED", + .address = 0x4, +}, +{ + .name = "PCIE_TX_GART_TLB29_DATA", + .address = 0x40, +}, +{ + .name = "PCIE_CLK_CNTL", + .address = 0x400, +}, +{ + .name = "PCIE_PRBS10", + .address = 0x401, +}, +{ + .name = "PCIE_PRBS23_BITCNT0", + .address = 0x402, +}, +{ + .name = "PCIE_PRBS23_BITCNT1", + .address = 0x403, +}, +{ + .name = "PCIE_PRBS23_BITCNT2", + .address = 0x404, +}, +{ + .name = "PCIE_PRBS23_BITCNT3", + .address = 0x405, +}, +{ + .name = "PCIE_PRBS23_BITCNT4", + .address = 0x406, +}, +{ + .name = "PCIE_PRBS23_BITCNT5", + .address = 0x407, +}, +{ + .name = "PCIE_PRBS23_BITCNT6", + .address = 0x408, +}, +{ + .name = "PCIE_PRBS23_BITCNT7", + .address = 0x409, +}, +{ + .name = "PCIE_PRBS23_BITCNT8", + .address = 0x40a, +}, +{ + .name = "PCIE_PRBS23_BITCNT9", + .address = 0x40b, +}, +{ + .name = "PCIE_PRBS23_BITCNT10", + .address = 0x40c, +}, +{ + .name = "PCIE_PRBS23_BITCNT11", + .address = 0x40d, +}, +{ + .name = "PCIE_PRBS23_BITCNT12", + .address = 0x40e, +}, +{ + .name = "PCIE_PRBS23_BITCNT13", + .address = 0x40f, +}, +{ + .name = "PCIE_TX_GART_TLB30_DATA", + .address = 0x41, +}, +{ + .name = "PCIE_PRBS23_BITCNT14", + .address = 0x410, +}, +{ + .name = "PCIE_PRBS23_BITCNT15", + .address = 0x411, +}, +{ + .name = "PCIE_PRBS23_ERRCNT0", + .address = 0x412, +}, +{ + .name = "PCIE_PRBS23_ERRCNT1", + .address = 0x413, +}, +{ + .name = "PCIE_PRBS23_ERRCNT2", + .address = 0x414, +}, +{ + .name = "PCIE_PRBS23_ERRCNT3", + .address = 0x415, +}, +{ + .name = "PCIE_PRBS23_ERRCNT4", + .address = 0x416, +}, +{ + .name = "PCIE_PRBS23_ERRCNT5", + .address = 0x417, +}, +{ + .name = "PCIE_PRBS23_ERRCNT6", + .address = 0x418, +}, +{ + .name = "PCIE_PRBS23_ERRCNT7", + .address = 0x419, +}, +{ + .name = "PCIE_PRBS23_ERRCNT8", + .address = 0x41a, +}, +{ + .name = "PCIE_PRBS23_ERRCNT9", + .address = 0x41b, +}, +{ + .name = "PCIE_PRBS23_ERRCNT10", + .address = 0x41c, +}, +{ + .name = "PCIE_PRBS23_ERRCNT11", + .address = 0x41d, +}, +{ + .name = "PCIE_PRBS23_ERRCNT12", + .address = 0x41e, +}, +{ + .name = "PCIE_PRBS23_ERRCNT13", + .address = 0x41f, +}, +{ + .name = "PCIE_TX_GART_TLB31_DATA", + .address = 0x42, +}, +{ + .name = "PCIE_PRBS23_ERRCNT14", + .address = 0x420, +}, +{ + .name = "PCIE_PRBS23_ERRCNT15", + .address = 0x421, +}, +{ + .name = "PCIE_PRBS23_CTRL0", + .address = 0x422, +}, +{ + .name = "PCIE_PRBS23_CTRL1", + .address = 0x423, +}, +{ + .name = "PCIE_PRBS_EN", + .address = 0x424, +}, +{ + .name = "PCIE_XSTRAP1", + .address = 0x425, +}, +{ + .name = "PCIE_XSTRAP2", + .address = 0x426, +}, +{ + .name = "PCIE_XSTRAP5", + .address = 0x429, +}, +{ + .name = "PCIE_TX_CREDITS_CONSUMED_D", + .address = 0x5, +}, +{ + .name = "PCIE_TX_CREDITS_CONSUMED_CPLD", + .address = 0x6, +}, +{ + .name = "PCIE_FLOW_CNTL", + .address = 0x60, +}, +{ + .name = "PCIE_TXRX_DEBUG_SEQNUM", + .address = 0x61, +}, +{ + .name = "PCIE_TXRX_TEST_MODE", + .address = 0x62, +}, +{ + .name = "PCIE_TX_CREDITS_LIMIT", + .address = 0x7, +}, +{ + .name = "PCIE_RX_CNTL", + .address = 0x70, +}, +{ + .name = "PCIE_RX_NUM_NACK", + .address = 0x71, +}, +{ + .name = "PCIE_RX_NUM_NACK_GENERATED", + .address = 0x72, +}, +{ + .name = "PCIE_RX_ACK_NACK_LATENCY", + .address = 0x73, +}, +{ + .name = "PCIE_RX_ACK_NACK_LATENCY_THRESHOLD", + .address = 0x74, +}, +{ + .name = "PCIE_RX_TLP_HDR0", + .address = 0x75, +}, +{ + .name = "PCIE_RX_TLP_HDR1", + .address = 0x76, +}, +{ + .name = "PCIE_RX_TLP_HDR2", + .address = 0x77, +}, +{ + .name = "PCIE_RX_TLP_HDR3", + .address = 0x78, +}, +{ + .name = "PCIE_RX_TLP_HDR4", + .address = 0x79, +}, +{ + .name = "PCIE_RX_TLP_CRC", + .address = 0x7a, +}, +{ + .name = "PCIE_RX_DLP0", + .address = 0x7b, +}, +{ + .name = "PCIE_RX_DLP1", + .address = 0x7c, +}, +{ + .name = "PCIE_RX_DLP_CRC", + .address = 0x7d, +}, +{ + .name = "PCIE_RX_CREDITS_ALLOCATED", + .address = 0x7e, +}, +{ + .name = "PCIE_RX_CREDITS_ALLOCATED_D", + .address = 0x7f, +}, +{ + .name = "PCIE_TX_CREDITS_LIMIT_D", + .address = 0x8, +}, +{ + .name = "PCIE_RX_CREDITS_ALLOCATED_CPLD", + .address = 0x80, +}, +{ + .name = "PCIE_RX_CREDITS_RECEIVED", + .address = 0x81, +}, +{ + .name = "PCIE_RX_CREDITS_RECEIVED_D", + .address = 0x82, +}, +{ + .name = "PCIE_RX_CREDITS_RECEIVED_CPLD", + .address = 0x83, +}, +{ + .name = "PCIE_RX_MAL_TLP_COUNT", + .address = 0x84, +}, +{ + .name = "PCIE_RX_ERR_LOG", + .address = 0x85, +}, +{ + .name = "PCIE_RX_EXPECTED_SEQNUM", + .address = 0x86, +}, +{ + .name = "PCIE_TX_CREDITS_LIMIT_CPLD", + .address = 0x9, +}, +{ + .name = "PCIE_CI_CNTL", + .address = 0x90, +}, +{ + .name = "PCIE_CI_FLUSH_CNTL", + .address = 0x91, +}, +{ + .name = "PCIE_CI_PANIC", + .address = 0x92, +}, +{ + .name = "PCIE_CI_HANG", + .address = 0x93, +}, +{ + .name = "PCIE_LC_CNTL", + .address = 0xa0, +}, +{ + .name = "PCIE_LC_N_FTS_CNTL", + .address = 0xa1, +}, +{ + .name = "PCIE_LC_LINK_WIDTH_CNTL", + .address = 0xa2, +}, +{ + .name = "PCIE_LC_STATE0", + .address = 0xa5, +}, +{ + .name = "PCIE_LC_STATE1", + .address = 0xa6, +}, +{ + .name = "PCIE_LC_STATE2", + .address = 0xa7, +}, +{ + .name = "PCIE_LC_STATE3", + .address = 0xa8, +}, +{ + .name = "PCIE_LC_STATE4", + .address = 0xa9, +}, +{ + .name = "PCIE_LC_STATE5", + .address = 0xaa, +}, +{ + .name = "PCIE_LC_FORCE_SYNC_LOSS_CNTL", + .address = 0xab, +}, +{ + .name = "PCIE_P_CNTL", + .address = 0xb0, +}, +{ + .name = "PCIE_P_CNTL2", + .address = 0xb1, +}, +{ + .name = "PCIE_P_BUF_STATUS", + .address = 0xb2, +}, +{ + .name = "PCIE_P_DECODER_STATUS", + .address = 0xb3, +}, +{ + .name = "PCIE_P_MISC_DEBUG_STATUS", + .address = 0xb4, +}, +{ + .name = "PCIE_P_IMP_CNTL_STRENGTH", + .address = 0xc0, +}, +{ + .name = "PCIE_P_IMP_CNTL_UPDATE", + .address = 0xc1, +}, +{ + .name = "PCIE_P_STR_CNTL_UPDATE", + .address = 0xc2, +}, +{ + .name = "PCIE_P_PAD_MISC_CNTL", + .address = 0xc3, +}, +{ + .name = "PCIE_P_SYMSYNC_CTL", + .address = 0xc4, +}, +{ + .name = "PCIE_P_DECODE_ERR_CNTL", + .address = 0xc5, +}, +{ + .name = "PCIE_ERR_CNTL", + .address = 0xe0, +}, +{ + .name = "PCIE_CLK_RST_CNTL", + .address = 0xe1, +}, +{ + .name = "PCIE_P_DECODE_ERR_CNT_0", + .address = 0xf0, +}, +{ + .name = "PCIE_P_DECODE_ERR_CNT_1", + .address = 0xf1, +}, +{ + .name = "PCIE_P_DECODE_ERR_CNT_2", + .address = 0xf2, +}, +{ + .name = "PCIE_P_DECODE_ERR_CNT_3", + .address = 0xf3, +}, +{ + .name = "PCIE_P_DECODE_ERR_CNT_4", + .address = 0xf4, +}, +{ + .name = "PCIE_P_DECODE_ERR_CNT_5", + .address = 0xf5, +}, +{ + .name = "PCIE_P_DECODE_ERR_CNT_6", + .address = 0xf6, +}, +{ + .name = "PCIE_P_DECODE_ERR_CNT_7", + .address = 0xf7, +}, +{ + .name = "PCIE_P_DECODE_ERR_CNT_8", + .address = 0xf8, +}, +{ + .name = "PCIE_P_DECODE_ERR_CNT_9", + .address = 0xf9, +}, +{ + .name = "PCIE_P_DECODE_ERR_CNT_10", + .address = 0xfa, +}, +{ + .name = "PCIE_P_DECODE_ERR_CNT_11", + .address = 0xfb, +}, +{ + .name = "PCIE_P_DECODE_ERR_CNT_12", + .address = 0xfc, +}, +{ + .name = "PCIE_P_DECODE_ERR_CNT_13", + .address = 0xfd, +}, +{ + .name = "PCIE_P_DECODE_ERR_CNT_14", + .address = 0xfe, +}, +{ + .name = "PCIE_P_DECODE_ERR_CNT_15", + .address = 0xff, +}, diff --git a/regs/pcie_registers.txt b/regs/pcie_registers.txt new file mode 100644 index 0000000..4d005a6 --- /dev/null +++ b/regs/pcie_registers.txt @@ -0,0 +1,486 @@ +PCIE_TX_CNTL +PCIEIND:0x1 +2-80 +PCIE_TX_GART_CNTL +PCIEIND:0x10 +2-82 +PCIE_TX_GART_DISCARD_RD_ADDR_LO +PCIEIND:0x11 +2-82 +PCIE_TX_GART_DISCARD_RD_ADDR_HI +PCIEIND:0x12 +2-82 +PCIE_TX_GART_BASE +PCIEIND:0x13 +2-83 +PCIE_TX_GART_START_LO +PCIEIND:0x14 +2-83 +PCIE_TX_GART_START_HI +PCIEIND:0x15 +2-83 +PCIE_TX_GART_END_LO +PCIEIND:0x16 +2-83 +PCIE_TX_GART_END_HI +PCIEIND:0x17 +2-83 +PCIE_TX_GART_ERROR +PCIEIND:0x18 +2-83 +PCIE_TX_SEQ +PCIEIND:0x2 +2-80 +PCIE_TX_GART_LRU_MRU_PTR +PCIEIND:0x20 +2-84 +PCIE_TX_GART_STATUS +PCIEIND:0x21 +2-84 +PCIE_TX_GART_TLB_VALID +PCIEIND:0x22 +2-84 +PCIE_TX_GART_TLB0_DATA +PCIEIND:0x23 +2-84 +PCIE_TX_GART_TLB1_DATA +PCIEIND:0x24 +2-84 +PCIE_TX_GART_TLB2_DATA +PCIEIND:0x25 +2-84 +PCIE_TX_GART_TLB3_DATA +PCIEIND:0x26 +2-85 +PCIE_TX_GART_TLB4_DATA +PCIEIND:0x27 +2-85 +PCIE_TX_GART_TLB5_DATA +PCIEIND:0x28 +2-85 +PCIE_TX_GART_TLB6_DATA +PCIEIND:0x29 +2-85 +PCIE_TX_GART_TLB7_DATA +PCIEIND:0x2A +2-85 +PCIE_TX_GART_TLB8_DATA +PCIEIND:0x2B +2-85 +PCIE_TX_GART_TLB9_DATA +PCIEIND:0x2C +2-85 +PCIE_TX_GART_TLB10_DATA +PCIEIND:0x2D +2-86 +PCIE_TX_GART_TLB11_DATA +PCIEIND:0x2E +2-86 +PCIE_TX_GART_TLB12_DATA +PCIEIND:0x2F +2-86 +PCIE_TX_REPLAY +PCIEIND:0x3 +2-80 +PCIE_TX_GART_TLB13_DATA +PCIEIND:0x30 +2-86 +PCIE_TX_GART_TLB14_DATA +PCIEIND:0x31 +2-86 +PCIE_TX_GART_TLB15_DATA +PCIEIND:0x32 +2-86 +PCIE_TX_GART_TLB16_DATA +PCIEIND:0x33 +2-87 +PCIE_TX_GART_TLB17_DATA +PCIEIND:0x34 +2-87 +PCIE_TX_GART_TLB18_DATA +PCIEIND:0x35 +2-87 +PCIE_TX_GART_TLB19_DATA +PCIEIND:0x36 +2-87 +PCIE_TX_GART_TLB20_DATA +PCIEIND:0x37 +2-87 +PCIE_TX_GART_TLB21_DATA +PCIEIND:0x38 +2-87 +PCIE_TX_GART_TLB22_DATA +PCIEIND:0x39 +2-88 +PCIE_TX_GART_TLB23_DATA +PCIEIND:0x3A +2-88 +PCIE_TX_GART_TLB24_DATA +PCIEIND:0x3B +2-88 +PCIE_TX_GART_TLB25_DATA +PCIEIND:0x3C +2-88 +PCIE_TX_GART_TLB26_DATA +PCIEIND:0x3D +2-88 +PCIE_TX_GART_TLB27_DATA +PCIEIND:0x3E +2-88 +PCIE_TX_GART_TLB28_DATA +PCIEIND:0x3F +2-89 +PCIE_TX_CREDITS_CONSUMED +PCIEIND:0x4 +2-81 +PCIE_TX_GART_TLB29_DATA +PCIEIND:0x40 +2-89 +PCIE_CLK_CNTL +PCIEIND:0x400 +2-107 +PCIE_PRBS10 +PCIEIND:0x401 +2-107 +PCIE_PRBS23_BITCNT0 +PCIEIND:0x402 +2-107 +PCIE_PRBS23_BITCNT1 +PCIEIND:0x403 +2-107 +PCIE_PRBS23_BITCNT2 +PCIEIND:0x404 +2-107 +PCIE_PRBS23_BITCNT3 +PCIEIND:0x405 +2-108 +PCIE_PRBS23_BITCNT4 +PCIEIND:0x406 +2-108 +PCIE_PRBS23_BITCNT5 +PCIEIND:0x407 +2-108 +PCIE_PRBS23_BITCNT6 +PCIEIND:0x408 +2-108 +PCIE_PRBS23_BITCNT7 +PCIEIND:0x409 +2-108 +PCIE_PRBS23_BITCNT8 +PCIEIND:0x40A +2-108 +PCIE_PRBS23_BITCNT9 +PCIEIND:0x40B +2-108 +PCIE_PRBS23_BITCNT10 +PCIEIND:0x40C +2-109 +PCIE_PRBS23_BITCNT11 +PCIEIND:0x40D +2-109 +PCIE_PRBS23_BITCNT12 +PCIEIND:0x40E +2-109 +PCIE_PRBS23_BITCNT13 +PCIEIND:0x40F +2-109 +PCIE_TX_GART_TLB30_DATA +PCIEIND:0x41 +2-89 +PCIE_PRBS23_BITCNT14 +PCIEIND:0x410 +2-109 +PCIE_PRBS23_BITCNT15 +PCIEIND:0x411 +2-109 +PCIE_PRBS23_ERRCNT0 +PCIEIND:0x412 +2-110 +PCIE_PRBS23_ERRCNT1 +PCIEIND:0x413 +2-110 +PCIE_PRBS23_ERRCNT2 +PCIEIND:0x414 +2-110 +PCIE_PRBS23_ERRCNT3 +PCIEIND:0x415 +2-110 +PCIE_PRBS23_ERRCNT4 +PCIEIND:0x416 +2-110 +PCIE_PRBS23_ERRCNT5 +PCIEIND:0x417 +2-110 +PCIE_PRBS23_ERRCNT6 +PCIEIND:0x418 +2-110 +PCIE_PRBS23_ERRCNT7 +PCIEIND:0x419 +2-111 +PCIE_PRBS23_ERRCNT8 +PCIEIND:0x41A +2-111 +PCIE_PRBS23_ERRCNT9 +PCIEIND:0x41B +2-111 +PCIE_PRBS23_ERRCNT10 +PCIEIND:0x41C +2-111 +PCIE_PRBS23_ERRCNT11 +PCIEIND:0x41D +2-111 +PCIE_PRBS23_ERRCNT12 +PCIEIND:0x41E +2-111 +PCIE_PRBS23_ERRCNT13 +PCIEIND:0x41F +2-111 +PCIE_TX_GART_TLB31_DATA +PCIEIND:0x42 +2-89 +PCIE_PRBS23_ERRCNT14 +PCIEIND:0x420 +2-112 +PCIE_PRBS23_ERRCNT15 +PCIEIND:0x421 +2-112 +PCIE_PRBS23_CTRL0 +PCIEIND:0x422 +2-112 +PCIE_PRBS23_CTRL1 +PCIEIND:0x423 +2-113 +PCIE_PRBS_EN +PCIEIND:0x424 +2-113 +PCIE_XSTRAP1 +PCIEIND:0x425 +2-113 +PCIE_XSTRAP2 +PCIEIND:0x426 +2-114 +PCIE_XSTRAP5 +PCIEIND:0x429 +2-114 +PCIE_TX_CREDITS_CONSUMED_D +PCIEIND:0x5 +2-81 +PCIE_TX_CREDITS_CONSUMED_CPLD +PCIEIND:0x6 +2-81 +PCIE_FLOW_CNTL +PCIEIND:0x60 +2-89 +PCIE_TXRX_DEBUG_SEQNUM +PCIEIND:0x61 +2-90 +PCIE_TXRX_TEST_MODE +PCIEIND:0x62 +2-90 +PCIE_TX_CREDITS_LIMIT +PCIEIND:0x7 +2-81 +PCIE_RX_CNTL +PCIEIND:0x70 +2-90 +PCIE_RX_NUM_NACK +PCIEIND:0x71 +2-91 +PCIE_RX_NUM_NACK_GENERATED +PCIEIND:0x72 +2-91 +PCIE_RX_ACK_NACK_LATENCY +PCIEIND:0x73 +2-91 +PCIE_RX_ACK_NACK_LATENCY_THRESHOLD +PCIEIND:0x74 +2-91 +PCIE_RX_TLP_HDR0 +PCIEIND:0x75 +2-91 +PCIE_RX_TLP_HDR1 +PCIEIND:0x76 +2-91 +PCIE_RX_TLP_HDR2 +PCIEIND:0x77 +2-91 +PCIE_RX_TLP_HDR3 +PCIEIND:0x78 +2-92 +PCIE_RX_TLP_HDR4 +PCIEIND:0x79 +2-92 +PCIE_RX_TLP_CRC +PCIEIND:0x7A +2-92 +PCIE_RX_DLP0 +PCIEIND:0x7B +2-92 +PCIE_RX_DLP1 +PCIEIND:0x7C +2-92 +PCIE_RX_DLP_CRC +PCIEIND:0x7D +2-92 +PCIE_RX_CREDITS_ALLOCATED +PCIEIND:0x7E +2-92 +PCIE_RX_CREDITS_ALLOCATED_D +PCIEIND:0x7F +2-93 +PCIE_TX_CREDITS_LIMIT_D +PCIEIND:0x8 +2-81 +PCIE_RX_CREDITS_ALLOCATED_CPLD +PCIEIND:0x80 +2-93 +PCIE_RX_CREDITS_RECEIVED +PCIEIND:0x81 +2-93 +PCIE_RX_CREDITS_RECEIVED_D +PCIEIND:0x82 +2-93 +PCIE_RX_CREDITS_RECEIVED_CPLD +PCIEIND:0x83 +2-93 +PCIE_RX_MAL_TLP_COUNT +PCIEIND:0x84 +2-93 +PCIE_RX_ERR_LOG +PCIEIND:0x85 +2-94 +PCIE_RX_EXPECTED_SEQNUM +PCIEIND:0x86 +2-94 +PCIE_TX_CREDITS_LIMIT_CPLD +PCIEIND:0x9 +2-82 +PCIE_CI_CNTL +PCIEIND:0x90 +2-94 +PCIE_CI_FLUSH_CNTL +PCIEIND:0x91 +2-94 +PCIE_CI_PANIC +PCIEIND:0x92 +2-94 +PCIE_CI_HANG +PCIEIND:0x93 +2-95 +PCIE_LC_CNTL +PCIEIND:0xA0 +2-95 +PCIE_LC_N_FTS_CNTL +PCIEIND:0xA1 +2-95 +PCIE_LC_LINK_WIDTH_CNTL +PCIEIND:0xA2 +2-97 +PCIE_LC_STATE0 +PCIEIND:0xA5 +2-95 +PCIE_LC_STATE1 +PCIEIND:0xA6 +2-96 +PCIE_LC_STATE2 +PCIEIND:0xA7 +2-96 +PCIE_LC_STATE3 +PCIEIND:0xA8 +2-96 +PCIE_LC_STATE4 +PCIEIND:0xA9 +2-96 +PCIE_LC_STATE5 +PCIEIND:0xAA +2-96 +PCIE_LC_FORCE_SYNC_LOSS_CNTL +PCIEIND:0xAB +2-97 +PCIE_P_CNTL +PCIEIND:0xB0 +2-97 +PCIE_P_CNTL2 +PCIEIND:0xB1 +2-98 +PCIE_P_BUF_STATUS +PCIEIND:0xB2 +2-98 +PCIE_P_DECODER_STATUS +PCIEIND:0xB3 +2-99 +PCIE_P_MISC_DEBUG_STATUS +PCIEIND:0xB4 +2-100 +PCIE_P_IMP_CNTL_STRENGTH +PCIEIND:0xC0 +2-101 +PCIE_P_IMP_CNTL_UPDATE +PCIEIND:0xC1 +2-102 +PCIE_P_STR_CNTL_UPDATE +PCIEIND:0xC2 +2-102 +PCIE_P_PAD_MISC_CNTL +PCIEIND:0xC3 +2-102 +PCIE_P_SYMSYNC_CTL +PCIEIND:0xC4 +2-102 +PCIE_P_DECODE_ERR_CNTL +PCIEIND:0xC5 +2-103 +PCIE_ERR_CNTL +PCIEIND:0xE0 +2-105 +PCIE_CLK_RST_CNTL +PCIEIND:0xE1 +2-105 +PCIE_P_DECODE_ERR_CNT_0 +PCIEIND:0xF0 +2-103 +PCIE_P_DECODE_ERR_CNT_1 +PCIEIND:0xF1 +2-103 +PCIE_P_DECODE_ERR_CNT_2 +PCIEIND:0xF2 +2-103 +PCIE_P_DECODE_ERR_CNT_3 +PCIEIND:0xF3 +2-103 +PCIE_P_DECODE_ERR_CNT_4 +PCIEIND:0xF4 +2-103 +PCIE_P_DECODE_ERR_CNT_5 +PCIEIND:0xF5 +2-103 +PCIE_P_DECODE_ERR_CNT_6 +PCIEIND:0xF6 +2-104 +PCIE_P_DECODE_ERR_CNT_7 +PCIEIND:0xF7 +2-104 +PCIE_P_DECODE_ERR_CNT_8 +PCIEIND:0xF8 +2-104 +PCIE_P_DECODE_ERR_CNT_9 +PCIEIND:0xF9 +2-104 +PCIE_P_DECODE_ERR_CNT_10 +PCIEIND:0xFA +2-104 +PCIE_P_DECODE_ERR_CNT_11 +PCIEIND:0xFB +2-104 +PCIE_P_DECODE_ERR_CNT_12 +PCIEIND:0xFC +2-105 +PCIE_P_DECODE_ERR_CNT_13 +PCIEIND:0xFD +2-105 +PCIE_P_DECODE_ERR_CNT_14 +PCIEIND:0xFE +2-105 +PCIE_P_DECODE_ERR_CNT_15 +PCIEIND:0xFF +2-105 diff --git a/regs/rrg_registers.py b/regs/rrg_registers.py new file mode 100644 index 0000000..9e40d2d --- /dev/null +++ b/regs/rrg_registers.py @@ -0,0 +1,37 @@ +import sys + +with open(sys.argv[1]) as f: + buf = f.read() + +prefixes = sys.argv[2:] +assert len(prefixes) >= 1 + +lines = [line.strip() for line in buf.strip().split()] + +assert len(lines) % 3 == 0 + +def parse(lines): + for i in range(len(lines) // 3): + name = lines[i * 3 + 0] + address = lines[i * 3 + 1] + page = lines[i * 3 + 2] + + assert '-' in page, page + orig_address = address + for prefix in prefixes: + if address.startswith(f"{prefix}:"): + address = address.removeprefix(f"{prefix}:") + assert address != orig_address + assert address.startswith("0x") + address = address.removeprefix("0x") + address = int(address, 16) + yield name, address, page + + +for name, address, page in parse(lines): + print("{") + print(f" .name = \"{name}\",") + print(f" .address = {hex(address)},") + print("},") + +#print(f"#define {name} {hex(address)}")