dreamcast/regs/sh7091_bits.csv

1	block	register_name	enum_name	bits	bit_name	value	mask	description
2	CCN	PTEH		31-10	VPN			Virtual Page Number
3	CCN	PTEH		7-0	ASID			Address space identifier
4
5	CCN	PTEL		28-10	PPN			Physical page number
6	CCN	PTEL	V	8	invalid	0		Validity
7	CCN	PTEL	V	8	valid	1		Validity
8	CCN	PTEL	SZ	7,4	1_kbyte_page	0b0000		Page size
9	CCN	PTEL	SZ	7,4	4_kbyte_page	0b0001		Page size
10	CCN	PTEL	SZ	7,4	64_kbyte_page	0b1000		Page size
11	CCN	PTEL	SZ	7,4	1_mbyte_page	0b1001		Page size
12	CCN	PTEL	PR	6-5	read_only_in_privileged_mode	0b00		Protection key data
13	CCN	PTEL	PR	6-5	read_write_in_privileged_mode	0b01		Protection key data
14	CCN	PTEL	PR	6-5	read_only_in_privileged_and_user_mode	0b10		Protection key data
15	CCN	PTEL	PR	6-5	read_write_in_privileged_and_user_mode	0b11		Protection key data
16	CCN	PTEL	C	3	not_cacheable	0		Cacheability bit
17	CCN	PTEL	C	3	cacheable	1		Cacheability bit
18	CCN	PTEL	D	2	write_has_not_been_performed	0		Dirty bit
19	CCN	PTEL	D	2	write_has_been_performed	1		Dirty bit
20	CCN	PTEL	SH	1	pages_are_shared_by_processes	0		Share status bit
21	CCN	PTEL	SH	1	pages_are_not_shared_by_processes	1		Share status bit
22	CCN	PTEL	WT	0	copy_back_mode	0		Write-through bit
23	CCN	PTEL	WT	0	write_through_mode	1		Write-through bit
24
25	CCN	MMUCR		31-26	LRUI			Least recently used ITLB
26	CCN	MMUCR		23-18	URB			UTLB replace boundary
27	CCN	MMUCR		15-10	URC			UTLB replace counter
28	CCN	MMUCR	SQMD	9	user_privileged_access_possible	0		Store queue mode bit
29	CCN	MMUCR	SQMD	9	privileged_access_possible	1		Store queue mode bit
30	CCN	MMUCR	SV	8	multiple_virtual_memory_mode	0		Single virtual mode bit
31	CCN	MMUCR	SV	8	single_virtual_memory_mode	1		Single virtual mode bit
32	CCN	MMUCR	TI	2	invalidate_all_utlb_itlb_bits	1		TLB invalidate
33	CCN	MMUCR	AT	0	mmu_disabled	0		Address translation bit
34	CCN	MMUCR	AT	0	mmu_enabled	1		Address translation bit
35
36	CCN	BASRA		7-0	basa		0xff
37
38	CCN	BASRB		7-0	basa		0xff
39
40	CCN	CCR	IIX	15	address_bits_12_5_used_for_ic_entry_selection	0		IC index enable
41	CCN	CCR	IIX	15	address_bits_25_and_11_5_used_for_ic_entry_selection	1		IC index enable
42	CCN	CCR	ICI	11	clear_v_bits_of_all_ic_entries	1		IC invalidation
43	CCN	CCR	ICE	8	ic_not_used	0		IC enable
44	CCN	CCR	ICE	8	ic_used	1		IC enable
45	CCN	CCR	OIX	7	address_bits_13_5_used_for_oc_entry_selection	0		OC index enable
46	CCN	CCR	OIX	7	address_bits_25_and_12_5_used_for_oc_entry_selection	1		OC index enable
47	CCN	CCR	ORA	5	16_kbytes_used_as_cache	0		OC RAM enable
48	CCN	CCR	ORA	5	8_kbytes_used_as_cache_8_kbytes_used_as_ram	1		OC RAM enable
49	CCN	CCR	OCI	3	clear_v_and_u_bits_of_all_oc_entries	1		OC invalidation
50	CCN	CCR	CB	2	write_through_mode	0		Copy-back enable
51	CCN	CCR	CB	2	copy_back_mode	1		Copy-back enable
52	CCN	CCR	WT	1	copy_back_mode	0		Write-through enable
53	CCN	CCR	WT	1	write_through_mode	1		Write-through enable
54	CCN	CCR	OCE	0	oc_not_used	0		OC enable
55	CCN	CCR	OCE	0	oc_used	1		OC enable
56
57	CCN	TRA		9-2	imm
58
59	CCN	EXPEVT		11-0	exception_code
60
61	CCN	INTEVT		11-0	exception_code
62
63	CCN	PTEA	TC	3	area_5_is_used	0		Timing control bit
64	CCN	PTEA	TC	3	area_6_is_used	1		Timing control bit
65	CCN	PTEA	SA	2-0	undefined	0b000		Space attribute bits
66	CCN	PTEA	SA	2-0	variable_size_io_space	0b001		Space attribute bits
67	CCN	PTEA	SA	2-0	8_bit_io_space	0b010		Space attribute bits
68	CCN	PTEA	SA	2-0	16_bit_io_space	0b011		Space attribute bits
69	CCN	PTEA	SA	2-0	8_bit_common_memory_space	0b100		Space attribute bits
70	CCN	PTEA	SA	2-0	16_bit_common_memory_space	0b101		Space attribute bits
71	CCN	PTEA	SA	2-0	8_bit_attribute_memory_space	0b110		Space attribute bits
72	CCN	PTEA	SA	2-0	16_bit_attribute_memory_space	0b111		Space attribute bits
73
74	CCN	QACR0		4-2	area		0b111
75
76	CCN	QACR1		4-2	area		0b111
77
78	DMAC	DMATCR		23-0	transfer_count		0xffffff
79
80	DMAC	CHCR	SSA	31-29	reserved_in_pcmcia_access	0b000
81	DMAC	CHCR	SSA	31-29	dynamic_bus_sizing_io_space	0b001
82	DMAC	CHCR	SSA	31-29	8_bit_io_space	0b010
83	DMAC	CHCR	SSA	31-29	16_bit_io_space	0b011
84	DMAC	CHCR	SSA	31-29	8_bit_common_memory_space	0b100
85	DMAC	CHCR	SSA	31-29	16_bit_common_memory_space	0b101
86	DMAC	CHCR	SSA	31-29	8_bit_attribute_memory_space	0b110
87	DMAC	CHCR	SSA	31-29	16_bit_attribute_memory_space	0b111
88	DMAC	CHCR	STC	28	c5_space_wait_cycle_selection	0
89	DMAC	CHCR	STC	28	c6_space_wait_cycle_selection	1
90	DMAC	CHCR	DSA	27-25	reserved_in_pcmcia_access	0b000
91	DMAC	CHCR	DSA	27-25	dynamic_bus_sizing_io_space	0b001
92	DMAC	CHCR	DSA	27-25	8_bit_io_space	0b010
93	DMAC	CHCR	DSA	27-25	16_bit_io_space	0b011
94	DMAC	CHCR	DSA	27-25	8_bit_common_memory_space	0b100
95	DMAC	CHCR	DSA	27-25	16_bit_common_memory_space	0b101
96	DMAC	CHCR	DSA	27-25	8_bit_attribute_memory_space	0b110
97	DMAC	CHCR	DSA	27-25	16_bit_attribute_memory_space	0b111
98	DMAC	CHCR	DTC	24	c5_space_wait_cycle_selection	0
99	DMAC	CHCR	DTC	24	c6_space_wait_cycle_selection	1
100	DMAC	CHCR	DS	19	low_level_detection	0
101	DMAC	CHCR	DS	19	falling_edge_detection	1
102	DMAC	CHCR	RL	18	drak_is_an_active_high	0
103	DMAC	CHCR	RL	18	drak_is_an_active_low	1
104	DMAC	CHCR	AM	17	dack_is_output_in_read_cycle	0
105	DMAC	CHCR	AM	17	dack_is_output_in_write_cycle	1
106	DMAC	CHCR	AL	16	active_high_output	0
107	DMAC	CHCR	AL	16	active_low_output	1
108	DMAC	CHCR	DM	15-14	destination_address_fixed	0b00
109	DMAC	CHCR	DM	15-14	destination_address_incremented	0b01
110	DMAC	CHCR	DM	15-14	destination_address_decremented	0b10
111	DMAC	CHCR	SM	13-12	source_address_fixed	0b00
112	DMAC	CHCR	SM	13-12	source_address_incremented	0b01
113	DMAC	CHCR	SM	13-12	source_address_decremented	0b10
114	DMAC	CHCR	RS	11-8	resource_select		0b1111
115	DMAC	CHCR	TM	7	cycle_steal_mode	0
116	DMAC	CHCR	TM	7	cycle_burst_mode	1
117	DMAC	CHCR	TS	6-4	64_bit	0b000
118	DMAC	CHCR	TS	6-4	8_bit	0b001
119	DMAC	CHCR	TS	6-4	16_bit	0b010
120	DMAC	CHCR	TS	6-4	32_bit	0b011
121	DMAC	CHCR	TS	6-4	32_byte	0b100
122	DMAC	CHCR	IE	2	interrupt_request_not_generated	0
123	DMAC	CHCR	IE	2	interrupt_request_generated	1
124	DMAC	CHCR	TE	1	transfers_not_completed	0
125	DMAC	CHCR	TE	1	transfers_completed	1
126	DMAC	CHCR	DE	0	channel_operation_disabled	0
127	DMAC	CHCR	DE	0	channel_operation_enabled	1
128
129	DMAC	DMAOR	DDT	15	normal_dma_mode	0
130	DMAC	DMAOR	DDT	15	on_demand_data_transfer_mode	1
131	DMAC	DMAOR	PR	9-8	ch0_ch1_ch2_ch3	0b00
132	DMAC	DMAOR	PR	9-8	ch0_ch2_ch3_ch1	0b01
133	DMAC	DMAOR	PR	9-8	ch2_ch0_ch1_ch3	0b10
134	DMAC	DMAOR	PR	9-8	round_robin	0b11
135	DMAC	DMAOR	AE	2	no_address_error__dma_transfer_enabled	0
136	DMAC	DMAOR	AE	2	address_error__dma_transfer_disabled	1
137	DMAC	DMAOR	NMIF	1	no_nmi__dma_transfer_enabled	0
138	DMAC	DMAOR	NMIF	1	nmi__dma_transfer_disabled	1
139	DMAC	DMAOR	DME	0	operation_disabled_on_all_channels	0
140	DMAC	DMAOR	DME	0	operation_enabled_on_all_channels	1
141
142	INTC	ICR	NMIL	15	pin_input_level_is_low	0
143	INTC	ICR	NMIL	15	pin_input_level_is_high	1
144	INTC	ICR	MAI	14	interrupts_enabled_while_nmi_pin_is_low	0
145	INTC	ICR	MAI	14	interrupts_disabled_while_nmi_pin_is_low	1
146	INTC	ICR	NMIB	9	interrupt_requests_witheld	0
147	INTC	ICR	NMIB	9	interrupt_requests_detected	1
148	INTC	ICR	NMIE	8	interrupt_on_falling_edge_of_nmi	0
149	INTC	ICR	NMIE	8	interrupt_on_rising_edge_of_nmi	1
150	INTC	ICR	IRLM	7	level_encoded_interrupt_requests	0
151	INTC	ICR	IRLM	7	independent_interrupt_request	1
152
153	INTC	IPRA		15-12	TMU0		0b1111
154	INTC	IPRA		11-8	TMU1		0b1111
155	INTC	IPRA		7-4	TMU2		0b1111
156	INTC	IPRA		3-0	RTC		0b1111
157
158	INTC	IPRB		15-12	WDT		0b1111
159	INTC	IPRB		11-8	REF		0b1111
160	INTC	IPRB		7-4	SCI1		0b1111
161
162	INTC	IPRC		15-12	GPIO		0b1111
163	INTC	IPRC		11-8	DMAC		0b1111
164	INTC	IPRC		7-4	SCIF		0b1111
165	INTC	IPRC		3-0	UDI		0b1111
166
167	TMU	TOCR	TCOE	0	tclk_is_external_clock_or_input_capture	0		Timer Clock Pin Control
168	TMU	TOCR	TCOE	0	tclk_is_on_chip_rtc	1		Timer Clock Pin Control
169
170	TMU	TSTR	STR2	2	counter_start	1		Counter Start 2
171	TMU	TSTR	STR1	1	counter_start	1		Counter Start 1
172	TMU	TSTR	STR0	0	counter_start	1		Counter Start 0
173
174	TMU	TCR0		8	UNF	1		Underflow Flag
175	TMU	TCR0		5	UNIE	1		Underflow Interrupt Control
176	TMU	TCR0	CKEG	4-3	rising	0b00		Clock Edge
177	TMU	TCR0	CKEG	4-3	falling	0b01		Clock Edge
178	TMU	TCR0	CKEG	4-3	rising_falling	0b10		Clock Edge
179	TMU	TCR0	TPSC	2-0	p_phi_4	0b000		Timer Prescaler
180	TMU	TCR0	TPSC	2-0	p_phi_16	0b001		Timer Prescaler
181	TMU	TCR0	TPSC	2-0	p_phi_64	0b010		Timer Prescaler
182	TMU	TCR0	TPSC	2-0	p_phi_256	0b011		Timer Prescaler
183	TMU	TCR0	TPSC	2-0	p_phi_1024	0b100		Timer Prescaler
184	TMU	TCR0	TPSC	2-0	rtc_output	0b110		Timer Prescaler
185	TMU	TCR0	TPSC	2-0	external	0b111		Timer Prescaler
186
187	TMU	TCR1		8	UNF	1		Underflow Flag
188	TMU	TCR1		5	UNIE	1		Underflow Interrupt Control
189	TMU	TCR1	CKEG	4-3	rising	0b00		Clock Edge
190	TMU	TCR1	CKEG	4-3	falling	0b01		Clock Edge
191	TMU	TCR1	CKEG	4-3	rising_falling	0b10		Clock Edge
192	TMU	TCR1	TPSC	2-0	p_phi_4	0b000		Timer Prescaler
193	TMU	TCR1	TPSC	2-0	p_phi_16	0b001		Timer Prescaler
194	TMU	TCR1	TPSC	2-0	p_phi_64	0b010		Timer Prescaler
195	TMU	TCR1	TPSC	2-0	p_phi_256	0b011		Timer Prescaler
196	TMU	TCR1	TPSC	2-0	p_phi_1024	0b100		Timer Prescaler
197	TMU	TCR1	TPSC	2-0	rtc_output	0b110		Timer Prescaler
198	TMU	TCR1	TPSC	2-0	external	0b111		Timer Prescaler
199
200	TMU	TCR2		9	ICPF	1		Input Capture Interrupt Flag
201	TMU	TCR2		8	UNF	1		Underflow Flag
202	TMU	TCR2	ICPE	7-6	disabled	0b00		Input Capture Control
203	TMU	TCR2	ICPE	7-6	enabled	0b10		Input Capture Control
204	TMU	TCR2	ICPE	7-6	enabled_with_interrupts	0b11		Input Capture Control
205	TMU	TCR2		5	UNIE	1		Underflow Interrupt Control
206	TMU	TCR2	CKEG	4-3	rising	0b00		Clock Edge
207	TMU	TCR2	CKEG	4-3	falling	0b01		Clock Edge
208	TMU	TCR2	CKEG	4-3	rising_falling	0b10		Clock Edge
209	TMU	TCR2	TPSC	2-0	p_phi_4	0b000		Timer Prescaler
210	TMU	TCR2	TPSC	2-0	p_phi_16	0b001		Timer Prescaler
211	TMU	TCR2	TPSC	2-0	p_phi_64	0b010		Timer Prescaler
212	TMU	TCR2	TPSC	2-0	p_phi_256	0b011		Timer Prescaler
213	TMU	TCR2	TPSC	2-0	p_phi_1024	0b100		Timer Prescaler
214	TMU	TCR2	TPSC	2-0	rtc_output	0b110		Timer Prescaler
215	TMU	TCR2	TPSC	2-0	external	0b111		Timer Prescaler
216
217	SCIF	SCSMR2	CHR	6	8_bit_data	0
218	SCIF	SCSMR2	CHR	6	7_bit_data	1
219	SCIF	SCSMR2	PE	5	parity_disabled	0
220	SCIF	SCSMR2	PE	5	parity_enabled	1
221	SCIF	SCSMR2	OE	4	even_parity	0
222	SCIF	SCSMR2	OE	4	odd_parity	1
223	SCIF	SCSMR2	STOP	3	1_stop_bit	0
224	SCIF	SCSMR2	STOP	3	2_stop_bits	1
225	SCIF	SCSMR2	CKS	1-0	p_phi_clock	0b00
226	SCIF	SCSMR2	CKS	1-0	p_phi_4_clock	0b01
227	SCIF	SCSMR2	CKS	1-0	p_phi_16_clock	0b10
228	SCIF	SCSMR2	CKS	1-0	p_phi_64_clock	0b11
229
230	SCIF	SCSCR2	TIE	7	transmit_fifo_data_empty_interrupt_disabled	0
231	SCIF	SCSCR2	TIE	7	transmit_fifo_data_empty_interrupt_enabled	1
232	SCIF	SCSCR2	RIE	6	request_disabled	0
233	SCIF	SCSCR2	RIE	6	request_enabled	1
234	SCIF	SCSCR2	TE	5	transmission_disabled	0
235	SCIF	SCSCR2	TE	5	transmission_enabled	1
236	SCIF	SCSCR2	RE	4	reception_disabled	0
237	SCIF	SCSCR2	RE	4	reception_enabled	1
238	SCIF	SCSCR2	REIE	3	requests_disabled	0
239	SCIF	SCSCR2	REIE	3	requests_enabled	1
240	SCIF	SCSCR2	CKE1	1	sck2_pin_functions_as_input_pin	0
241	SCIF	SCSCR2	CKE1	1	sck2_pin_functions_as_clock_input	1
242
243	SCIF	SCFSR2	PER3_0	15-12	number_of_parity_errors
244	SCIF	SCFSR2	FER3_0	11-8	number_of_framing_errors
245	SCIF	SCFSR2	ER	7	no_framing_error_or_parity_error	0
246	SCIF	SCFSR2	ER	7	framing_error_or_parity_error	1
247	SCIF	SCFSR2	TEND	6	transmission_in_progress	0
248	SCIF	SCFSR2	TEND	6	transmission_has_ended	1
249	SCIF	SCFSR2	TDFE	5	transmit_data_bytes_does_exceed_trigger	0
250	SCIF	SCFSR2	TDFE	5	transmit_data_bytes_does_not_exceed_trigger	1
251	SCIF	SCFSR2	BRK	4	break_not_received	0
252	SCIF	SCFSR2	BRK	4	break_received	1
253	SCIF	SCFSR2	FER	3	no_framing_error	0
254	SCIF	SCFSR2	FER	3	framing_error	1
255	SCIF	SCFSR2	PER	2	parity_error	0
256	SCIF	SCFSR2	PER	2	no_parity_error	1
257	SCIF	SCFSR2	RDF	1	receive_data_bytes_less_than_receive_trigger	0
258	SCIF	SCFSR2	RDF	1	receive_data_bytes_greater_than_or_equal_receive_trigger	1
259	SCIF	SCFSR2	DR	0	reception_is_in_progress	0
260	SCIF	SCFSR2	DR	0	no_further_data_has_arrived	1
261
262	SCIF	SCFCR2	RTRG	7-6	trigger_on_1_byte	0b00
263	SCIF	SCFCR2	RTRG	7-6	trigger_on_4_bytes	0b01
264	SCIF	SCFCR2	RTRG	7-6	trigger_on_8_bytes	0b10
265	SCIF	SCFCR2	RTRG	7-6	trigger_on_14_byte	0b11
266	SCIF	SCFCR2	TTRG	5-4	trigger_on_8_bytes	0b00
267	SCIF	SCFCR2	TTRG	5-4	trigger_on_4_bytes	0b01
268	SCIF	SCFCR2	TTRG	5-4	trigger_on_2_bytes	0b10
269	SCIF	SCFCR2	TTRG	5-4	trigger_on_1_bytes	0b11
270	SCIF	SCFCR2	MCE	3	modem_signals_disabled	0
271	SCIF	SCFCR2	MCE	3	modem_signals_enabled	1
272	SCIF	SCFCR2	TFRST	2	reset_operation_disabled	0
273	SCIF	SCFCR2	TFRST	2	reset_operation_enabled	1
274	SCIF	SCFCR2	RFRST	1	reset_operation_disabled	0
275	SCIF	SCFCR2	RFRST	1	reset_operation_enabled	1
276	SCIF	SCFCR2	LOOP	0	loopback_test_disabled	0
277	SCIF	SCFCR2	LOOP	0	loopback_test_enabled	1
278
279	SCIF	SCFDR2		12-8	transmit_data_bytes
280	SCIF	SCFDR2		4-0	receive_data_bytes
281
282	SCIF	SCSPTR2	RTSIO	7	rtsdt_not_output_to_rts2	0
283	SCIF	SCSPTR2	RTSIO	7	rtsdt_output_to_rts2	1
284	SCIF	SCSPTR2	RTSDT	6	input_output_data_is_low_level	0
285	SCIF	SCSPTR2	RTSDT	6	input_output_data_is_high_level	1
286	SCIF	SCSPTR2	CTSIO	5	ctsdt_is_not_output_to_cts2	0
287	SCIF	SCSPTR2	CTSIO	5	ctsdt_is_output_to_cts2	1
288	SCIF	SCSPTR2	CTSDT	4	input_output_data_is_low_level	0
289	SCIF	SCSPTR2	CTSDT	4	input_output_data_is_high_level	1
290	SCIF	SCSPTR2	SPB2IO	1	spb2dt_is_not_output_to_txd2	0
291	SCIF	SCSPTR2	SPB2IO	1	spb2dt_is_output_to_txd2	1
292	SCIF	SCSPTR2	SPB2DT	0	input_output_data_is_low_level	0
293	SCIF	SCSPTR2	SPB2DT	0	input_output_data_is_high_level	1
294
295	SCIF	SCLSR2	ORER	0	overrun_error_occured	1
296
297	SH	SR		30	md	1
298	SH	SR		29	rb	1
299	SH	SR		28	bl	1
300	SH	SR		15	fd	1
301	SH	SR		9	m	1
302	SH	SR		8	q	1
303	SH	SR		7-4	imask		0b1111
304	SH	SR		1	s	1
305	SH	SR		0	t	1
306
307	SH	FPSCR		21	fr	1
308	SH	FPSCR		20	sz	1
309	SH	FPSCR		19	pr	1
310	SH	FPSCR		18	dn	1
311	SH	FPSCR	CAUSE	17-12	fpu_error	0b100000
312	SH	FPSCR	CAUSE	17-12	invalid_operation	0b010000
313	SH	FPSCR	CAUSE	17-12	division_by_zero	0b001000
314	SH	FPSCR	CAUSE	17-12	overflow	0b000100
315	SH	FPSCR	CAUSE	17-12	underflow	0b000010
316	SH	FPSCR	CAUSE	17-12	inexact	0b000001
317	SH	FPSCR	ENABLED	11-7	invalid_operation	0b10000
318	SH	FPSCR	ENABLED	11-7	division_by_zero	0b01000
319	SH	FPSCR	ENABLED	11-7	overflow	0b00100
320	SH	FPSCR	ENABLED	11-7	underflow	0b00010
321	SH	FPSCR	ENABLED	11-7	inexact	0b00001
322	SH	FPSCR	FLAG	6-2	invalid_operation	0b10000
323	SH	FPSCR	FLAG	6-2	division_by_zero	0b01000
324	SH	FPSCR	FLAG	6-2	overflow	0b00100
325	SH	FPSCR	FLAG	6-2	underflow	0b00010
326	SH	FPSCR	FLAG	6-2	inexact	0b00001
327	SH	FPSCR	RM	1-0	round_to_nearest	0b00
328	SH	FPSCR	RM	1-0	round_to_zero	0b01
329
330	UBC	BAMRA	BAMA	3,1,0	all_bara_bits_are_included_in_break_conditions	0b0000
331	UBC	BAMRA	BAMA	3,1,0	lower_10_bits_of_bara_are_not_included_in_break_conditions	0b0001
332	UBC	BAMRA	BAMA	3,1,0	lower_12_bits_of_bara_are_not_included_in_break_conditions	0b0010
333	UBC	BAMRA	BAMA	3,1,0	all_bara_bits_are_not_included_in_break_conditions	0b0011
334	UBC	BAMRA	BAMA	3,1,0	lower_16_bits_of_bara_are_not_included_in_break_conditions	0b1000
335	UBC	BAMRA	BAMA	3,1,0	lower_20_bits_of_bara_are_not_included_in_break_conditions	0b1001
336	UBC	BAMRA	BASMA	2	all_basra_bits_are_included_in_break_conditions	0
337	UBC	BAMRA	BASMA	2	no_basra_bits_are_included_in_break_conditions	1
338
339	UBC	BBRA	SZA	6,1,0	operand_size_is_not_included_in_break_conditions	0b00
340	UBC	BBRA	SZA	6,1,0	byte_access_is_used_as_break_condition	0b01
341	UBC	BBRA	SZA	6,1,0	word_access_is_used_as_break_condition	0b10
342	UBC	BBRA	SZA	6,1,0	longword_access_is_used_as_break_condition	0b11
343	UBC	BBRA	SZA	6,1,0	quadword_access_is_used_as_break_condition	0b1000000
344	UBC	BBRA	IDA	5-4	condition_comparison_is_not_performed	0b00
345	UBC	BBRA	IDA	5-4	instruction_access_cycle_is_used_as_break_condition	0b01
346	UBC	BBRA	IDA	5-4	operand_access_cycle_is_used_as_break_condition	0b10
347	UBC	BBRA	IDA	5-4	instruction_access_cycle_or_operand_access_cycle_is_used_as_break_condition	0b11
348	UBC	BBRA	RWA	3-2	condition_comparison_is_not_performed	0b00
349	UBC	BBRA	RWA	3-2	read_cycle_is_used_as_break_condition	0b01
350	UBC	BBRA	RWA	3-2	write_cycle_is_used_as_break_condition	0b10
351	UBC	BBRA	RWA	3-2	read_cycle_or_write_cycle_is_used_as_break_condition	0b11
352
353	UBC	BRCR	CMFA	15	channel_a_break_condition_is_not_matched	0
354	UBC	BRCR	CMFA	15	channel_a_break_condition_match_has_occured	1
355	UBC	BRCR	CMFB	14	channel_b_break_condition_is_not_matched	0
356	UBC	BRCR	CMFB	14	channel_b_break_condition_match_has_occured	1
357	UBC	BRCR	PCBA	10	channel_a_pc_break_is_effected_before_instruction_execution	0
358	UBC	BRCR	PCBA	10	channel_a_pc_break_is_effected_after_instruction_execution	1
359	UBC	BRCR	DBEB	7	data_bus_condition_is_not_included_in_channel_b_conditions	0
360	UBC	BRCR	DBEB	7	data_bus_condition_is_included_in_channel_b_conditions	1
361	UBC	BRCR	PCBB	6	channel_b_pc_break_is_effected_before_instruction_execution	0
362	UBC	BRCR	PCBB	6	channel_b_pc_break_is_effected_after_instruction_execution	1
363	UBC	BRCR	SEQ	3	channel_a_and_b_comparison_are_performed_as_independent_condition	0
364	UBC	BRCR	SEQ	3	channel_a_and_b_comparison_are_performed_as_sequential_condition	1
365	UBC	BRCR	UBDE	0	user_break_debug_function_is_not_used	0
366	UBC	BRCR	UBDE	0	user_break_debug_function_is_used	1