example: add UBC experiment

This commit is contained in:
Zack Buhman 2024-11-12 20:37:40 -06:00
parent 1d25d54bb1
commit d32bd87baa
13 changed files with 1468 additions and 721 deletions

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@ -1,6 +1,8 @@
.global _illslot
_illslot:
trapa #12
rts
mova test,r0
nop
mova test,r0
test: .long 0x12345678

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@ -11,9 +11,11 @@ void vbr100()
{
serial::string("vbr100\n");
serial::string("expevt ");
serial::integer(sh7091.CCN.EXPEVT);
serial::integer<uint16_t>(sh7091.CCN.EXPEVT);
serial::string("intevt ");
serial::integer(sh7091.CCN.INTEVT);
serial::integer<uint16_t>(sh7091.CCN.INTEVT);
serial::string("tra ");
serial::integer<uint16_t>(sh7091.CCN.TRA);
uint32_t spc;
uint32_t ssr;
asm volatile ("stc spc,%0"
@ -42,9 +44,53 @@ void vbr600()
while (1);
}
__attribute__ ((interrupt_handler))
void dbr();
void dbr()
{
serial::string("dbr\n");
serial::string("expevt ");
serial::integer<uint16_t>(sh7091.CCN.EXPEVT);
serial::string("intevt ");
serial::integer<uint16_t>(sh7091.CCN.INTEVT);
serial::string("tra ");
serial::integer<uint16_t>(sh7091.CCN.TRA);
uint32_t spc;
uint32_t ssr;
asm volatile ("stc spc,%0" : "=r" (spc) );
asm volatile ("stc ssr,%0" : "=r" (ssr) );
serial::string("spc ");
serial::integer(spc);
serial::string("ssr ");
serial::integer(ssr);
uint32_t sr;
asm volatile ("stc sr,%0" : "=r" (sr) );
serial::string("sr ");
serial::integer(sr);
return;
}
int do_stuff(int a, int b)
{
serial::string("do_stuff\n");
asm volatile ("nop;");
return a + b;
}
extern "C" uint32_t * illslot(void);
void main()
{
serial::string("main\n");
for (int i = 0; i < 10000000; i++) {
asm volatile ("nop;");
}
//serial::init(0);
uint32_t vbr = reinterpret_cast<uint32_t>(&__vbr_link_start) - 0x100;
system.IML2NRM = 0;
@ -83,24 +129,64 @@ void main()
serial::string("sr ");
serial::integer<uint32_t>(sr);
sr = sr & (~(1 << 28)); // BL
sr &= ~sh::sr::bl; // BL
sr |= sh::sr::imask(15); // imask
asm volatile ("ldc %0, sr"
serial::string("sr ");
serial::integer<uint32_t>(sr);
asm volatile ("ldc %0,sr"
:
: "r" (sr));
/*
uint32_t vbr2;
asm volatile ("stc vbr,%0"
: "=r" (vbr2));
*/
serial::string("vbr ");
serial::integer<uint32_t>(vbr);
//serial::integer<uint32_t>(vbr2);
serial::string("vbr100 ");
serial::integer<uint32_t>(reinterpret_cast<uint32_t>(&vbr100));
uint32_t * test = illslot();
serial::integer<uint32_t>(*test);
(void)dbr;
uint32_t dbr_address = reinterpret_cast<uint32_t>(&dbr);
asm volatile ("ldc %0,dbr"
:
: "r" (dbr_address));
serial::string("dbr ");
serial::integer<uint32_t>(dbr_address);
while (1);
sh7091.UBC.BARA = reinterpret_cast<uint32_t>(&do_stuff);
sh7091.CCN.BASRA = 0;
sh7091.UBC.BAMRA
= ubc::bamra::bama::all_bara_bits_are_included_in_break_conditions
| ubc::bamra::basma::no_basra_bits_are_included_in_break_conditions
;
sh7091.UBC.BBRA
= ubc::bbra::sza::operand_size_is_not_included_in_break_conditions
| ubc::bbra::ida::instruction_access_cycle_is_used_as_break_condition
| ubc::bbra::rwa::read_cycle_or_write_cycle_is_used_as_break_condition
;
sh7091.UBC.BRCR
= ubc::brcr::pcba::channel_a_pc_break_is_effected_before_instruction_execution
| ubc::brcr::ubde::user_break_debug_function_is_used
;
serial::string("basra ");
serial::integer(sh7091.CCN.BASRA);
serial::string("bara ");
serial::integer(sh7091.UBC.BARA);
serial::string("bamra ");
serial::integer(sh7091.UBC.BAMRA);
serial::string("bbra ");
serial::integer(sh7091.UBC.BBRA);
serial::string("brcr ");
serial::integer(sh7091.UBC.BRCR);
int res = do_stuff(1, 2);
(void)res;
/*
uint32_t * test = illslot();
serial::string("illslot\n");
serial::integer<uint32_t>(*test);
*/
serial::string("return\n");
//while (1);
}

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@ -7,15 +7,15 @@
void main()
{
serial::init(0);
//serial::init(0);
uint32_t send_buf[1024] __attribute__((aligned(32)));
uint32_t recv_buf[1024] __attribute__((aligned(32)));
uint8_t send_buf[1024] __attribute__((aligned(32)));
uint8_t recv_buf[1024] __attribute__((aligned(32)));
using command_type = maple::device_request;
using response_type = maple::device_status;
auto writer = maple::host_command_writer(send_buf, recv_buf);
auto writer = maple::host_command_writer<>(send_buf, recv_buf);
auto [host_command, host_response]
= writer.append_command_all_ports<command_type, response_type>();
@ -47,5 +47,5 @@ void main()
}
}
while (1);
//while (1);
}

2
ip.lds
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@ -99,4 +99,4 @@ __vbr_load_end = 0;
INCLUDE "addresses.lds"
__send_buf = 0xac000020;
__recv_buf = 0xac002020;
__recv_buf = 0xac004020;

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@ -75,4 +75,4 @@ INCLUDE "addresses.lds"
__stack_end = 0x8c00f000;
__send_buf = 0xac000020;
__recv_buf = 0xac002020;
__recv_buf = 0xac004000;

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@ -107,12 +107,10 @@ uint32_t init_block_write(uint32_t * command_buf, uint32_t * receive_buf,
}
*/
static inline void _dma_start(const uint32_t * command_buf)
static inline void _dma_start(const uint8_t * command_buf)
{
using namespace dmac;
//command_buf = reinterpret_cast<uint32_t *>(reinterpret_cast<uint32_t>(command_buf) | 0xa000'0000);
sh7091.DMAC.DMAOR = dmaor::ddt::on_demand_data_transfer_mode /* on-demand data transfer mode */
| dmaor::pr::ch2_ch0_ch1_ch3 /* priority mode; CH2 > CH0 > CH1 > CH3 */
| dmaor::dme::operation_enabled_on_all_channels; /* DMAC master enable */
@ -161,9 +159,9 @@ bool dma_poll_complete()
return complete;
}
void dma_start(const uint32_t * send_buf,
void dma_start(uint8_t const * const send_buf,
const uint32_t send_size,
const uint32_t * recv_buf,
uint8_t * const recv_buf,
const uint32_t recv_size
)
{
@ -171,7 +169,7 @@ void dma_start(const uint32_t * send_buf,
for (uint32_t i = 0; i < align_32byte(send_size) / 32; i++) {
asm volatile ("ocbwb @%0"
: // output
: "r" (reinterpret_cast<uint32_t>(&send_buf[(32 * i) / 4])) // input
: "r" (reinterpret_cast<uint32_t>(&send_buf[32 * i])) // input
);
}
@ -182,7 +180,7 @@ void dma_start(const uint32_t * send_buf,
for (uint32_t i = 0; i < align_32byte(recv_size) / 32; i++) {
asm volatile ("ocbp @%0"
: // output
: "r" (reinterpret_cast<uint32_t>(&recv_buf[(32 * i) / 4])) // input
: "r" (reinterpret_cast<uint32_t>(&recv_buf[32 * i])) // input
);
}
}

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@ -38,9 +38,9 @@ void dma_wait_complete();
bool dma_poll_complete();
void dma_start(uint32_t const * const command_buf,
void dma_start(uint8_t const * const command_buf,
const uint32_t command_size,
uint32_t const * const receive_buf,
uint8_t * const receive_buf,
const uint32_t receive_size
);

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@ -12,14 +12,15 @@ namespace maple {
template <uint32_t base_address = 0>
struct host_command_writer {
uint32_t * const send_buf;
uint32_t * const recv_buf;
uint8_t * const send_buf;
uint8_t * const recv_buf;
uint32_t send_offset;
uint32_t recv_offset;
uint32_t last_send_offset;
constexpr host_command_writer(uint32_t * const send_buf,
uint32_t * const recv_buf)
: send_buf(send_buf), recv_buf(recv_buf), send_offset(0), recv_offset(0)
constexpr host_command_writer(uint8_t * const send_buf,
uint8_t * const recv_buf)
: send_buf(send_buf), recv_buf(recv_buf), send_offset(0), recv_offset(0), last_send_offset(0)
{ }
template <typename C, typename R>
@ -38,8 +39,8 @@ struct host_command_writer {
static_assert((sizeof (command_type)) % 4 == 0);
static_assert((sizeof (response_type)) % 4 == 0);
auto host_command = reinterpret_cast<command_type *>(&send_buf[send_offset / 4]);
auto host_response = reinterpret_cast<response_type *>(&recv_buf[recv_offset / 4]);
auto host_command = reinterpret_cast<command_type *>(&send_buf[send_offset]);
auto host_response = reinterpret_cast<response_type *>(&recv_buf[recv_offset]);
host_command->host_instruction = (end_flag ? host_instruction::end_flag : 0)
| (host_port_select & host_instruction::port_select::bit_mask)
@ -59,6 +60,7 @@ struct host_command_writer {
host_command->bus_data.source_ap = destination_ap & ap::port_select::bit_mask;
host_command->bus_data.data_size = data_size / 4;
last_send_offset = send_offset;
send_offset += (sizeof (command_type)) + send_trailing;
recv_offset += (sizeof (response_type)) + recv_trailing;
@ -76,6 +78,22 @@ struct host_command_writer {
append_command<C, R>(host_instruction::port_select::d, ap::de::device | ap::port_select::d, true);
return ret;
}
void set_end_flag()
{
using host_command_type = maple::host_command<uint8_t[0]>;
auto host_command = reinterpret_cast<host_command_type *>(&send_buf[last_send_offset]);
host_command->host_instruction |= host_instruction::end_flag;
}
uint32_t reset()
{
const uint32_t old_recv_offset = recv_offset;
// reset writer
send_offset = 0;
recv_offset = 0;
return old_recv_offset;
}
};
}

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@ -15,22 +15,26 @@ def aggregate_registers(d):
return dict(aggregated)
def parse_bit_number(s):
assert '-' not in s
assert '-' not in s, s
assert ',' not in s, s
return int(s, 10)
def parse_bit_set(s, split_char):
assert len(list(c for c in s if c == split_char)) == 1
left, right = map(parse_bit_number, s.split(split_char, maxsplit=1))
assert left > right, (left, right)
return left, right
def parse_bit_set(s, split_char, maxsplit):
#assert len(list(c for c in s if c == split_char)) == 1, s
split = list(map(parse_bit_number, s.split(split_char, maxsplit=maxsplit)))
for i in range(len(split) - 1):
left = split[i]
right = split[i+1]
assert left > right, (left, right)
return split
def parse_bit_range(s):
if '-' in s:
left, right = parse_bit_set(s, '-')
left, right = parse_bit_set(s, '-', 1)
return set(range(right, left+1))
elif ',' in s:
left, right = parse_bit_set(s, ',')
return set([right, left])
bits = parse_bit_set(s, ',', -1)
return set(bits)
else:
num = parse_bit_number(s)
return set([num])
@ -124,8 +128,10 @@ def aggregate_all_enums(aggregated):
'''
def mask_from_bits(bits):
h, l = max(bits), min(bits)
mask = 2 ** ((h - l) + 1) - 1
mask = 0
for b in bits:
mask |= 1 << b
mask >>= min(bits)
return mask
def parse_value(value):

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@ -293,3 +293,74 @@
"SCIF","SCSPTR2","SPB2DT","0","input_output_data_is_high_level","1",,
,,,,,,,
"SCIF","SCLSR2","ORER","0","overrun_error_occured","1",,
,,,,,,,
"SH","SR",,"30","md","1",,
"SH","SR",,"29","rb","1",,
"SH","SR",,"28","bl","1",,
"SH","SR",,"15","fd","1",,
"SH","SR",,"9","m","1",,
"SH","SR",,"8","q","1",,
"SH","SR",,"7-4","imask",,"0b1111",
"SH","SR",,"1","s","1",,
"SH","SR",,"0","t","1",,
,,,,,,,
"SH","FPSCR",,"21","fr","1",,
"SH","FPSCR",,"20","sz","1",,
"SH","FPSCR",,"19","pr","1",,
"SH","FPSCR",,"18","dn","1",,
"SH","FPSCR","CAUSE","17-12","fpu_error","0b100000",,
"SH","FPSCR","CAUSE","17-12","invalid_operation","0b010000",,
"SH","FPSCR","CAUSE","17-12","division_by_zero","0b001000",,
"SH","FPSCR","CAUSE","17-12","overflow","0b000100",,
"SH","FPSCR","CAUSE","17-12","underflow","0b000010",,
"SH","FPSCR","CAUSE","17-12","inexact","0b000001",,
"SH","FPSCR","ENABLED","11-7","invalid_operation","0b10000",,
"SH","FPSCR","ENABLED","11-7","division_by_zero","0b01000",,
"SH","FPSCR","ENABLED","11-7","overflow","0b00100",,
"SH","FPSCR","ENABLED","11-7","underflow","0b00010",,
"SH","FPSCR","ENABLED","11-7","inexact","0b00001",,
"SH","FPSCR","FLAG","6-2","invalid_operation","0b10000",,
"SH","FPSCR","FLAG","6-2","division_by_zero","0b01000",,
"SH","FPSCR","FLAG","6-2","overflow","0b00100",,
"SH","FPSCR","FLAG","6-2","underflow","0b00010",,
"SH","FPSCR","FLAG","6-2","inexact","0b00001",,
"SH","FPSCR","RM","1-0","round_to_nearest","0b00",,
"SH","FPSCR","RM","1-0","round_to_zero","0b01",,
,,,,,,,
"UBC","BAMRA","BAMA","3,1,0","all_bara_bits_are_included_in_break_conditions","0b0000",,
"UBC","BAMRA","BAMA","3,1,0","lower_10_bits_of_bara_are_not_included_in_break_conditions","0b0001",,
"UBC","BAMRA","BAMA","3,1,0","lower_12_bits_of_bara_are_not_included_in_break_conditions","0b0010",,
"UBC","BAMRA","BAMA","3,1,0","all_bara_bits_are_not_included_in_break_conditions","0b0011",,
"UBC","BAMRA","BAMA","3,1,0","lower_16_bits_of_bara_are_not_included_in_break_conditions","0b1000",,
"UBC","BAMRA","BAMA","3,1,0","lower_20_bits_of_bara_are_not_included_in_break_conditions","0b1001",,
"UBC","BAMRA","BASMA","2","all_basra_bits_are_included_in_break_conditions","0",,
"UBC","BAMRA","BASMA","2","no_basra_bits_are_included_in_break_conditions","1",,
,,,,,,,
"UBC","BBRA","SZA","6,1,0","operand_size_is_not_included_in_break_conditions","0b00",,
"UBC","BBRA","SZA","6,1,0","byte_access_is_used_as_break_condition","0b01",,
"UBC","BBRA","SZA","6,1,0","word_access_is_used_as_break_condition","0b10",,
"UBC","BBRA","SZA","6,1,0","longword_access_is_used_as_break_condition","0b11",,
"UBC","BBRA","SZA","6,1,0","quadword_access_is_used_as_break_condition","0b1000000",,
"UBC","BBRA","IDA","5-4","condition_comparison_is_not_performed","0b00",,
"UBC","BBRA","IDA","5-4","instruction_access_cycle_is_used_as_break_condition","0b01",,
"UBC","BBRA","IDA","5-4","operand_access_cycle_is_used_as_break_condition","0b10",,
"UBC","BBRA","IDA","5-4","instruction_access_cycle_or_operand_access_cycle_is_used_as_break_condition","0b11",,
"UBC","BBRA","RWA","3-2","condition_comparison_is_not_performed","0b00",,
"UBC","BBRA","RWA","3-2","read_cycle_is_used_as_break_condition","0b01",,
"UBC","BBRA","RWA","3-2","write_cycle_is_used_as_break_condition","0b10",,
"UBC","BBRA","RWA","3-2","read_cycle_or_write_cycle_is_used_as_break_condition","0b11",,
,,,,,,,
"UBC","BRCR","CMFA","15","channel_a_break_condition_is_not_matched","0",,
"UBC","BRCR","CMFA","15","channel_a_break_condition_match_has_occured","1",,
"UBC","BRCR","CMFB","14","channel_b_break_condition_is_not_matched","0",,
"UBC","BRCR","CMFB","14","channel_b_break_condition_match_has_occured","1",,
"UBC","BRCR","PCBA","10","channel_a_pc_break_is_effected_before_instruction_execution","0",,
"UBC","BRCR","PCBA","10","channel_a_pc_break_is_effected_after_instruction_execution","1",,
"UBC","BRCR","DBEB","7","data_bus_condition_is_not_included_in_channel_b_conditions","0",,
"UBC","BRCR","DBEB","7","data_bus_condition_is_included_in_channel_b_conditions","1",,
"UBC","BRCR","PCBB","6","channel_b_pc_break_is_effected_before_instruction_execution","0",,
"UBC","BRCR","PCBB","6","channel_b_pc_break_is_effected_after_instruction_execution","1",,
"UBC","BRCR","SEQ","3","channel_a_and_b_comparison_are_performed_as_independent_condition","0",,
"UBC","BRCR","SEQ","3","channel_a_and_b_comparison_are_performed_as_sequential_condition","1",,
"UBC","BRCR","UBDE","0","user_break_debug_function_is_not_used","0",,
"UBC","BRCR","UBDE","0","user_break_debug_function_is_used","1",,

1 block register_name enum_name bits bit_name value mask description
293 SCIF SCSPTR2 SPB2DT 0 input_output_data_is_high_level 1
294
295 SCIF SCLSR2 ORER 0 overrun_error_occured 1
296
297 SH SR 30 md 1
298 SH SR 29 rb 1
299 SH SR 28 bl 1
300 SH SR 15 fd 1
301 SH SR 9 m 1
302 SH SR 8 q 1
303 SH SR 7-4 imask 0b1111
304 SH SR 1 s 1
305 SH SR 0 t 1
306
307 SH FPSCR 21 fr 1
308 SH FPSCR 20 sz 1
309 SH FPSCR 19 pr 1
310 SH FPSCR 18 dn 1
311 SH FPSCR CAUSE 17-12 fpu_error 0b100000
312 SH FPSCR CAUSE 17-12 invalid_operation 0b010000
313 SH FPSCR CAUSE 17-12 division_by_zero 0b001000
314 SH FPSCR CAUSE 17-12 overflow 0b000100
315 SH FPSCR CAUSE 17-12 underflow 0b000010
316 SH FPSCR CAUSE 17-12 inexact 0b000001
317 SH FPSCR ENABLED 11-7 invalid_operation 0b10000
318 SH FPSCR ENABLED 11-7 division_by_zero 0b01000
319 SH FPSCR ENABLED 11-7 overflow 0b00100
320 SH FPSCR ENABLED 11-7 underflow 0b00010
321 SH FPSCR ENABLED 11-7 inexact 0b00001
322 SH FPSCR FLAG 6-2 invalid_operation 0b10000
323 SH FPSCR FLAG 6-2 division_by_zero 0b01000
324 SH FPSCR FLAG 6-2 overflow 0b00100
325 SH FPSCR FLAG 6-2 underflow 0b00010
326 SH FPSCR FLAG 6-2 inexact 0b00001
327 SH FPSCR RM 1-0 round_to_nearest 0b00
328 SH FPSCR RM 1-0 round_to_zero 0b01
329
330 UBC BAMRA BAMA 3,1,0 all_bara_bits_are_included_in_break_conditions 0b0000
331 UBC BAMRA BAMA 3,1,0 lower_10_bits_of_bara_are_not_included_in_break_conditions 0b0001
332 UBC BAMRA BAMA 3,1,0 lower_12_bits_of_bara_are_not_included_in_break_conditions 0b0010
333 UBC BAMRA BAMA 3,1,0 all_bara_bits_are_not_included_in_break_conditions 0b0011
334 UBC BAMRA BAMA 3,1,0 lower_16_bits_of_bara_are_not_included_in_break_conditions 0b1000
335 UBC BAMRA BAMA 3,1,0 lower_20_bits_of_bara_are_not_included_in_break_conditions 0b1001
336 UBC BAMRA BASMA 2 all_basra_bits_are_included_in_break_conditions 0
337 UBC BAMRA BASMA 2 no_basra_bits_are_included_in_break_conditions 1
338
339 UBC BBRA SZA 6,1,0 operand_size_is_not_included_in_break_conditions 0b00
340 UBC BBRA SZA 6,1,0 byte_access_is_used_as_break_condition 0b01
341 UBC BBRA SZA 6,1,0 word_access_is_used_as_break_condition 0b10
342 UBC BBRA SZA 6,1,0 longword_access_is_used_as_break_condition 0b11
343 UBC BBRA SZA 6,1,0 quadword_access_is_used_as_break_condition 0b1000000
344 UBC BBRA IDA 5-4 condition_comparison_is_not_performed 0b00
345 UBC BBRA IDA 5-4 instruction_access_cycle_is_used_as_break_condition 0b01
346 UBC BBRA IDA 5-4 operand_access_cycle_is_used_as_break_condition 0b10
347 UBC BBRA IDA 5-4 instruction_access_cycle_or_operand_access_cycle_is_used_as_break_condition 0b11
348 UBC BBRA RWA 3-2 condition_comparison_is_not_performed 0b00
349 UBC BBRA RWA 3-2 read_cycle_is_used_as_break_condition 0b01
350 UBC BBRA RWA 3-2 write_cycle_is_used_as_break_condition 0b10
351 UBC BBRA RWA 3-2 read_cycle_or_write_cycle_is_used_as_break_condition 0b11
352
353 UBC BRCR CMFA 15 channel_a_break_condition_is_not_matched 0
354 UBC BRCR CMFA 15 channel_a_break_condition_match_has_occured 1
355 UBC BRCR CMFB 14 channel_b_break_condition_is_not_matched 0
356 UBC BRCR CMFB 14 channel_b_break_condition_match_has_occured 1
357 UBC BRCR PCBA 10 channel_a_pc_break_is_effected_before_instruction_execution 0
358 UBC BRCR PCBA 10 channel_a_pc_break_is_effected_after_instruction_execution 1
359 UBC BRCR DBEB 7 data_bus_condition_is_not_included_in_channel_b_conditions 0
360 UBC BRCR DBEB 7 data_bus_condition_is_included_in_channel_b_conditions 1
361 UBC BRCR PCBB 6 channel_b_pc_break_is_effected_before_instruction_execution 0
362 UBC BRCR PCBB 6 channel_b_pc_break_is_effected_after_instruction_execution 1
363 UBC BRCR SEQ 3 channel_a_and_b_comparison_are_performed_as_independent_condition 0
364 UBC BRCR SEQ 3 channel_a_and_b_comparison_are_performed_as_sequential_condition 1
365 UBC BRCR UBDE 0 user_break_debug_function_is_not_used 0
366 UBC BRCR UBDE 0 user_break_debug_function_is_used 1

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@ -72,7 +72,6 @@ static void poststart_read()
static void prestart_maple_raw__command()
{
uint32_t dest = reinterpret_cast<uint32_t>(&__send_buf);
//uint32_t dest = 0xac000020;
uint32_t size = state.buf.arg[0];
serial::recv_dma(dest - 1, size + 1);
state.reply_crc.value = 0xffffffff;
@ -82,7 +81,6 @@ static void prestart_maple_raw__command()
static void prestart_maple_raw__response()
{
uint32_t src = reinterpret_cast<uint32_t>(&__recv_buf);
//uint32_t src = 0xac002020;
uint32_t size = state.buf.arg[1];
serial::send_dma(src, size);
state.reply_crc.value = 0xffffffff;

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