89 lines
1.9 KiB
Verilog
89 lines
1.9 KiB
Verilog
`timescale 1ns / 1ps
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module vga_top
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(input wire clk,
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input wire rst,
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output wire led,
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output reg [3:0] red,
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output reg [3:0] green,
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output reg [3:0] blue,
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output wire h_sync,
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output wire v_sync
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);
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reg [26:0] counter;
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wire clk270, clk180, clk90, clk0, usr_ref_out;
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wire usr_pll_lock_stdy, usr_pll_lock;
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CC_PLL #(
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.REF_CLK(10.0), // reference input in MHz
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.OUT_CLK(25.175), // pll output frequency in MHz
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.PERF_MD("ECONOMY"), // LOWPOWER, ECONOMY, SPEED
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.LOW_JITTER(1), // 0: disable, 1: enable low jitter mode
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.CI_FILTER_CONST(2), // optional CI filter constant
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.CP_FILTER_CONST(4) // optional CP filter constant
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) pll_inst (
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.CLK_REF(clk), .CLK_FEEDBACK(1'b0), .USR_CLK_REF(1'b0),
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.USR_LOCKED_STDY_RST(1'b0), .USR_PLL_LOCKED_STDY(usr_pll_lock_stdy), .USR_PLL_LOCKED(usr_pll_lock),
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.CLK270(clk270), .CLK180(clk180), .CLK90(clk90), .CLK0(clk0), .CLK_REF_OUT(usr_ref_out)
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);
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assign led = counter[26];
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always @(posedge clk0)
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begin
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if (!rst) begin
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counter <= 0;
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end else begin
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counter <= counter + 1'b1;
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end
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end
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wire [9:0] h_count;
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wire [9:0] v_count;
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wire display;
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wire h_sync1;
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wire v_sync1;
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wire rst0 = 0;
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vga_spg spg(.clk(clk0),
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.rst(rst0),
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.h_count(h_count),
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.v_count(v_count),
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.h_sync(h_sync1),
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.v_sync(v_sync1),
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.display(display));
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reg h_sync2;
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reg v_sync2;
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assign h_sync = h_sync2;
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assign v_sync = v_sync2;
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always @(posedge clk0) begin
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h_sync2 <= h_sync1;
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v_sync2 <= v_sync1;
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if (display) begin
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if (v_count[3]) begin
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red <= 4'd15;
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green <= 4'd15;
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blue <= 4'd0;
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end else begin
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red <= 4'd15;
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green <= 4'd0;
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blue <= 4'd0;
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end
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end else begin
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red <= 4'd0;
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green <= 4'd0;
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blue <= 4'd0;
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end
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end
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endmodule
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