improve test bench

.gitignore

@@ -15,3 +15,6 @@
 *.sdf
 *.txt
 *.used
+*.vcd
+bin/*
+net/*

build.sh

@@ -2,6 +2,7 @@ set -eux
 
 yosys <<EOF
 read_verilog vga_spg.v
+read_verilog vga_fb.v
 read_verilog vga_top.v
 synth_gatemate -top vga_top -nomx8 -vlog net/synth.v
 EOF
@@ -10,4 +11,4 @@ PR=/home/bilbo/cc-toolchain-linux/bin/p_r/p_r
 
 $PR -i net/synth.v -o bin/vga -ccf vga.ccf -cCP
 
-openFPGALoader --cable dirtyJtag net/vga_00.cfg
+openFPGALoader --cable dirtyJtag bin/vga_00.cfg

test.sh

@@ -0,0 +1,4 @@
+set -eux
+
+iverilog -o bin/vga_tb vga_spg.v vga_fb.v vga_tb.v
+vvp bin/vga_tb

vga_fb.v

@@ -0,0 +1,51 @@
+module vga_fb
+  (input wire       clk,
+   input wire	    rst,
+   output reg [3:0] red,
+   output reg [3:0] green,
+   output reg [3:0] blue,
+   output reg	    h_sync,
+   output reg	    v_sync);
+
+
+   wire [9:0] h_count;
+   wire [9:0] v_count;
+   wire	      display;
+
+   wire	      h_sync1;
+   wire	      v_sync1;
+
+   vga_spg spg(.clk(clk),
+	       .rst(rst),
+	       .h_count(h_count),
+	       .v_count(v_count),
+	       .h_sync(h_sync1),
+	       .v_sync(v_sync1),
+	       .display(display));
+
+   always @(posedge clk) begin
+      h_sync <= h_sync1;
+      v_sync <= v_sync1;
+
+      if (display) begin
+	 if (h_count == 0 && v_count == 0) begin
+	    red <= 4'd15;
+	    green <= 4'd15;
+	    blue <= 4'd15;
+	 end else if (v_count[3]) begin
+	    red <= 4'd15;
+	    green <= 4'd15;
+	    blue <= 4'd0;
+         end else begin
+	    red <= 4'd15;
+	    green <= 4'd0;
+	    blue <= 4'd0;
+         end
+      end else begin
+	 red <= 4'd0;
+	 green <= 4'd0;
+	 blue <= 4'd0;
+      end
+   end
+
+endmodule

vga_tb.v

@@ -14,18 +14,18 @@ module vga_tb;
    reg clk = 0;
    always #1 clk = !clk;
 
-   wire	[9:0] h_count;
+   wire	[3:0] red;
-   wire	[9:0] v_count;
+   wire	[3:0] green;
+   wire [3:0] blue;
    wire	      h_sync;
    wire	      v_sync;
-   wire	      display;
 
-   vga_spg spg(clk,
+   vga_fb fb(clk,
-	       rst,
+	     rst,
-	       h_count,
+	     red,
-	       v_count,
+	     green,
-	       h_sync,
+	     blue,
-	       v_sync,
+	     h_sync,
-	       display);
+	     v_sync);
 
 endmodule

vga_top.v

@@ -19,7 +19,7 @@ module vga_top
    CC_PLL #(
 	    .REF_CLK(10.0),      // reference input in MHz
 	    .OUT_CLK(25.175),     // pll output frequency in MHz
-	    .PERF_MD("ECONOMY"), // LOWPOWER, ECONOMY, SPEED
+	    .PERF_MD("SPEED"), // LOWPOWER, ECONOMY, SPEED
 	    .LOW_JITTER(1),      // 0: disable, 1: enable low jitter mode
 	    .CI_FILTER_CONST(2), // optional CI filter constant
 	    .CP_FILTER_CONST(4)  // optional CP filter constant
@@ -40,49 +40,12 @@ module vga_top
 	end
      end
 
-   wire [9:0] h_count;
+   vga_fb fb(.clk(clk),
-   wire [9:0] v_count;
+	     .rst(rst),
-   wire	      display;
+	     .red(red),
-
+	     .green(green),
-   wire	      h_sync1;
+	     .blue(blue),
-   wire	      v_sync1;
+	     .h_sync(h_sync),
-
+	     .v_sync(v_sync));
-   wire       rst0 = 0;
-
-
-   vga_spg spg(.clk(clk0),
-	       .rst(rst0),
-	       .h_count(h_count),
-	       .v_count(v_count),
-	       .h_sync(h_sync1),
-	       .v_sync(v_sync1),
-	       .display(display));
-
-   reg        h_sync2;
-   reg        v_sync2;
-
-   assign h_sync = h_sync2;
-   assign v_sync = v_sync2;
-
-   always @(posedge clk0) begin
-      h_sync2 <= h_sync1;
-      v_sync2 <= v_sync1;
-
-      if (display) begin
-         if (v_count[3]) begin
-	    red <= 4'd15;
-	    green <= 4'd15;
-	    blue <= 4'd0;
-         end else begin
-	    red <= 4'd15;
-	    green <= 4'd0;
-	    blue <= 4'd0;
-         end
-      end else begin
-	 red <= 4'd0;
-	 green <= 4'd0;
-	 blue <= 4'd0;
-      end
-   end
 
 endmodule