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3209054b8f
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decode: implement PR- and SZ- instruction decode discrimination
Some SH4 floating point instructions have ambiguous encodings that
depend on the state of FPSCR bits. Exhaustively, these are:
FMOV XDm,DRn (sz 1)
FMOV FRm,FRn (sz 0)
FMOV DRm,@(R0,Rn) (sz 1)
FMOV.S FRm,@(R0,Rn) (sz 0)
FCMP/EQ DRm,DRn (pr 1)
FCMP/EQ FRm,FRn (pr 0)
FMOV @Rm+,XDn (sz 1)
FMOV.S @Rm+,FRn (sz 0)
FMOV XDm,@(R0,Rn) (sz 1)
FMOV.S FRm,@(R0,Rn) (sz 0)
FMUL DRm,DRn (pr 1)
FMUL FRm,FRn (pr 0)
FMOV.S @Rm+,FRn (sz 0)
FMOV @Rm+,DRn (sz 1)
FLOAT FPUL,DRn (pr 1)
FLOAT FPUL,FRn (pr 0)
FNEG DRn (pr 1)
FNEG FRn (pr 0)
FTRC DRm,FPUL (pr 1)
FTRC FRm,FPUL (pr 0)
FMOV.S @(R0,Rm),FRn (sz 0)
FMOV @(R0,Rm),DRn (sz 1)
FMOV.S @Rm,FRn (sz 0)
FMOV @Rm,DRn (sz 1)
FMOV XDm,XDn (sz 1)
FMOV FRm,FRn (sz 0)
FABS FRn (pr 0)
FABS DRn (pr 1)
FMOV.S FRm,@Rn (sz 0)
FMOV DRm,@Rn (sz 1)
FSUB DRm,DRn (pr 1)
FSUB FRm,FRn (pr 0)
FDIV DRm,DRn (pr 1)
FDIV FRm,FRn (pr 0)
FCMP/GT DRm,DRn (pr 1)
FCMP/GT FRm,FRn (pr 0)
FMOV DRm,DRn (sz 1)
FMOV FRm,FRn (sz 0)
FMOV.S FRm,@-Rn (sz 0)
FMOV DRm,@-Rn (sz 1)
FADD DRm,DRn (pr 1)
FADD FRm,FRn (pr 0)
FMOV.S FRm,@Rn (sz 0)
FMOV XDm,@Rn (sz 1)
FMOV.S @(R0,Rm),FRn (sz 0)
FMOV @(R0,Rm),XDn (sz 1)
FMOV DRm,XDn (sz 1)
FMOV FRm,FRn (sz 0)
FMOV XDm,@-Rn (sz 1)
FMOV.S FRm,@-Rn (sz 0)
FSQRT DRn (pr 1)
FSQRT FRn (pr 0)
FMOV.S @Rm,FRn (sz 0)
FMOV @Rm,XDn (sz 1)
This commit automatically calculates which FPU instructions require
FPSCR-discrimination, and automatically inserts the appropriate
conditional logic in the instruction decoder.
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2024-04-26 18:51:01 +08:00 |
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