From 65ee273b61d487e2f05c1f0f4f9fa38178792061 Mon Sep 17 00:00:00 2001 From: Zack Buhman Date: Thu, 18 Apr 2024 18:18:53 +0800 Subject: [PATCH] sh4: add descriptions for all instructions --- compare.py => python/compare.py | 0 decode.py => python/decode.py | 0 disassemble.py => python/disassemble.py | 0 .../effective_address.py | 0 elf.py => python/elf.py | 0 execute.py => python/execute.py | 0 generate.py => python/generate.py | 0 impl2.py => python/impl2.py | 0 .../instruction_properties.py | 0 .../instruction_table.py | 23 ++++++++++-- log.py => python/log.py | 0 mem.py => python/mem.py | 0 operations.py => python/operations.py | 0 sh2.py => python/sh2.py | 0 simulate.py => python/simulate.py | 0 test_impl.py => python/test_impl.py | 0 sh4.txt | 4 ++- sh4/ADD #imm,Rn | 5 +++ sh4/ADD Rm,Rn | 5 +++ sh4/ADDC Rm,Rn | 8 +++++ sh4/ADDV Rm,Rn | 7 ++++ sh4/AND #imm,R0 | 5 +++ sh4/AND Rm,Rn | 5 +++ sh4/AND.B #imm,@(R0,GBR) | 8 +++++ sh4/BF label | 16 +++++++++ sh4/BF_S label | 13 +++++++ sh4/BRA label | 8 +++++ sh4/BRAF Rn | 8 +++++ sh4/BRK | 2 ++ sh4/BSR label | 10 ++++++ sh4/BSRF Rn | 10 ++++++ sh4/BT label | 16 +++++++++ sh4/BT_S label | 13 +++++++ sh4/CLRMAC | 5 +++ sh4/CLRS | 3 ++ sh4/CLRT | 3 ++ sh4/CMP_EQ #imm,R0 | 5 +++ sh4/CMP_EQ Rm,Rn | 5 +++ sh4/CMP_GE Rm,Rn | 5 +++ sh4/CMP_GT Rm,Rn | 5 +++ sh4/CMP_HI Rm,Rn | 5 +++ sh4/CMP_HS Rm,Rn | 5 +++ sh4/CMP_PL Rn | 4 +++ sh4/CMP_PZ Rn | 4 +++ sh4/CMP_STR Rm,Rn | 9 +++++ sh4/DIV0S Rm,Rn | 9 +++++ sh4/DIV0U | 7 ++++ sh4/DIV1 Rm,Rn | 18 ++++++++++ sh4/DMULS.L Rm,Rn | 8 +++++ sh4/DMULU.L Rm,Rn | 8 +++++ sh4/DT Rn | 6 ++++ sh4/EXTS.B Rm,Rn | 4 +++ sh4/EXTS.W Rm,Rn | 4 +++ sh4/EXTU.B Rm,Rn | 4 +++ sh4/EXTU.W Rm,Rn | 4 +++ sh4/FABS DRn | 10 ++++++ sh4/FABS FRn | 10 ++++++ sh4/FADD DRm,DRn | 19 ++++++++++ sh4/FADD FRm,FRn | 19 ++++++++++ sh4/FCMP_EQ DRm,DRn | 15 ++++++++ sh4/FCMP_EQ FRm,FRn | 15 ++++++++ sh4/FCMP_GT DRm,DRn | 15 ++++++++ sh4/FCMP_GT FRm,FRn | 15 ++++++++ sh4/FCNVDS DRm,FPUL | 18 ++++++++++ sh4/FCNVSD FPUL,DRn | 16 +++++++++ sh4/FCSA FPUL,DRn | 1 + sh4/FDIV DRm,DRn | 21 +++++++++++ sh4/FDIV FRm,FRn | 21 +++++++++++ sh4/FIPR FVm,FVn | 17 +++++++++ sh4/FLDI0 FRn | 9 +++++ sh4/FLDI1 FRn | 9 +++++ sh4/FLDS FRm,FPUL | 9 +++++ sh4/FLOAT FPUL,DRn | 11 ++++++ sh4/FLOAT FPUL,FRn | 14 ++++++++ sh4/FMAC FR0,FRm,FRn | 20 +++++++++++ sh4/FMOV @(R0,Rm),DRn | 12 +++++++ sh4/FMOV @(R0,Rm),XDn | 12 +++++++ sh4/FMOV @Rm+,DRn | 14 ++++++++ sh4/FMOV @Rm+,XDn | 14 ++++++++ sh4/FMOV @Rm,DRn | 11 ++++++ sh4/FMOV @Rm,XDn | 12 +++++++ sh4/FMOV DRm,@(R0,Rn) | 12 +++++++ sh4/FMOV DRm,@-Rn | 14 ++++++++ sh4/FMOV DRm,@Rn | 12 +++++++ sh4/FMOV DRm,DRn | 10 ++++++ sh4/FMOV DRm,XDn | 10 ++++++ sh4/FMOV FRm,FRn | 11 ++++++ sh4/FMOV XDm,@(R0,Rn) | 12 +++++++ sh4/FMOV XDm,@-Rn | 15 ++++++++ sh4/FMOV XDm,@Rn | 12 +++++++ sh4/FMOV XDm,DRn | 11 ++++++ sh4/FMOV XDm,XDn | 11 ++++++ sh4/FMOV.S @(R0,Rm),FRn | 12 +++++++ sh4/FMOV.S @Rm+,FRn | 13 +++++++ sh4/FMOV.S @Rm,FRn | 12 +++++++ sh4/FMOV.S FRm,@(R0,Rn) | 12 +++++++ sh4/FMOV.S FRm,@-Rn | 14 ++++++++ sh4/FMOV.S FRm,@Rn | 12 +++++++ sh4/FMUL DRm,DRn | 19 ++++++++++ sh4/FMUL FRm,FRn | 19 ++++++++++ sh4/FNEG DRn | 10 ++++++ sh4/FNEG FRn | 11 ++++++ sh4/FRCHG | 10 ++++++ sh4/FSCHG | 10 ++++++ sh4/FSQRT DRn | 18 ++++++++++ sh4/FSQRT FRn | 18 ++++++++++ sh4/FSRRA FRn | 1 + sh4/FSTS FPUL,FRn | 9 +++++ sh4/FSUB DRm,DRn | 19 ++++++++++ sh4/FSUB FRm,FRn | 19 ++++++++++ sh4/FTRC DRm,FPUL | 14 ++++++++ sh4/FTRC FRm,FPUL | 14 ++++++++ sh4/FTRV XMTRX,FVn | 15 ++++++++ sh4/JMP @Rn | 7 ++++ sh4/JSR @Rn | 10 ++++++ sh4/LDC Rm,DBR | 7 ++++ sh4/LDC Rm,GBR | 4 +++ sh4/LDC Rm,Rn_BANK | 7 ++++ sh4/LDC Rm,SPC | 7 ++++ sh4/LDC Rm,SR | 7 ++++ sh4/LDC Rm,SSR | 7 ++++ sh4/LDC Rm,VBR | 7 ++++ sh4/LDC.L @Rm+,DBR | 10 ++++++ sh4/LDC.L @Rm+,GBR | 7 ++++ sh4/LDC.L @Rm+,Rn_BANK | 10 ++++++ sh4/LDC.L @Rm+,SPC | 10 ++++++ sh4/LDC.L @Rm+,SR | 10 ++++++ sh4/LDC.L @Rm+,SSR | 10 ++++++ sh4/LDC.L @Rm+,VBR | 10 ++++++ sh4/LDS Rm,FPSCR | 12 +++++++ sh4/LDS Rm,FPUL | 9 +++++ sh4/LDS Rm,MACH | 4 +++ sh4/LDS Rm,MACL | 4 +++ sh4/LDS Rm,PR | 6 ++++ sh4/LDS.L @Rm+,FPSCR | 16 +++++++++ sh4/LDS.L @Rm+,FPUL | 12 +++++++ sh4/LDS.L @Rm+,MACH | 7 ++++ sh4/LDS.L @Rm+,MACL | 7 ++++ sh4/LDS.L @Rm+,PR | 9 +++++ sh4/LDTLB | 14 ++++++++ sh4/MAC.L @Rm+,@Rn+ | 33 +++++++++++++++++ sh4/MAC.W @Rm+,@Rn+ | 35 +++++++++++++++++++ sh4/MOV #imm,Rn | 4 +++ sh4/MOV Rm,Rn | 4 +++ sh4/MOV.B @(R0,Rm),Rn | 6 ++++ sh4/MOV.B @(disp,GBR),R0 | 6 ++++ sh4/MOV.B @(disp,Rm),R0 | 6 ++++ sh4/MOV.B @Rm+,Rn | 12 +++++++ sh4/MOV.B @Rm,Rn | 5 +++ sh4/MOV.B R0,@(disp,GBR) | 6 ++++ sh4/MOV.B R0,@(disp,Rn) | 6 ++++ sh4/MOV.B Rm,@(R0,Rn) | 6 ++++ sh4/MOV.B Rm,@-Rn | 7 ++++ sh4/MOV.B Rm,@Rn | 5 +++ sh4/MOV.L @(R0,Rm),Rn | 6 ++++ sh4/MOV.L @(disp,GBR),R0 | 6 ++++ sh4/MOV.L @(disp,PC),Rn | 8 +++++ sh4/MOV.L @(disp,Rm),Rn | 6 ++++ sh4/MOV.L @Rm+,Rn | 12 +++++++ sh4/MOV.L @Rm,Rn | 5 +++ sh4/MOV.L R0,@(disp,GBR) | 6 ++++ sh4/MOV.L Rm,@(R0,Rn) | 6 ++++ sh4/MOV.L Rm,@(disp,Rn) | 6 ++++ sh4/MOV.L Rm,@-Rn | 7 ++++ sh4/MOV.L Rm,@Rn | 5 +++ sh4/MOV.W @(R0,Rm),Rn | 6 ++++ sh4/MOV.W @(disp,GBR),R0 | 6 ++++ sh4/MOV.W @(disp,PC),Rn | 8 +++++ sh4/MOV.W @(disp,Rm),R0 | 6 ++++ sh4/MOV.W @Rm+,Rn | 12 +++++++ sh4/MOV.W @Rm,Rn | 5 +++ sh4/MOV.W R0,@(disp,GBR) | 6 ++++ sh4/MOV.W R0,@(disp,Rn) | 6 ++++ sh4/MOV.W Rm,@(R0,Rn) | 6 ++++ sh4/MOV.W Rm,@-Rn | 7 ++++ sh4/MOV.W Rm,@Rn | 5 +++ sh4/MOVA @(disp,PC),R0 | 7 ++++ sh4/MOVCA.L R0,@Rn | 14 ++++++++ sh4/MOVT Rn | 4 +++ sh4/MUL.L Rm,Rn | 5 +++ sh4/MULS.W Rm,Rn | 5 +++ sh4/MULU.W Rm,Rn | 5 +++ sh4/NEG Rm,Rn | 4 +++ sh4/NEGC Rm,Rn | 7 ++++ sh4/NOP | 2 ++ sh4/NOT Rm,Rn | 4 +++ sh4/OCBI @Rn | 11 ++++++ sh4/OCBP @Rn | 9 +++++ sh4/OCBWB @Rn | 9 +++++ sh4/OR #imm,R0 | 5 +++ sh4/OR Rm,Rn | 5 +++ sh4/OR.B #imm,@(R0,GBR) | 8 +++++ sh4/PREF @Rn | 7 ++++ sh4/ROTCL Rn | 7 ++++ sh4/ROTCR Rn | 8 +++++ sh4/ROTL Rn | 6 ++++ sh4/ROTR Rn | 6 ++++ sh4/RTE | 11 ++++++ sh4/RTS | 7 ++++ sh4/SETS | 3 ++ sh4/SETT | 3 ++ sh4/SHAD Rm,Rn | 13 +++++++ sh4/SHAL Rn | 6 ++++ sh4/SHAR Rn | 6 ++++ sh4/SHLD Rm,Rn | 11 ++++++ sh4/SHLL Rn | 6 ++++ sh4/SHLL16 Rn | 4 +++ sh4/SHLL2 Rn | 4 +++ sh4/SHLL8 Rn | 4 +++ sh4/SHLR Rn | 6 ++++ sh4/SHLR16 Rn | 4 +++ sh4/SHLR2 Rn | 4 +++ sh4/SHLR8 Rn | 4 +++ sh4/SLEEP | 5 +++ sh4/STC DBR,Rn | 7 ++++ sh4/STC GBR,Rn | 4 +++ sh4/STC Rm_BANK,Rn | 7 ++++ sh4/STC SGR,Rn | 7 ++++ sh4/STC SPC,Rn | 7 ++++ sh4/STC SR,Rn | 7 ++++ sh4/STC SSR,Rn | 7 ++++ sh4/STC VBR,Rn | 7 ++++ sh4/STC.L DBR,@-Rn | 10 ++++++ sh4/STC.L GBR,@-Rn | 7 ++++ sh4/STC.L Rm_BANK,@-Rn | 10 ++++++ sh4/STC.L SGR,@-Rn | 10 ++++++ sh4/STC.L SPC,@-Rn | 10 ++++++ sh4/STC.L SR,@-Rn | 10 ++++++ sh4/STC.L SSR,@-Rn | 10 ++++++ sh4/STC.L VBR,@-Rn | 10 ++++++ sh4/STS FPSCR,Rn | 9 +++++ sh4/STS FPUL,Rn | 9 +++++ sh4/STS MACH,Rn | 4 +++ sh4/STS MACL,Rn | 4 +++ sh4/STS PR,Rn | 4 +++ sh4/STS.L FPSCR,@-Rn | 13 +++++++ sh4/STS.L FPUL,@-Rn | 12 +++++++ sh4/STS.L MACH,@-Rn | 7 ++++ sh4/STS.L MACL,@-Rn | 7 ++++ sh4/STS.L PR,@-Rn | 7 ++++ sh4/SUB Rm,Rn | 5 +++ sh4/SUBC Rm,Rn | 8 +++++ sh4/SUBV Rm,Rn | 7 ++++ sh4/SWAP.B Rm,Rn | 4 +++ sh4/SWAP.W Rm,Rn | 4 +++ sh4/TAS.B @Rn | 9 +++++ sh4/TRAPA #imm | 5 +++ sh4/TST #imm,R0 | 5 +++ sh4/TST Rm,Rn | 5 +++ sh4/TST.B #imm,@(R0,GBR) | 8 +++++ sh4/XOR #imm,R0 | 5 +++ sh4/XOR Rm,Rn | 5 +++ sh4/XOR.B #imm,@(R0,GBR) | 8 +++++ sh4/XTRCT Rm,Rn | 5 +++ 254 files changed, 2108 insertions(+), 3 deletions(-) rename compare.py => python/compare.py (100%) rename decode.py => python/decode.py (100%) rename disassemble.py => python/disassemble.py (100%) rename effective_address.py => python/effective_address.py (100%) rename elf.py => python/elf.py (100%) rename execute.py => python/execute.py (100%) rename generate.py => python/generate.py (100%) rename impl2.py => python/impl2.py (100%) rename instruction_properties.py => python/instruction_properties.py (100%) rename instruction_table.py => python/instruction_table.py (89%) rename log.py => python/log.py (100%) rename mem.py => python/mem.py (100%) rename operations.py => python/operations.py (100%) rename sh2.py => python/sh2.py (100%) rename simulate.py => python/simulate.py (100%) rename test_impl.py => python/test_impl.py (100%) create mode 100644 sh4/ADD #imm,Rn create mode 100644 sh4/ADD Rm,Rn create mode 100644 sh4/ADDC Rm,Rn create mode 100644 sh4/ADDV Rm,Rn create mode 100644 sh4/AND #imm,R0 create mode 100644 sh4/AND Rm,Rn create mode 100644 sh4/AND.B #imm,@(R0,GBR) create mode 100644 sh4/BF label create mode 100644 sh4/BF_S label create mode 100644 sh4/BRA label create mode 100644 sh4/BRAF Rn create mode 100644 sh4/BRK create mode 100644 sh4/BSR label create mode 100644 sh4/BSRF Rn create mode 100644 sh4/BT label create mode 100644 sh4/BT_S label create mode 100644 sh4/CLRMAC create mode 100644 sh4/CLRS create mode 100644 sh4/CLRT create mode 100644 sh4/CMP_EQ #imm,R0 create mode 100644 sh4/CMP_EQ Rm,Rn create mode 100644 sh4/CMP_GE Rm,Rn create mode 100644 sh4/CMP_GT Rm,Rn create mode 100644 sh4/CMP_HI Rm,Rn create mode 100644 sh4/CMP_HS Rm,Rn create mode 100644 sh4/CMP_PL Rn create mode 100644 sh4/CMP_PZ Rn create mode 100644 sh4/CMP_STR Rm,Rn create mode 100644 sh4/DIV0S Rm,Rn create mode 100644 sh4/DIV0U create mode 100644 sh4/DIV1 Rm,Rn create mode 100644 sh4/DMULS.L Rm,Rn create mode 100644 sh4/DMULU.L Rm,Rn create mode 100644 sh4/DT Rn create mode 100644 sh4/EXTS.B Rm,Rn create mode 100644 sh4/EXTS.W Rm,Rn create mode 100644 sh4/EXTU.B Rm,Rn create mode 100644 sh4/EXTU.W Rm,Rn create mode 100644 sh4/FABS DRn create mode 100644 sh4/FABS FRn create mode 100644 sh4/FADD DRm,DRn create mode 100644 sh4/FADD FRm,FRn create mode 100644 sh4/FCMP_EQ DRm,DRn create mode 100644 sh4/FCMP_EQ FRm,FRn create mode 100644 sh4/FCMP_GT DRm,DRn create mode 100644 sh4/FCMP_GT FRm,FRn create mode 100644 sh4/FCNVDS DRm,FPUL create mode 100644 sh4/FCNVSD FPUL,DRn create mode 100644 sh4/FCSA FPUL,DRn create mode 100644 sh4/FDIV DRm,DRn create mode 100644 sh4/FDIV FRm,FRn create mode 100644 sh4/FIPR FVm,FVn create mode 100644 sh4/FLDI0 FRn create mode 100644 sh4/FLDI1 FRn create mode 100644 sh4/FLDS FRm,FPUL create mode 100644 sh4/FLOAT FPUL,DRn create mode 100644 sh4/FLOAT FPUL,FRn create mode 100644 sh4/FMAC FR0,FRm,FRn create mode 100644 sh4/FMOV @(R0,Rm),DRn create mode 100644 sh4/FMOV @(R0,Rm),XDn create mode 100644 sh4/FMOV @Rm+,DRn create mode 100644 sh4/FMOV @Rm+,XDn create mode 100644 sh4/FMOV @Rm,DRn create mode 100644 sh4/FMOV @Rm,XDn create mode 100644 sh4/FMOV DRm,@(R0,Rn) create mode 100644 sh4/FMOV DRm,@-Rn create mode 100644 sh4/FMOV DRm,@Rn create mode 100644 sh4/FMOV DRm,DRn create mode 100644 sh4/FMOV DRm,XDn create mode 100644 sh4/FMOV FRm,FRn create mode 100644 sh4/FMOV XDm,@(R0,Rn) create mode 100644 sh4/FMOV XDm,@-Rn create mode 100644 sh4/FMOV XDm,@Rn create mode 100644 sh4/FMOV XDm,DRn create mode 100644 sh4/FMOV XDm,XDn create mode 100644 sh4/FMOV.S @(R0,Rm),FRn create mode 100644 sh4/FMOV.S @Rm+,FRn create mode 100644 sh4/FMOV.S @Rm,FRn create mode 100644 sh4/FMOV.S FRm,@(R0,Rn) create mode 100644 sh4/FMOV.S FRm,@-Rn create mode 100644 sh4/FMOV.S FRm,@Rn create mode 100644 sh4/FMUL DRm,DRn create mode 100644 sh4/FMUL FRm,FRn create mode 100644 sh4/FNEG DRn create mode 100644 sh4/FNEG FRn create mode 100644 sh4/FRCHG create mode 100644 sh4/FSCHG create mode 100644 sh4/FSQRT DRn create mode 100644 sh4/FSQRT FRn create mode 100644 sh4/FSRRA FRn create mode 100644 sh4/FSTS FPUL,FRn create mode 100644 sh4/FSUB DRm,DRn create mode 100644 sh4/FSUB FRm,FRn create mode 100644 sh4/FTRC DRm,FPUL create mode 100644 sh4/FTRC FRm,FPUL create mode 100644 sh4/FTRV XMTRX,FVn create mode 100644 sh4/JMP @Rn create mode 100644 sh4/JSR @Rn create mode 100644 sh4/LDC Rm,DBR create mode 100644 sh4/LDC Rm,GBR create mode 100644 sh4/LDC Rm,Rn_BANK create mode 100644 sh4/LDC Rm,SPC create mode 100644 sh4/LDC Rm,SR create mode 100644 sh4/LDC Rm,SSR create mode 100644 sh4/LDC Rm,VBR create mode 100644 sh4/LDC.L @Rm+,DBR create mode 100644 sh4/LDC.L @Rm+,GBR create mode 100644 sh4/LDC.L @Rm+,Rn_BANK create mode 100644 sh4/LDC.L @Rm+,SPC create mode 100644 sh4/LDC.L @Rm+,SR create mode 100644 sh4/LDC.L @Rm+,SSR create mode 100644 sh4/LDC.L @Rm+,VBR create mode 100644 sh4/LDS Rm,FPSCR create mode 100644 sh4/LDS Rm,FPUL create mode 100644 sh4/LDS Rm,MACH create mode 100644 sh4/LDS Rm,MACL create mode 100644 sh4/LDS Rm,PR create mode 100644 sh4/LDS.L @Rm+,FPSCR create mode 100644 sh4/LDS.L @Rm+,FPUL create mode 100644 sh4/LDS.L @Rm+,MACH create mode 100644 sh4/LDS.L @Rm+,MACL create mode 100644 sh4/LDS.L @Rm+,PR create mode 100644 sh4/LDTLB create mode 100644 sh4/MAC.L @Rm+,@Rn+ create mode 100644 sh4/MAC.W @Rm+,@Rn+ create mode 100644 sh4/MOV #imm,Rn create mode 100644 sh4/MOV Rm,Rn create mode 100644 sh4/MOV.B @(R0,Rm),Rn create mode 100644 sh4/MOV.B @(disp,GBR),R0 create mode 100644 sh4/MOV.B @(disp,Rm),R0 create mode 100644 sh4/MOV.B @Rm+,Rn create mode 100644 sh4/MOV.B @Rm,Rn create mode 100644 sh4/MOV.B R0,@(disp,GBR) create mode 100644 sh4/MOV.B R0,@(disp,Rn) create mode 100644 sh4/MOV.B Rm,@(R0,Rn) create mode 100644 sh4/MOV.B Rm,@-Rn create mode 100644 sh4/MOV.B Rm,@Rn create mode 100644 sh4/MOV.L @(R0,Rm),Rn create mode 100644 sh4/MOV.L @(disp,GBR),R0 create mode 100644 sh4/MOV.L @(disp,PC),Rn create mode 100644 sh4/MOV.L @(disp,Rm),Rn create mode 100644 sh4/MOV.L @Rm+,Rn create mode 100644 sh4/MOV.L @Rm,Rn create mode 100644 sh4/MOV.L R0,@(disp,GBR) create mode 100644 sh4/MOV.L Rm,@(R0,Rn) create mode 100644 sh4/MOV.L Rm,@(disp,Rn) create mode 100644 sh4/MOV.L Rm,@-Rn create mode 100644 sh4/MOV.L Rm,@Rn create mode 100644 sh4/MOV.W @(R0,Rm),Rn create mode 100644 sh4/MOV.W @(disp,GBR),R0 create mode 100644 sh4/MOV.W @(disp,PC),Rn create mode 100644 sh4/MOV.W @(disp,Rm),R0 create mode 100644 sh4/MOV.W @Rm+,Rn create mode 100644 sh4/MOV.W @Rm,Rn create mode 100644 sh4/MOV.W R0,@(disp,GBR) create mode 100644 sh4/MOV.W R0,@(disp,Rn) create mode 100644 sh4/MOV.W Rm,@(R0,Rn) create mode 100644 sh4/MOV.W Rm,@-Rn create mode 100644 sh4/MOV.W Rm,@Rn create mode 100644 sh4/MOVA @(disp,PC),R0 create mode 100644 sh4/MOVCA.L R0,@Rn create mode 100644 sh4/MOVT Rn create mode 100644 sh4/MUL.L Rm,Rn create mode 100644 sh4/MULS.W Rm,Rn create mode 100644 sh4/MULU.W Rm,Rn create mode 100644 sh4/NEG Rm,Rn create mode 100644 sh4/NEGC Rm,Rn create mode 100644 sh4/NOP create mode 100644 sh4/NOT Rm,Rn create mode 100644 sh4/OCBI @Rn create mode 100644 sh4/OCBP @Rn create mode 100644 sh4/OCBWB @Rn create mode 100644 sh4/OR #imm,R0 create mode 100644 sh4/OR Rm,Rn create mode 100644 sh4/OR.B #imm,@(R0,GBR) create mode 100644 sh4/PREF @Rn create mode 100644 sh4/ROTCL Rn create mode 100644 sh4/ROTCR Rn create mode 100644 sh4/ROTL Rn create mode 100644 sh4/ROTR Rn create mode 100644 sh4/RTE create mode 100644 sh4/RTS create mode 100644 sh4/SETS create mode 100644 sh4/SETT create mode 100644 sh4/SHAD Rm,Rn create mode 100644 sh4/SHAL Rn create mode 100644 sh4/SHAR Rn create mode 100644 sh4/SHLD Rm,Rn create mode 100644 sh4/SHLL Rn create mode 100644 sh4/SHLL16 Rn create mode 100644 sh4/SHLL2 Rn create mode 100644 sh4/SHLL8 Rn create mode 100644 sh4/SHLR Rn create mode 100644 sh4/SHLR16 Rn create mode 100644 sh4/SHLR2 Rn create mode 100644 sh4/SHLR8 Rn create mode 100644 sh4/SLEEP create mode 100644 sh4/STC DBR,Rn create mode 100644 sh4/STC GBR,Rn create mode 100644 sh4/STC Rm_BANK,Rn create mode 100644 sh4/STC SGR,Rn create mode 100644 sh4/STC SPC,Rn create mode 100644 sh4/STC SR,Rn create mode 100644 sh4/STC SSR,Rn create mode 100644 sh4/STC VBR,Rn create mode 100644 sh4/STC.L DBR,@-Rn create mode 100644 sh4/STC.L GBR,@-Rn create mode 100644 sh4/STC.L Rm_BANK,@-Rn create mode 100644 sh4/STC.L SGR,@-Rn create mode 100644 sh4/STC.L SPC,@-Rn create mode 100644 sh4/STC.L SR,@-Rn create mode 100644 sh4/STC.L SSR,@-Rn create mode 100644 sh4/STC.L VBR,@-Rn create mode 100644 sh4/STS FPSCR,Rn create mode 100644 sh4/STS FPUL,Rn create mode 100644 sh4/STS MACH,Rn create mode 100644 sh4/STS MACL,Rn create mode 100644 sh4/STS PR,Rn create mode 100644 sh4/STS.L FPSCR,@-Rn create mode 100644 sh4/STS.L FPUL,@-Rn create mode 100644 sh4/STS.L MACH,@-Rn create mode 100644 sh4/STS.L MACL,@-Rn create mode 100644 sh4/STS.L PR,@-Rn create mode 100644 sh4/SUB Rm,Rn create mode 100644 sh4/SUBC Rm,Rn create mode 100644 sh4/SUBV Rm,Rn create mode 100644 sh4/SWAP.B Rm,Rn create mode 100644 sh4/SWAP.W Rm,Rn create mode 100644 sh4/TAS.B @Rn create mode 100644 sh4/TRAPA #imm create mode 100644 sh4/TST #imm,R0 create mode 100644 sh4/TST Rm,Rn create mode 100644 sh4/TST.B #imm,@(R0,GBR) create mode 100644 sh4/XOR #imm,R0 create mode 100644 sh4/XOR Rm,Rn create mode 100644 sh4/XOR.B #imm,@(R0,GBR) create mode 100644 sh4/XTRCT Rm,Rn diff --git a/compare.py b/python/compare.py similarity index 100% rename from compare.py rename to python/compare.py diff --git a/decode.py b/python/decode.py similarity index 100% rename from decode.py rename to python/decode.py diff --git a/disassemble.py b/python/disassemble.py similarity index 100% rename from disassemble.py rename to python/disassemble.py diff --git a/effective_address.py b/python/effective_address.py similarity index 100% rename from effective_address.py rename to python/effective_address.py diff --git a/elf.py b/python/elf.py similarity index 100% rename from elf.py rename to python/elf.py diff --git a/execute.py b/python/execute.py similarity index 100% rename from execute.py rename to python/execute.py diff --git a/generate.py b/python/generate.py similarity index 100% rename from generate.py rename to python/generate.py diff --git a/impl2.py b/python/impl2.py similarity index 100% rename from impl2.py rename to python/impl2.py diff --git a/instruction_properties.py b/python/instruction_properties.py similarity index 100% rename from instruction_properties.py rename to python/instruction_properties.py diff --git a/instruction_table.py b/python/instruction_table.py similarity index 89% rename from instruction_table.py rename to python/instruction_table.py index 37f8fd4..3a576d2 100644 --- a/instruction_table.py +++ b/python/instruction_table.py @@ -158,10 +158,13 @@ def parse_variables(operands): for token in parse_tokens(operands): yield from get_variable(token) - def parse_instruction(*, instruction, operands, code, operation, **kwargs): code = parse_code(code) - variables = tuple(parse_variables(operands)) + try: + variables = tuple(parse_variables(operands)) + except: + print(instruction) + raise return ( instruction, @@ -233,3 +236,19 @@ def untabulate_instructions_sh4(): ])) return untabulate_instructions(os.path.join(directory, "sh4.txt"), columns) + +l = untabulate_instructions_sh4() +from pprint import pprint +for ins in list(l): + if ins.operands: + fn = ' '.join([ins.instruction, ins.operands]) + else: + fn = ins.instruction + fn = fn.replace('/', '_') + code = list(f'{ins.code.code_bits:016b}') + for operand in ins.code.operands.values(): + for i in range(operand.lsb, operand.lsb + operand.length): + code[15 - i] = operand.operand + + with open(os.path.join(directory, "sh4", fn), 'w') as f: + f.write(''.join(code) + '\n') diff --git a/log.py b/python/log.py similarity index 100% rename from log.py rename to python/log.py diff --git a/mem.py b/python/mem.py similarity index 100% rename from mem.py rename to python/mem.py diff --git a/operations.py b/python/operations.py similarity index 100% rename from operations.py rename to python/operations.py diff --git a/sh2.py b/python/sh2.py similarity index 100% rename from sh2.py rename to python/sh2.py diff --git a/simulate.py b/python/simulate.py similarity index 100% rename from simulate.py rename to python/simulate.py diff --git a/test_impl.py b/python/test_impl.py similarity index 100% rename from test_impl.py rename to python/test_impl.py diff --git a/sh4.txt b/sh4.txt index a9981d0..1907099 100644 --- a/sh4.txt +++ b/sh4.txt @@ -250,5 +250,7 @@ FTRV XMTRX,FVn transform_vector [XMTRX, FVn] → FVn FRCHG ~FPSCR.FR → SPFCR.FR 1111101111111101 — — FSCHG ~FPSCR.SZ → SPFCR.SZ 1111001111111101 — — -FCSA FPUL, DRn sin(FPUL) → FRn ; cos(FPUL) → FR[n+1] 1111nnn011111101 — — +FCSA FPUL,DRn sin(FPUL) → FRn ; cos(FPUL) → FR[n+1] 1111nnn011111101 — — FSRRA FRn 1/√FRn → FRn 1111nnnn01111101 — — + +BRK BREAK 0000000000111011 — — diff --git a/sh4/ADD #imm,Rn b/sh4/ADD #imm,Rn new file mode 100644 index 0000000..f4a2446 --- /dev/null +++ b/sh4/ADD #imm,Rn @@ -0,0 +1,5 @@ +0111nnnniiiiiiii +imm ← SignExtend8(s); +op2 ← SignExtend32(Rn); +op2 ← op2 + imm; +Rn ← Register(op2); \ No newline at end of file diff --git a/sh4/ADD Rm,Rn b/sh4/ADD Rm,Rn new file mode 100644 index 0000000..9d4bc29 --- /dev/null +++ b/sh4/ADD Rm,Rn @@ -0,0 +1,5 @@ +0011nnnnmmmm1100 +op1 ← SignExtend32(Rm); +op2 ← SignExtend32(Rn); +op2 ← op2 + op1; +Rn ← Register(op2); diff --git a/sh4/ADDC Rm,Rn b/sh4/ADDC Rm,Rn new file mode 100644 index 0000000..b526b5e --- /dev/null +++ b/sh4/ADDC Rm,Rn @@ -0,0 +1,8 @@ +0011nnnnmmmm1110 +t ← ZeroExtend1(T); +op1 ← ZeroExtend32(SignExtend32(Rm)); +op2 ← ZeroExtend32(SignExtend32(Rn)); +op2 ← (op2 + op1) + t; +t ← op2< 32 FOR 1 >; +Rn ← Register(op2); +T ← Bit(t); diff --git a/sh4/ADDV Rm,Rn b/sh4/ADDV Rm,Rn new file mode 100644 index 0000000..006385b --- /dev/null +++ b/sh4/ADDV Rm,Rn @@ -0,0 +1,7 @@ +0011nnnnmmmm1111 +op1 ← SignExtend32(Rm); +op2 ← SignExtend32(Rn); +op2 ← op2 + op1; +t ← INT ((op2 < (- 231)) OR (op2 ≥ 231)); +Rn ← Register(op2); +T ← Bit(t); diff --git a/sh4/AND #imm,R0 b/sh4/AND #imm,R0 new file mode 100644 index 0000000..7c50781 --- /dev/null +++ b/sh4/AND #imm,R0 @@ -0,0 +1,5 @@ +11001001iiiiiiii +r0 ← ZeroExtend32(R0); +imm ← ZeroExtend8(i); +r0 ← r0 ∧ imm; +R0 ← Register(r0); diff --git a/sh4/AND Rm,Rn b/sh4/AND Rm,Rn new file mode 100644 index 0000000..d3c0aa0 --- /dev/null +++ b/sh4/AND Rm,Rn @@ -0,0 +1,5 @@ +0010nnnnmmmm1001 +op1 ← ZeroExtend32(Rm); +op2 ← ZeroExtend32(Rn); +op2 ← op2 ∧ op1; +Rn ← Register(op2); diff --git a/sh4/AND.B #imm,@(R0,GBR) b/sh4/AND.B #imm,@(R0,GBR) new file mode 100644 index 0000000..4c47566 --- /dev/null +++ b/sh4/AND.B #imm,@(R0,GBR) @@ -0,0 +1,8 @@ +11001101iiiiiiii +r0 ← SignExtend32(R0); +gbr ← SignExtend32(GBR); +imm ← ZeroExtend8(i); +address ← ZeroExtend32(r0 + gbr); +value ← ZeroExtend8(ReadMemory8(address)); +value ← value ∧ imm; +WriteMemory8(address, value); diff --git a/sh4/BF label b/sh4/BF label new file mode 100644 index 0000000..a1a3757 --- /dev/null +++ b/sh4/BF label @@ -0,0 +1,16 @@ +10001011dddddddd +t ← ZeroExtend1(T); +pc ← SignExtend32(PC); +newpc ← SignExtend32(PC’); +delayedpc ← SignExtend32(PC’’); +label ← SignExtend8(s) << 1; +IF (IsDelaySlot()) +THROW ILLSLOT; +IF (t = 0) +{ +temp ← ZeroExtend32(pc + 4 + label); +newpc ← temp; +delayedpc ← temp + 2; +} +PC’ ← Register(newpc); +PC’’ ← Register(delayedpc); diff --git a/sh4/BF_S label b/sh4/BF_S label new file mode 100644 index 0000000..f064aff --- /dev/null +++ b/sh4/BF_S label @@ -0,0 +1,13 @@ +10001111dddddddd +t ← ZeroExtend1(T); +pc ← SignExtend32(PC); +delayedpc ← SignExtend32(PC’’); +label ← SignExtend8(s) << 1; +IF (IsDelaySlot()) +THROW ILLSLOT; +IF (t = 0) +{ +temp ← ZeroExtend32(pc + 4 + label); +delayedpc ← temp; +} +PC’’ ← Register(delayedpc); diff --git a/sh4/BRA label b/sh4/BRA label new file mode 100644 index 0000000..c66a5d8 --- /dev/null +++ b/sh4/BRA label @@ -0,0 +1,8 @@ +1010dddddddddddd +pc ← SignExtend32(PC); +label ← SignExtend12(s) << 1; +IF (IsDelaySlot()) +THROW ILLSLOT; +temp ← ZeroExtend32(pc + 4 + label); +delayedpc ← temp; +PC’’ ← Register(delayedpc); diff --git a/sh4/BRAF Rn b/sh4/BRAF Rn new file mode 100644 index 0000000..53ad51c --- /dev/null +++ b/sh4/BRAF Rn @@ -0,0 +1,8 @@ +0000nnnn00100011 +pc ← SignExtend32(PC); +op1 ← SignExtend32(Rn); +IF (IsDelaySlot()) +THROW ILLSLOT; +target ← ZeroExtend32(pc + 4 + op1); +delayedpc ← target ∧ (~ 0x1); +PC’’ ← Register(delayedpc); diff --git a/sh4/BRK b/sh4/BRK new file mode 100644 index 0000000..6d9f254 --- /dev/null +++ b/sh4/BRK @@ -0,0 +1,2 @@ +0000000000111011 +THROW BREAK; diff --git a/sh4/BSR label b/sh4/BSR label new file mode 100644 index 0000000..37e3d6f --- /dev/null +++ b/sh4/BSR label @@ -0,0 +1,10 @@ +1011dddddddddddd +pc ← SignExtend32(PC); +label ← SignExtend12(s) << 1; +IF (IsDelaySlot()) +THROW ILLSLOT; +delayedpr ← pc + 4; +temp ← ZeroExtend32(pc + 4 + label); +delayedpc ← temp; +PR’’ ← Register(delayedpr); +PC’’ ← Register(delayedpc); diff --git a/sh4/BSRF Rn b/sh4/BSRF Rn new file mode 100644 index 0000000..9437004 --- /dev/null +++ b/sh4/BSRF Rn @@ -0,0 +1,10 @@ +0000nnnn00000011 +pc ← SignExtend32(PC); +op1 ← SignExtend32(Rn); +IF (IsDelaySlot()) +THROW ILLSLOT; +delayedpr ← pc + 4; +target ← ZeroExtend32(pc + 4 + op1); +delayedpc ← target ∧ (~ 0x1); +PR’’ ← Register(delayedpr); +PC’’ ← Register(delayedpc); diff --git a/sh4/BT label b/sh4/BT label new file mode 100644 index 0000000..cf49168 --- /dev/null +++ b/sh4/BT label @@ -0,0 +1,16 @@ +10001001dddddddd +t ← ZeroExtend1(T); +pc ← SignExtend32(PC); +newpc ← SignExtend32(PC’); +delayedpc ← SignExtend32(PC’’); +label ← SignExtend8(s) << 1; +IF (IsDelaySlot()) +THROW ILLSLOT; +IF (t = 1) +{ +temp ← ZeroExtend32(pc + 4 + label); +newpc ← temp; +delayedpc ← temp + 2; +} +PC’ ← Register(newpc); +PC’’ ← Register(delayedpc); diff --git a/sh4/BT_S label b/sh4/BT_S label new file mode 100644 index 0000000..185c828 --- /dev/null +++ b/sh4/BT_S label @@ -0,0 +1,13 @@ +10001101dddddddd +t ← ZeroExtend1(T); +pc ← SignExtend32(PC); +delayedpc ← SignExtend32(PC’’); +label ← SignExtend8(s) << 1; +IF (IsDelaySlot()) +THROW ILLSLOT; +IF (t = 1) +{ +temp ← ZeroExtend32(pc + 4 + label); +delayedpc ← temp; +} +PC’’ ← Register(delayedpc); diff --git a/sh4/CLRMAC b/sh4/CLRMAC new file mode 100644 index 0000000..15fa52a --- /dev/null +++ b/sh4/CLRMAC @@ -0,0 +1,5 @@ +0000000000101000 +macl ← 0; +mach ← 0; +MACL ← ZeroExtend32(macl); +MACH ← ZeroExtend32(mach); diff --git a/sh4/CLRS b/sh4/CLRS new file mode 100644 index 0000000..c886d90 --- /dev/null +++ b/sh4/CLRS @@ -0,0 +1,3 @@ +0000000001001000 +s ← 0; +S ← Bit(s); diff --git a/sh4/CLRT b/sh4/CLRT new file mode 100644 index 0000000..5780484 --- /dev/null +++ b/sh4/CLRT @@ -0,0 +1,3 @@ +0000000000001000 +t ← 0; +T ← Bit(t); diff --git a/sh4/CMP_EQ #imm,R0 b/sh4/CMP_EQ #imm,R0 new file mode 100644 index 0000000..ff25bfd --- /dev/null +++ b/sh4/CMP_EQ #imm,R0 @@ -0,0 +1,5 @@ +10001000iiiiiiii +r0 ← SignExtend32(R0); +imm ← SignExtend8(s); +t ← INT (r0 = imm); +T ← Bit(t); diff --git a/sh4/CMP_EQ Rm,Rn b/sh4/CMP_EQ Rm,Rn new file mode 100644 index 0000000..1365138 --- /dev/null +++ b/sh4/CMP_EQ Rm,Rn @@ -0,0 +1,5 @@ +0011nnnnmmmm0000 +op1 ← SignExtend32(Rm); +op2 ← SignExtend32(Rn); +t ← INT (op2 = op1); +T ← Bit(t); diff --git a/sh4/CMP_GE Rm,Rn b/sh4/CMP_GE Rm,Rn new file mode 100644 index 0000000..5f92656 --- /dev/null +++ b/sh4/CMP_GE Rm,Rn @@ -0,0 +1,5 @@ +0011nnnnmmmm0011 +op1 ← SignExtend32(Rm); +op2 ← SignExtend32(Rn); +t ← INT (op2 ≥ op1); +T ← Bit(t); diff --git a/sh4/CMP_GT Rm,Rn b/sh4/CMP_GT Rm,Rn new file mode 100644 index 0000000..513bfaa --- /dev/null +++ b/sh4/CMP_GT Rm,Rn @@ -0,0 +1,5 @@ +0011nnnnmmmm0111 +op1 ← SignExtend32(Rm); +op2 ← SignExtend32(Rn); +t ← INT (op2 > op1); +T ← Bit(t); diff --git a/sh4/CMP_HI Rm,Rn b/sh4/CMP_HI Rm,Rn new file mode 100644 index 0000000..5ef32d2 --- /dev/null +++ b/sh4/CMP_HI Rm,Rn @@ -0,0 +1,5 @@ +0011nnnnmmmm0110 +op1 ← ZeroExtend32(SignExtend32(Rm)); +op2 ← ZeroExtend32(SignExtend32(Rn)); +t ← INT (op2 > op1); +T ← Bit(t); diff --git a/sh4/CMP_HS Rm,Rn b/sh4/CMP_HS Rm,Rn new file mode 100644 index 0000000..c37d838 --- /dev/null +++ b/sh4/CMP_HS Rm,Rn @@ -0,0 +1,5 @@ +0011nnnnmmmm0010 +op1 ← ZeroExtend32(SignExtend32(Rm)); +op2 ← ZeroExtend32(SignExtend32(Rn)); +t ← INT (op2 ≥ op1); +T ← Bit(t); diff --git a/sh4/CMP_PL Rn b/sh4/CMP_PL Rn new file mode 100644 index 0000000..928d3d4 --- /dev/null +++ b/sh4/CMP_PL Rn @@ -0,0 +1,4 @@ +0100nnnn00010101 +op1 ← SignExtend32(Rn); +t ← INT (op1 > 0); +T ← Bit(t); diff --git a/sh4/CMP_PZ Rn b/sh4/CMP_PZ Rn new file mode 100644 index 0000000..a7a9def --- /dev/null +++ b/sh4/CMP_PZ Rn @@ -0,0 +1,4 @@ +0100nnnn00010001 +op1 ← SignExtend32(Rn); +t ← INT (op1 ≥ 0); +T ← Bit(t); diff --git a/sh4/CMP_STR Rm,Rn b/sh4/CMP_STR Rm,Rn new file mode 100644 index 0000000..6545460 --- /dev/null +++ b/sh4/CMP_STR Rm,Rn @@ -0,0 +1,9 @@ +0010nnnnmmmm1100 +op1 ← SignExtend32(Rm); +op2 ← SignExtend32(Rn); +temp ← op1 ⊕ op2; +t ← INT (temp< 0 FOR 8 > = 0); +t ← (INT (temp< 8 FOR 8 > = 0)) ∨ t; +t ← (INT (temp< 16 FOR 8 > = 0)) ∨ t; +t ← (INT (temp< 24 FOR 8 > = 0)) ∨ t; +T ← Bit(t); diff --git a/sh4/DIV0S Rm,Rn b/sh4/DIV0S Rm,Rn new file mode 100644 index 0000000..c4614c2 --- /dev/null +++ b/sh4/DIV0S Rm,Rn @@ -0,0 +1,9 @@ +0010nnnnmmmm0111 +op1 ← SignExtend32(Rm); +op2 ← SignExtend32(Rn); +q ← op2< 31 FOR 1 >; +m ← op1< 31 FOR 1 >; +t ← m ⊕ q; +Q ← Bit(q); +M ← Bit(m); +T ← Bit(t); diff --git a/sh4/DIV0U b/sh4/DIV0U new file mode 100644 index 0000000..7ffb3b2 --- /dev/null +++ b/sh4/DIV0U @@ -0,0 +1,7 @@ +0000000000011001 +q ← 0; +m ← 0; +t ← 0; +Q ← Bit(q); +M ← Bit(m); +T ← Bit(t); diff --git a/sh4/DIV1 Rm,Rn b/sh4/DIV1 Rm,Rn new file mode 100644 index 0000000..bc23fc5 --- /dev/null +++ b/sh4/DIV1 Rm,Rn @@ -0,0 +1,18 @@ +0011nnnnmmmm0100 +q ← ZeroExtend1(Q); +m ← ZeroExtend1(M); +t ← ZeroExtend1(T); +op1 ← ZeroExtend32(SignExtend32(Rm)); +op2 ← ZeroExtend32(SignExtend32(Rn)); +oldq ← q; +q ← op2< 31 FOR 1 >; +op2 ← ZeroExtend32(op2 << 1) ∨ t; +IF (oldq = m) +op2 ← op2 - op1; +ELSE +op2 ← op2 + op1; +q ← (q ⊕ m) ⊕ op2< 32 FOR 1 >; +t ← 1 - (q ⊕ m); +Rn ← Register(op2); +Q ← Bit(q); +T ← Bit(t); diff --git a/sh4/DMULS.L Rm,Rn b/sh4/DMULS.L Rm,Rn new file mode 100644 index 0000000..32d8c3d --- /dev/null +++ b/sh4/DMULS.L Rm,Rn @@ -0,0 +1,8 @@ +0011nnnnmmmm1101 +op1 ← SignExtend32(Rm); +op2 ← SignExtend32(Rn); +mac ← op2 × op1; +macl ← mac; +mach ← mac >> 32; +MACL ← ZeroExtend32(macl); +MACH ← ZeroExtend32(mach); diff --git a/sh4/DMULU.L Rm,Rn b/sh4/DMULU.L Rm,Rn new file mode 100644 index 0000000..2bb2aa8 --- /dev/null +++ b/sh4/DMULU.L Rm,Rn @@ -0,0 +1,8 @@ +0011nnnnmmmm0101 +op1 ← ZeroExtend32(SignExtend32(Rm)); +op2 ← ZeroExtend32(SignExtend32(Rn)); +mac ← op2 × op1; +macl ← mac; +mach ← mac >> 32; +MACL ← ZeroExtend32(macl); +MACH ← ZeroExtend32(mach); diff --git a/sh4/DT Rn b/sh4/DT Rn new file mode 100644 index 0000000..962adc1 --- /dev/null +++ b/sh4/DT Rn @@ -0,0 +1,6 @@ +0100nnnn00010000 +op1 ← SignExtend32(Rn); +op1 ← op1 - 1; +t ← INT (op1 = 0); +Rn ← Register(op1); +T ← Bit(t); diff --git a/sh4/EXTS.B Rm,Rn b/sh4/EXTS.B Rm,Rn new file mode 100644 index 0000000..cc4322f --- /dev/null +++ b/sh4/EXTS.B Rm,Rn @@ -0,0 +1,4 @@ +0110nnnnmmmm1110 +op1 ← SignExtend8(Rm); +op2 ← op1; +Rn ← Register(op2); diff --git a/sh4/EXTS.W Rm,Rn b/sh4/EXTS.W Rm,Rn new file mode 100644 index 0000000..29f0897 --- /dev/null +++ b/sh4/EXTS.W Rm,Rn @@ -0,0 +1,4 @@ +0110nnnnmmmm1111 +op1 ← SignExtend16(Rm); +op2 ← op1; +Rn ← Register(op2); diff --git a/sh4/EXTU.B Rm,Rn b/sh4/EXTU.B Rm,Rn new file mode 100644 index 0000000..eba30e5 --- /dev/null +++ b/sh4/EXTU.B Rm,Rn @@ -0,0 +1,4 @@ +0110nnnnmmmm1100 +op1 ← ZeroExtend8(Rm); +op2 ← op1; +Rn ← Register(op2); diff --git a/sh4/EXTU.W Rm,Rn b/sh4/EXTU.W Rm,Rn new file mode 100644 index 0000000..34473e9 --- /dev/null +++ b/sh4/EXTU.W Rm,Rn @@ -0,0 +1,4 @@ +0110nnnnmmmm1101 +op1 ← ZeroExtend16(Rm); +op2 ← op1; +Rn ← Register(op2); diff --git a/sh4/FABS DRn b/sh4/FABS DRn new file mode 100644 index 0000000..3c26cc2 --- /dev/null +++ b/sh4/FABS DRn @@ -0,0 +1,10 @@ +1111nnn001011101 +Available only when PR=1 and SZ=0 +sr ← ZeroExtend32(SR); +op1 ← FloatValue64(DR2n); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +op1 ← FABS_D(op1); +DR2n ← FloatRegister64(op1); diff --git a/sh4/FABS FRn b/sh4/FABS FRn new file mode 100644 index 0000000..abb38df --- /dev/null +++ b/sh4/FABS FRn @@ -0,0 +1,10 @@ +1111nnnn01011101 +Available only when PR=0 +sr ← ZeroExtend32(SR); +op1 ← FloatValue32(FRn); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +op1 ← FABS_S(op1); +FRn ← FloatRegister32(op1); diff --git a/sh4/FADD DRm,DRn b/sh4/FADD DRm,DRn new file mode 100644 index 0000000..684980d --- /dev/null +++ b/sh4/FADD DRm,DRn @@ -0,0 +1,19 @@ +1111nnn0mmm00000 +Available only when PR=1 and SZ=0 +sr ← ZeroExtend32(SR); +fps ← ZeroExtend32(FPSCR); +op1 ← FloatValue64(DR2m); +op2 ← FloatValue64(DR2n); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +op2, fps ← FADD_D(op1, op2, fps); +IF (FpuEnableV(fps) AND FpuCauseV(fps)) +THROW FPUEXC, fps; +IF (FpuCauseE(fps)) +THROW FPUEXC, fps; +IF ((FpuEnableI(fps) OR FpuEnableO(fps)) OR FpuEnableU(fps)) +THROW FPUEXC, fps; +DR2n ← FloatRegister64(op2); +FPSCR ← ZeroExtend32(fps); diff --git a/sh4/FADD FRm,FRn b/sh4/FADD FRm,FRn new file mode 100644 index 0000000..fc07f70 --- /dev/null +++ b/sh4/FADD FRm,FRn @@ -0,0 +1,19 @@ +1111nnnnmmmm0000 +Available only when PR=0 +sr ← ZeroExtend32(SR); +fps ← ZeroExtend32(FPSCR); +op1 ← FloatValue32(FRm); +op2 ← FloatValue32(FRn); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +op2, fps ← FADD_S(op1, op2, fps); +IF (FpuEnableV(fps) AND FpuCauseV(fps)) +THROW FPUEXC, fps; +IF (FpuCauseE(fps)) +THROW FPUEXC, fps; +IF ((FpuEnableI(fps) OR FpuEnableO(fps)) OR FpuEnableU(fps)) +THROW FPUEXC, fps; +FRn ← FloatRegister32(op2); +FPSCR ← ZeroExtend32(fps); diff --git a/sh4/FCMP_EQ DRm,DRn b/sh4/FCMP_EQ DRm,DRn new file mode 100644 index 0000000..b8b9537 --- /dev/null +++ b/sh4/FCMP_EQ DRm,DRn @@ -0,0 +1,15 @@ +1111nnn0mmm00100 +Available only when PR=1 and SZ=0 +sr ← ZeroExtend32(SR); +fps ← ZeroExtend32(FPSCR); +op1 ← FloatValue64(DR2m); +op2 ← FloatValue64(DR2n); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +t, fps ← FCMPEQ_D(op1, op2, fps); +IF (FpuEnableV(fps) AND FpuCauseV(fps)) +THROW FPUEXC, fps; +FPSCR ← ZeroExtend32(fps); +T ← Bit(t); diff --git a/sh4/FCMP_EQ FRm,FRn b/sh4/FCMP_EQ FRm,FRn new file mode 100644 index 0000000..ebb64f7 --- /dev/null +++ b/sh4/FCMP_EQ FRm,FRn @@ -0,0 +1,15 @@ +1111nnnnmmmm0100 +Available only when PR=0 +sr ← ZeroExtend32(SR); +fps ← ZeroExtend32(FPSCR); +op1 ← FloatValue32(FRm); +op2 ← FloatValue32(FRn); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +t, fps ← FCMPEQ_S(op1, op2, fps); +IF (FpuEnableV(fps) AND FpuCauseV(fps)) +THROW FPUEXC, fps; +FPSCR ← ZeroExtend32(fps); +T ← Bit(t); diff --git a/sh4/FCMP_GT DRm,DRn b/sh4/FCMP_GT DRm,DRn new file mode 100644 index 0000000..f1bec8b --- /dev/null +++ b/sh4/FCMP_GT DRm,DRn @@ -0,0 +1,15 @@ +1111nnn0mmm00101 +Available only when PR=1 and SZ=0 +sr ← ZeroExtend32(SR); +fps ← ZeroExtend32(FPSCR); +op1 ← FloatValue64(DR2m); +op2 ← FloatValue64(DR2n); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +t, fps ← FCMPGT_D(op2, op1, fps); +IF (FpuEnableV(fps) AND FpuCauseV(fps)) +THROW FPUEXC, fps; +FPSCR ← ZeroExtend32(fps); +T ← Bit(t); diff --git a/sh4/FCMP_GT FRm,FRn b/sh4/FCMP_GT FRm,FRn new file mode 100644 index 0000000..2fffd3f --- /dev/null +++ b/sh4/FCMP_GT FRm,FRn @@ -0,0 +1,15 @@ +1111nnnnmmmm0101 +Available only when PR=0 +sr ← ZeroExtend32(SR); +fps ← ZeroExtend32(FPSCR); +op1 ← FloatValue32(FRm); +op2 ← FloatValue32(FRn); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +t, fps ← FCMPGT_S(op2, op1, fps); +IF (FpuEnableV(fps) AND FpuCauseV(fps)) +THROW FPUEXC, fps; +FPSCR ← ZeroExtend32(fps); +T ← Bit(t); diff --git a/sh4/FCNVDS DRm,FPUL b/sh4/FCNVDS DRm,FPUL new file mode 100644 index 0000000..b9d5375 --- /dev/null +++ b/sh4/FCNVDS DRm,FPUL @@ -0,0 +1,18 @@ +1111mmm010111101 +Available only when PR=1 and SZ=0 +sr ← ZeroExtend32(SR); +fps ← ZeroExtend32(FPSCR); +op1 ← FloatValue64(DR2m); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +fpul, fps ← FCNV_DS(op1, fps); +IF (FpuEnableV(fps) AND FpuCauseV(fps)) +THROW FPUEXC, fps; +IF (FpuCauseE(fps)) +THROW FPUEXC, fps; +IF ((FpuEnableI(fps) OR FpuEnableO(fps)) OR FpuEnableU(fps)) +THROW FPUEXC, fps; +FPSCR ← ZeroExtend32(fps); +FPUL ← ZeroExtend32(fpul); diff --git a/sh4/FCNVSD FPUL,DRn b/sh4/FCNVSD FPUL,DRn new file mode 100644 index 0000000..2d961a6 --- /dev/null +++ b/sh4/FCNVSD FPUL,DRn @@ -0,0 +1,16 @@ +1111nnn010101101 +Available only when PR=1 and SZ=0 +sr ← ZeroExtend32(SR); +fps ← ZeroExtend32(FPSCR); +fpul ← SignExtend32(FPUL); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +op1, fps ← FCNV_SD(fpul, fps); +IF (FpuEnableV(fps) AND FpuCauseV(fps)) +THROW FPUEXC, fps; +IF (FpuCauseE(fps)) +THROW FPUEXC, fps; +DR2n ← FloatRegister64(op1); +FPSCR ← ZeroExtend32(fps); diff --git a/sh4/FCSA FPUL,DRn b/sh4/FCSA FPUL,DRn new file mode 100644 index 0000000..1b2ce5f --- /dev/null +++ b/sh4/FCSA FPUL,DRn @@ -0,0 +1 @@ +1111nnn011111101 diff --git a/sh4/FDIV DRm,DRn b/sh4/FDIV DRm,DRn new file mode 100644 index 0000000..db07d15 --- /dev/null +++ b/sh4/FDIV DRm,DRn @@ -0,0 +1,21 @@ +1111nnn0mmm00011 +Available only when PR=1 and SZ=0 +sr ← ZeroExtend32(SR); +fps ← ZeroExtend32(FPSCR); +op1 ← FloatValue64(DR2m); +op2 ← FloatValue64(DR2n); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +op2, fps ← FDIV_D(op2, op1, fps); +IF (FpuEnableV(fps) AND FpuCauseV(fps)) +THROW FPUEXC, fps; +IF (FpuEnableZ(fps) AND FpuCauseZ(fps)) +THROW FPUEXC, fps; +IF (FpuCauseE(fps)) +THROW FPUEXC, fps; +IF ((FpuEnableI(fps) OR FpuEnableO(fps)) OR FpuEnableU(fps)) +THROW FPUEXC, fps; +DR2n ← FloatRegister64(op2); +FPSCR ← ZeroExtend32(fps); diff --git a/sh4/FDIV FRm,FRn b/sh4/FDIV FRm,FRn new file mode 100644 index 0000000..c29abba --- /dev/null +++ b/sh4/FDIV FRm,FRn @@ -0,0 +1,21 @@ +1111nnnnmmmm0011 +Available only when PR=0 +sr ← ZeroExtend32(SR); +fps ← ZeroExtend32(FPSCR); +op1 ← FloatValue32(FRm); +op2 ← FloatValue32(FRn); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +op2, fps ← FDIV_S(op2, op1, fps); +IF (FpuEnableV(fps) AND FpuCauseV(fps)) +THROW FPUEXC, fps; +IF (FpuEnableZ(fps) AND FpuCauseZ(fps)) +THROW FPUEXC, fps; +IF (FpuCauseE(fps)) +THROW FPUEXC, fps; +IF ((FpuEnableI(fps) OR FpuEnableO(fps)) OR FpuEnableU(fps)) +THROW FPUEXC, fps; +FRn ← FloatRegister32(op2); +FPSCR ← ZeroExtend32(fps); diff --git a/sh4/FIPR FVm,FVn b/sh4/FIPR FVm,FVn new file mode 100644 index 0000000..c123b31 --- /dev/null +++ b/sh4/FIPR FVm,FVn @@ -0,0 +1,17 @@ +1111nnmm11101101 +Available only when PR=0 +sr ← ZeroExtend32(SR); +fps ← ZeroExtend32(FPSCR); +op1 ← FloatValueVector32(FV4m); +op2 ← FloatValueVector32(FV4n); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +op2[3], fps ← FIPR_S(op1, op2, fps); +IF (FpuEnableV(fps) AND FpuCauseV(fps)) +THROW FPUEXC, fps; +IF ((FpuEnableI(fps) OR FpuEnableO(fps)) OR FpuEnableU(fps)) +THROW FPUEXC, fps; +FV4n ← FloatRegisterVector32(op2); +FPSCR ← ZeroExtend32(fps); diff --git a/sh4/FLDI0 FRn b/sh4/FLDI0 FRn new file mode 100644 index 0000000..01914a2 --- /dev/null +++ b/sh4/FLDI0 FRn @@ -0,0 +1,9 @@ +1111nnnn10001101 +Available only when PR=0 +sr ← ZeroExtend32(SR); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +op1 ← 0x00000000; +FRn ← FloatRegister32(op1); \ No newline at end of file diff --git a/sh4/FLDI1 FRn b/sh4/FLDI1 FRn new file mode 100644 index 0000000..37de5a0 --- /dev/null +++ b/sh4/FLDI1 FRn @@ -0,0 +1,9 @@ +1111nnnn10011101 +Available only when PR=0 +sr ← ZeroExtend32(SR); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +op1 ← 0x3F800000; +FRn ← FloatRegister32(op1); diff --git a/sh4/FLDS FRm,FPUL b/sh4/FLDS FRm,FPUL new file mode 100644 index 0000000..ef6ab7e --- /dev/null +++ b/sh4/FLDS FRm,FPUL @@ -0,0 +1,9 @@ +1111mmmm00011101 +sr ← ZeroExtend32(SR); +op1 ← FloatValue32(FRm); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +fpul ← op1; +FPUL ← ZeroExtend32(fpul); diff --git a/sh4/FLOAT FPUL,DRn b/sh4/FLOAT FPUL,DRn new file mode 100644 index 0000000..c6698b5 --- /dev/null +++ b/sh4/FLOAT FPUL,DRn @@ -0,0 +1,11 @@ +1111nnn000101101 +Available only when PR=1 and SZ=0 +fpul ← SignExtend32(FPUL); +sr ← ZeroExtend32(SR); +fps ← ZeroExtend32(FPSCR); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +op1, fps ← FLOAT_LD(fpul, fps); +DR2n ← FloatRegister64(op1); diff --git a/sh4/FLOAT FPUL,FRn b/sh4/FLOAT FPUL,FRn new file mode 100644 index 0000000..2db7431 --- /dev/null +++ b/sh4/FLOAT FPUL,FRn @@ -0,0 +1,14 @@ +1111nnnn00101101 +Available only when PR=0 +sr ← ZeroExtend32(SR); +fps ← ZeroExtend32(FPSCR); +fpul ← SignExtend32(FPUL); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +op1, fps ← FLOAT_LS(fpul, fps); +IF (FpuEnableI(fps)) +THROW FPUEXC, fps; +FRn ← FloatRegister32(op1); +FPSCR ← ZeroExtend32(fps); diff --git a/sh4/FMAC FR0,FRm,FRn b/sh4/FMAC FR0,FRm,FRn new file mode 100644 index 0000000..8964df8 --- /dev/null +++ b/sh4/FMAC FR0,FRm,FRn @@ -0,0 +1,20 @@ +1111nnnnmmmm1110 +Available only when PR=0 +sr ← ZeroExtend32(SR); +fps ← ZeroExtend32(FPSCR); +fr0 ← FloatValue32(FR0); +op1 ← FloatValue32(FRm); +op2 ← FloatValue32(FRn); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +op2, fps ← FMAC_S(fr0, op1, op2, fps); +IF (FpuEnableV(fps) AND FpuCauseV(fps)) +THROW FPUEXC, fps; +IF (FpuCauseE(fps)) +THROW FPUEXC, fps; +IF ((FpuEnableI(fps) OR FpuEnableO(fps)) OR FpuEnableU(fps)) +THROW FPUEXC, fps; +FRn ← FloatRegister32(op2); +FPSCR ← ZeroExtend32(fps); diff --git a/sh4/FMOV @(R0,Rm),DRn b/sh4/FMOV @(R0,Rm),DRn new file mode 100644 index 0000000..db556fb --- /dev/null +++ b/sh4/FMOV @(R0,Rm),DRn @@ -0,0 +1,12 @@ +1111nnn0mmmm0110 +Available only when PR=0 and SZ=1 +sr ← ZeroExtend32(SR); +r0 ← SignExtend32(R0); +op1 ← SignExtend32(Rm); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +address ← ZeroExtend32(r0 + op1); +op2 ← ReadMemoryPair32(address); +FP2n ← FloatRegisterPair32(op2); diff --git a/sh4/FMOV @(R0,Rm),XDn b/sh4/FMOV @(R0,Rm),XDn new file mode 100644 index 0000000..60883d6 --- /dev/null +++ b/sh4/FMOV @(R0,Rm),XDn @@ -0,0 +1,12 @@ +1111nnn1mmmm0110 +Available only when PR=0 and SZ=1 +sr ← ZeroExtend32(SR); +r0 ← SignExtend32(R0); +op1 ← SignExtend32(Rm); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +address ← ZeroExtend32(r0 + op1); +op2 ← ReadMemoryPair32(address); +XD2n ← FloatRegisterPair32(op2); diff --git a/sh4/FMOV @Rm+,DRn b/sh4/FMOV @Rm+,DRn new file mode 100644 index 0000000..ad721b7 --- /dev/null +++ b/sh4/FMOV @Rm+,DRn @@ -0,0 +1,14 @@ +1111nnn0mmmm1001 +Available only when PR=0 and SZ=1 +sr ← ZeroExtend32(SR); +fps ← ZeroExtend32(FPSCR); +op1 ← SignExtend32(Rm); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +address ← ZeroExtend32(op1); +op2 ← ReadMemoryPair32(address); +op1 ← op1 + 8; +Rm ← Register(op1); +FP2n ← FloatRegisterPair32(op2); diff --git a/sh4/FMOV @Rm+,XDn b/sh4/FMOV @Rm+,XDn new file mode 100644 index 0000000..2337b18 --- /dev/null +++ b/sh4/FMOV @Rm+,XDn @@ -0,0 +1,14 @@ +1111nnn1mmmm1001 +Available only when PR=0 and SZ=1 +sr ← ZeroExtend32(SR); +fps ← ZeroExtend32(FPSCR); +op1 ← SignExtend32(Rm); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +address ← ZeroExtend32(op1); +op2 ← ReadMemoryPair32(address); +op1 ← op1 + 8; +Rm ← Register(op1); +XD2n ← FloatRegisterPair32(op2); diff --git a/sh4/FMOV @Rm,DRn b/sh4/FMOV @Rm,DRn new file mode 100644 index 0000000..b437805 --- /dev/null +++ b/sh4/FMOV @Rm,DRn @@ -0,0 +1,11 @@ +1111nnn0mmmm1000 +Available only when PR=0 and SZ=1 +sr ← ZeroExtend32(SR); +op1 ← SignExtend32(Rm); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +address ← ZeroExtend32(op1); +op2 ← ReadMemoryPair32(address); +FP2n ← FloatRegisterPair32(op2); diff --git a/sh4/FMOV @Rm,XDn b/sh4/FMOV @Rm,XDn new file mode 100644 index 0000000..b1b74a3 --- /dev/null +++ b/sh4/FMOV @Rm,XDn @@ -0,0 +1,12 @@ +1111nnn1mmmm1000 +Available only when PR=0 and SZ=1 +sr ← ZeroExtend32(SR); +fps ← ZeroExtend32(FPSCR); +op1 ← SignExtend32(Rm); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +address ← ZeroExtend32(op1); +op2 ← ReadMemoryPair32(address); +XD2n ← FloatRegisterPair32(op2); diff --git a/sh4/FMOV DRm,@(R0,Rn) b/sh4/FMOV DRm,@(R0,Rn) new file mode 100644 index 0000000..53de501 --- /dev/null +++ b/sh4/FMOV DRm,@(R0,Rn) @@ -0,0 +1,12 @@ +1111nnnnmmm00111 +Available only when PR=0 and SZ=1 +sr ← ZeroExtend32(SR); +r0 ← SignExtend32(R0); +op1 ← FloatValuePair32(FP2m); +op2 ← SignExtend32(Rn); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +address ← ZeroExtend32(r0 + op2); +WriteMemoryPair32(address, op1); diff --git a/sh4/FMOV DRm,@-Rn b/sh4/FMOV DRm,@-Rn new file mode 100644 index 0000000..c78644f --- /dev/null +++ b/sh4/FMOV DRm,@-Rn @@ -0,0 +1,14 @@ +1111nnnnmmm01011 +Available only when PR=0 and SZ=1 +sr ← ZeroExtend32(SR); +fps ← ZeroExtend32(FPSCR); +op1 ← FloatValuePair32(FP2m); +op2 ← SignExtend32(Rn); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +address ← ZeroExtend32(op2 - 8); +WriteMemoryPair32(address, op1); +op2 ← address; +Rn ← Register(op2); diff --git a/sh4/FMOV DRm,@Rn b/sh4/FMOV DRm,@Rn new file mode 100644 index 0000000..e0cf5a7 --- /dev/null +++ b/sh4/FMOV DRm,@Rn @@ -0,0 +1,12 @@ +1111nnnnmmm01010 +Available only when PR=0 and SZ=1 +sr ← ZeroExtend32(SR); +fps ← ZeroExtend32(FPSCR); +op1 ← FloatValuePair32(FP2m); +op2 ← SignExtend32(Rn); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +address ← ZeroExtend32(op2); +WriteMemoryPair32(address, op1); diff --git a/sh4/FMOV DRm,DRn b/sh4/FMOV DRm,DRn new file mode 100644 index 0000000..a3ce064 --- /dev/null +++ b/sh4/FMOV DRm,DRn @@ -0,0 +1,10 @@ +1111nnn0mmm01100 +Available only when PR=0 and SZ=1 +sr ← ZeroExtend32(SR); +op1 ← FloatValuePair32(FP2m); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +op2 ← op1; +FP2n ← FloatRegisterPair32(op2); diff --git a/sh4/FMOV DRm,XDn b/sh4/FMOV DRm,XDn new file mode 100644 index 0000000..1d71cfd --- /dev/null +++ b/sh4/FMOV DRm,XDn @@ -0,0 +1,10 @@ +1111nnn1mmm01100 +Available only when PR=0 and SZ=1 +sr ← ZeroExtend32(SR); +op1 ← FloatValuePair32(DR2m); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +op2 ← op1; +XD2n ← FloatRegisterPair32(op2); diff --git a/sh4/FMOV FRm,FRn b/sh4/FMOV FRm,FRn new file mode 100644 index 0000000..ee810f1 --- /dev/null +++ b/sh4/FMOV FRm,FRn @@ -0,0 +1,11 @@ +1111nnnnmmmm1100 +Available only when SZ=0 +sr ← ZeroExtend32(SR); +fps ← ZeroExtend32(FPSCR); +op1 ← FloatValue32(FRm); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +op2 ← op1; +FRn ← FloatRegister32(op2); diff --git a/sh4/FMOV XDm,@(R0,Rn) b/sh4/FMOV XDm,@(R0,Rn) new file mode 100644 index 0000000..1bdcb1d --- /dev/null +++ b/sh4/FMOV XDm,@(R0,Rn) @@ -0,0 +1,12 @@ +1111nnnnmmm10111 +Available only when PR=0 and SZ=1 +sr ← ZeroExtend32(SR); +r0 ← SignExtend32(R0); +op1 ← FloatValuePair32(XD2m); +op2 ← SignExtend32(Rn); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +address ← ZeroExtend32(r0 + op2); +WriteMemoryPair32(address, op1); diff --git a/sh4/FMOV XDm,@-Rn b/sh4/FMOV XDm,@-Rn new file mode 100644 index 0000000..d1fe6a8 --- /dev/null +++ b/sh4/FMOV XDm,@-Rn @@ -0,0 +1,15 @@ +1111nnnnmmm11011 +Available only when PR=0 and SZ=1 +sr ← ZeroExtend32(SR); +fps ← ZeroExtend32(FPSCR); +op1 ← FloatValuePair32(XD2m); +op2 ← SignExtend32(Rn); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +address ← ZeroExtend32(op2 - 8); +WriteMemoryPair32(address, op1); +op2 ← address; +Rn ← Register(op2); +FPSCR ← ZeroExtend32(fps); diff --git a/sh4/FMOV XDm,@Rn b/sh4/FMOV XDm,@Rn new file mode 100644 index 0000000..c5c5cc2 --- /dev/null +++ b/sh4/FMOV XDm,@Rn @@ -0,0 +1,12 @@ +1111nnnnmmm11010 +Available only when PR=0 and SZ=1 +sr ← ZeroExtend32(SR); +fps ← ZeroExtend32(FPSCR); +op1 ← FloatValuePair32(XD2m); +op2 ← SignExtend32(Rn); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +address ← ZeroExtend32(op2); +WriteMemoryPair32(address, op1); diff --git a/sh4/FMOV XDm,DRn b/sh4/FMOV XDm,DRn new file mode 100644 index 0000000..8259b74 --- /dev/null +++ b/sh4/FMOV XDm,DRn @@ -0,0 +1,11 @@ +1111nnn0mmm11100 +Available only when PR=0 and SZ=1 +sr ← ZeroExtend32(SR); +fps ← ZeroExtend32(FPSCR); +op1 ← FloatValuePair32(XD2m); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +op2 ← op1; +DR2n ← FloatRegisterPair32(op2); diff --git a/sh4/FMOV XDm,XDn b/sh4/FMOV XDm,XDn new file mode 100644 index 0000000..341c6f1 --- /dev/null +++ b/sh4/FMOV XDm,XDn @@ -0,0 +1,11 @@ +1111nnn1mmm11100 +Available only when PR=0 and SZ=1 +sr ← ZeroExtend32(SR); +fps ← ZeroExtend32(FPSCR); +op1 ← FloatValue64(XD2m); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +op2 ← op1; +XD2n ← FloatRegister64(op2); diff --git a/sh4/FMOV.S @(R0,Rm),FRn b/sh4/FMOV.S @(R0,Rm),FRn new file mode 100644 index 0000000..7ae6cb0 --- /dev/null +++ b/sh4/FMOV.S @(R0,Rm),FRn @@ -0,0 +1,12 @@ +1111nnnnmmmm0110 +Available only when SZ=0 +sr ← ZeroExtend32(SR); +r0 ← SignExtend32(R0); +op1 ← SignExtend32(Rm); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +address ← ZeroExtend32(r0 + op1); +op2 ← ReadMemory32(address); +FRn ← FloatRegister32(op2); diff --git a/sh4/FMOV.S @Rm+,FRn b/sh4/FMOV.S @Rm+,FRn new file mode 100644 index 0000000..8626fed --- /dev/null +++ b/sh4/FMOV.S @Rm+,FRn @@ -0,0 +1,13 @@ +1111nnnnmmmm1001 +Available only when SZ=0 +sr ← ZeroExtend32(SR); +op1 ← SignExtend32(Rm); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +address ← ZeroExtend32(op1); +op2 ← ReadMemory32(address); +op1 ← op1 + 4; +Rm ← Register(op1); +FRn ← FloatRegister32(op2); diff --git a/sh4/FMOV.S @Rm,FRn b/sh4/FMOV.S @Rm,FRn new file mode 100644 index 0000000..3c063af --- /dev/null +++ b/sh4/FMOV.S @Rm,FRn @@ -0,0 +1,12 @@ +1111nnnnmmmm1000 +Available only when SZ=0 +sr ← ZeroExtend32(SR); +fps ← ZeroExtend32(FPSCR); +op1 ← SignExtend32(Rm); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +address ← ZeroExtend32(op1); +op2 ← ReadMemory32(address); +FR2n ← FloatRegister32(op2); diff --git a/sh4/FMOV.S FRm,@(R0,Rn) b/sh4/FMOV.S FRm,@(R0,Rn) new file mode 100644 index 0000000..3d1f469 --- /dev/null +++ b/sh4/FMOV.S FRm,@(R0,Rn) @@ -0,0 +1,12 @@ +1111nnnnmmmm0111 +Available only when SZ=0 +sr ← ZeroExtend32(SR); +r0 ← SignExtend32(R0); +op1 ← FloatValue32(FRm); +op2 ← SignExtend32(Rn); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +address ← ZeroExtend32(r0 + op2); +WriteMemory32(address, op1); diff --git a/sh4/FMOV.S FRm,@-Rn b/sh4/FMOV.S FRm,@-Rn new file mode 100644 index 0000000..38eb54d --- /dev/null +++ b/sh4/FMOV.S FRm,@-Rn @@ -0,0 +1,14 @@ +1111nnnnmmmm1011 +Available only when SZ=0 +sr ← ZeroExtend32(SR); +fps ← ZeroExtend32(FPSCR); +op1 ← FloatValue32(FRm); +op2 ← SignExtend32(Rn); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +address ← ZeroExtend32(op2 - 4); +WriteMemory32(address, op1); +op2 ← address; +Rn ← Register(op2); diff --git a/sh4/FMOV.S FRm,@Rn b/sh4/FMOV.S FRm,@Rn new file mode 100644 index 0000000..d6ae317 --- /dev/null +++ b/sh4/FMOV.S FRm,@Rn @@ -0,0 +1,12 @@ +1111nnnnmmmm1010 +Available only when SZ=0 +sr ← ZeroExtend32(SR); +fps ← ZeroExtend32(FPSCR); +op1 ← FloatValue32(FRm); +op2 ← SignExtend32(Rn); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +address ← ZeroExtend32(op2); +WriteMemory32(address, op1); diff --git a/sh4/FMUL DRm,DRn b/sh4/FMUL DRm,DRn new file mode 100644 index 0000000..efc631b --- /dev/null +++ b/sh4/FMUL DRm,DRn @@ -0,0 +1,19 @@ +1111nnn0mmm00010 +Available only when PR=1 and SZ=0 +sr ← ZeroExtend32(SR); +fps ← ZeroExtend32(FPSCR); +op1 ← FloatValue64(DR2m); +op2 ← FloatValue64(DR2n); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +op2, fps ← FMUL_D(op1, op2, fps); +IF (FpuEnableV(fps) AND FpuCauseV(fps)) +THROW FPUEXC, fps; +IF (FpuCauseE(fps)) +THROW FPUEXC, fps; +IF ((FpuEnableI(fps) OR FpuEnableO(fps)) OR FpuEnableU(fps)) +THROW FPUEXC, fps; +DR2n ← FloatRegister64(op2); +FPSCR ← ZeroExtend32(fps); diff --git a/sh4/FMUL FRm,FRn b/sh4/FMUL FRm,FRn new file mode 100644 index 0000000..13a7a33 --- /dev/null +++ b/sh4/FMUL FRm,FRn @@ -0,0 +1,19 @@ +1111nnnnmmmm0010 +Available only when PR=0 +sr ← ZeroExtend32(SR); +fps ← ZeroExtend32(FPSCR); +op1 ← FloatValue32(FRm); +op2 ← FloatValue32(FRn); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +op2, fps ← FMUL_S(op1, op2, fps); +IF (FpuEnableV(fps) AND FpuCauseV(fps)) +THROW FPUEXC, fps; +IF (FpuCauseE(fps)) +THROW FPUEXC, fps; +IF ((FpuEnableI(fps) OR FpuEnableO(fps)) OR FpuEnableU(fps)) +THROW FPUEXC, fps; +FRn ← FloatRegister32(op2); +FPSCR ← ZeroExtend32(fps); diff --git a/sh4/FNEG DRn b/sh4/FNEG DRn new file mode 100644 index 0000000..3939b9d --- /dev/null +++ b/sh4/FNEG DRn @@ -0,0 +1,10 @@ +1111nnn001001101 +Available only when PR=1 and SZ=0 +sr ← ZeroExtend32(SR); +op1 ← FloatValue64(DR2n); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +op1 ← FNEG_D(op1); +DR2n ← FloatRegister64(op1); diff --git a/sh4/FNEG FRn b/sh4/FNEG FRn new file mode 100644 index 0000000..48f0f7c --- /dev/null +++ b/sh4/FNEG FRn @@ -0,0 +1,11 @@ +1111nnnn01001101 +Available only when PR=0 +sr ← ZeroExtend32(SR); +fps ← ZeroExtend32(FPSCR); +op1 ← FloatValue32(FRn); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +op1 ← FNEG_S(op1); +FRn ← FloatRegister32(op1); diff --git a/sh4/FRCHG b/sh4/FRCHG new file mode 100644 index 0000000..6a023a3 --- /dev/null +++ b/sh4/FRCHG @@ -0,0 +1,10 @@ +1111101111111101 +Available only when PR=0 +sr ← ZeroExtend32(SR); +fr ← ZeroExtend1(SR.FR); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +fr ← fr ⊕ 1; +SR.FR ← Bit(fr); diff --git a/sh4/FSCHG b/sh4/FSCHG new file mode 100644 index 0000000..1f220ad --- /dev/null +++ b/sh4/FSCHG @@ -0,0 +1,10 @@ +1111001111111101 +Available only when PR=0 +sr ← ZeroExtend32(SR); +sz ← ZeroExtend1(SR.SZ); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +sz ← sz ⊕ 1; +SR.SZ ← Bit(sz); diff --git a/sh4/FSQRT DRn b/sh4/FSQRT DRn new file mode 100644 index 0000000..063a555 --- /dev/null +++ b/sh4/FSQRT DRn @@ -0,0 +1,18 @@ +1111nnn001101101 +Available only when PR=1 and SZ=0 +sr ← ZeroExtend32(SR); +fps ← ZeroExtend32(FPSCR); +op1 ← FloatValue64(DR2n); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +op1, fps ← FSQRT_D(op1, fps); +IF (FpuEnableV(fps) AND FpuCauseV(fps)) +THROW FPUEXC, fps; +IF (FpuCauseE(fps)) +THROW FPUEXC, fps; +IF (FpuEnableI(fps)) +THROW FPUEXC, fps; +DR2n ← FloatRegister64(op1); +FPSCR ← ZeroExtend32(fps); diff --git a/sh4/FSQRT FRn b/sh4/FSQRT FRn new file mode 100644 index 0000000..d58cdac --- /dev/null +++ b/sh4/FSQRT FRn @@ -0,0 +1,18 @@ +1111nnnn01101101 +Available only when PR=0 +sr ← ZeroExtend32(SR); +fps ← ZeroExtend32(FPSCR); +op1 ← FloatValue32(FRn); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +op1, fps ← FSQRT_S(op1, fps); +IF (FpuEnableV(fps) AND FpuCauseV(fps)) +THROW FPUEXC, fps; +IF (FpuCauseE(fps)) +THROW FPUEXC, fps; +IF (FpuEnableI(fps)) +THROW FPUEXC, fps; +FRn ← FloatRegister32(op1); +FPSCR ← ZeroExtend32(fps); diff --git a/sh4/FSRRA FRn b/sh4/FSRRA FRn new file mode 100644 index 0000000..3375cab --- /dev/null +++ b/sh4/FSRRA FRn @@ -0,0 +1 @@ +1111nnnn01111101 diff --git a/sh4/FSTS FPUL,FRn b/sh4/FSTS FPUL,FRn new file mode 100644 index 0000000..6c21e69 --- /dev/null +++ b/sh4/FSTS FPUL,FRn @@ -0,0 +1,9 @@ +1111nnnn00001101 +sr ← ZeroExtend32(SR); +fpul ← SignExtend32(FPUL); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +op1 ← fpul; +FRn ← FloatRegister32(op1); diff --git a/sh4/FSUB DRm,DRn b/sh4/FSUB DRm,DRn new file mode 100644 index 0000000..40b173c --- /dev/null +++ b/sh4/FSUB DRm,DRn @@ -0,0 +1,19 @@ +1111nnn0mmm00001 +Available only when PR=1 and SZ=0 +sr ← ZeroExtend32(SR); +fps ← ZeroExtend32(FPSCR); +op1 ← FloatValue64(DR2m); +op2 ← FloatValue64(DR2n); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +op2, fps ← FSUB_D(op2, op1, fps); +IF (FpuEnableV(fps) AND FpuCauseV(fps)) +THROW FPUEXC, fps; +IF (FpuCauseE(fps)) +THROW FPUEXC, fps; +IF ((FpuEnableI(fps) OR FpuEnableO(fps)) OR FpuEnableU(fps)) +THROW FPUEXC, fps; +DR2n ← FloatRegister64(op2); +FPSCR ← ZeroExtend32(fps); diff --git a/sh4/FSUB FRm,FRn b/sh4/FSUB FRm,FRn new file mode 100644 index 0000000..1dcf2a8 --- /dev/null +++ b/sh4/FSUB FRm,FRn @@ -0,0 +1,19 @@ +1111nnnnmmmm0001 +Available only when PR=0 +sr ← ZeroExtend32(SR); +fps ← ZeroExtend32(FPSCR); +op1 ← FloatValue32(FRm); +op2 ← FloatValue32(FRn); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +op2, fps ← FSUB_S(op2, op1, fps); +IF (FpuEnableV(fps) AND FpuCauseV(fps)) +THROW FPUEXC, fps; +IF (FpuCauseE(fps)) +THROW FPUEXC, fps; +IF ((FpuEnableI(fps) OR FpuEnableO(fps)) OR FpuEnableU(fps)) +THROW FPUEXC, fps; +FRn ← FloatRegister32(op2); +FPSCR ← ZeroExtend32(fps); diff --git a/sh4/FTRC DRm,FPUL b/sh4/FTRC DRm,FPUL new file mode 100644 index 0000000..c0ba35a --- /dev/null +++ b/sh4/FTRC DRm,FPUL @@ -0,0 +1,14 @@ +1111mmm000111101 +Available only when PR=1 and SZ=0 +sr ← ZeroExtend32(SR); +fps ← ZeroExtend32(FPSCR); +op1 ← FloatValue64(DR2m); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +fpul, fps ← FTRC_DL(op1, fps); +IF (FpuEnableV(fps) AND FpuCauseV(fps)) +THROW FPUEXC, fps; +FPUL ← ZeroExtend32(fpul); +FPSCR ← ZeroExtend32(fps); diff --git a/sh4/FTRC FRm,FPUL b/sh4/FTRC FRm,FPUL new file mode 100644 index 0000000..60963b4 --- /dev/null +++ b/sh4/FTRC FRm,FPUL @@ -0,0 +1,14 @@ +1111mmmm00111101 +Available only when PR=0 +sr ← ZeroExtend32(SR); +fps ← ZeroExtend32(FPSCR); +op1 ← FloatValue32(FRm); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +fpul, fps ← FTRC_SL(op1, fps); +IF (FpuEnableV(fps) AND FpuCauseV(fps)) +THROW FPUEXC, fps; +FPSCR ← ZeroExtend32(fps); +FPUL ← ZeroExtend32(fpul); diff --git a/sh4/FTRV XMTRX,FVn b/sh4/FTRV XMTRX,FVn new file mode 100644 index 0000000..68597c1 --- /dev/null +++ b/sh4/FTRV XMTRX,FVn @@ -0,0 +1,15 @@ +1111nn0111111101 +Available only when PR=0 +sr ← ZeroExtend32(SR); +fps ← ZeroExtend32(FPSCR); +xmtrx ← FloatValueMatrix32(XMTRX); +op1 ← FloatValueVector32(FV4n); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +op1, fps ← FTRV_S(xmtrx, op1, fps); +IF (((FpuEnableV(fps) OR FpuEnableI(fps)) OR FpuEnableO(fps)) OR FpuEnableU(fps)) +THROW FPUEXC, fps; +FV4n ← FloatRegisterVector32(op1); +FPSCR ← ZeroExtend32(fps); diff --git a/sh4/JMP @Rn b/sh4/JMP @Rn new file mode 100644 index 0000000..66666b4 --- /dev/null +++ b/sh4/JMP @Rn @@ -0,0 +1,7 @@ +0100nnnn00101011 +op1 ← SignExtend32(Rn); +IF (IsDelaySlot()) +THROW ILLSLOT; +target ← op1; +delayedpc ← target ∧ (~ 0x1); +PC’’ ← Register(delayedpc); diff --git a/sh4/JSR @Rn b/sh4/JSR @Rn new file mode 100644 index 0000000..4b5ee95 --- /dev/null +++ b/sh4/JSR @Rn @@ -0,0 +1,10 @@ +0100nnnn00001011 +pc ← SignExtend32(PC); +op1 ← SignExtend32(Rn); +IF (IsDelaySlot()) +THROW ILLSLOT; +delayedpr ← pc + 4; +target ← op1; +delayedpc ← target ∧ (~ 0x1); +PR’’ ← Register(delayedpr); +PC’’ ← Register(delayedpc); diff --git a/sh4/LDC Rm,DBR b/sh4/LDC Rm,DBR new file mode 100644 index 0000000..a712425 --- /dev/null +++ b/sh4/LDC Rm,DBR @@ -0,0 +1,7 @@ +0100mmmm11111010 +md ← ZeroExtend1(MD); +IF (md = 0) +THROW RESINST; +op1 ← SignExtend32(Rm); +dbr← op1; +DBR ← Register(dbr); diff --git a/sh4/LDC Rm,GBR b/sh4/LDC Rm,GBR new file mode 100644 index 0000000..de30287 --- /dev/null +++ b/sh4/LDC Rm,GBR @@ -0,0 +1,4 @@ +0100mmmm00011110 +op1 ← SignExtend32(Rm); +gbr ← op1; +GBR ← Register(gbr); diff --git a/sh4/LDC Rm,Rn_BANK b/sh4/LDC Rm,Rn_BANK new file mode 100644 index 0000000..1d5f320 --- /dev/null +++ b/sh4/LDC Rm,Rn_BANK @@ -0,0 +1,7 @@ +0100mmmm1nnn1110 +md ← ZeroExtend1(MD); +IF (md = 0) +THROW RESINST; +op1 ← SignExtend32(Rm); +rn_bank← op1; +Rn_BANK ← Register(rn_bank); diff --git a/sh4/LDC Rm,SPC b/sh4/LDC Rm,SPC new file mode 100644 index 0000000..692153c --- /dev/null +++ b/sh4/LDC Rm,SPC @@ -0,0 +1,7 @@ +0100mmmm01001110 +md ← ZeroExtend1(MD); +IF (md = 0) +THROW RESINST; +op1 ← SignExtend32(Rm); +spc ← op1; +SPC ← Register(spc); diff --git a/sh4/LDC Rm,SR b/sh4/LDC Rm,SR new file mode 100644 index 0000000..d7dcde9 --- /dev/null +++ b/sh4/LDC Rm,SR @@ -0,0 +1,7 @@ +0100mmmm00001110 +md ← ZeroExtend1(MD); +IF (md = 0) +THROW RESINST; +op1 ← SignExtend32(Rm); +sr ← op1; +SR ← Register(sr); diff --git a/sh4/LDC Rm,SSR b/sh4/LDC Rm,SSR new file mode 100644 index 0000000..7b53b8f --- /dev/null +++ b/sh4/LDC Rm,SSR @@ -0,0 +1,7 @@ +0100mmmm00111110 +md ← ZeroExtend1(MD); +IF (md = 0) +THROW RESINST; +op1 ← SignExtend32(Rm); +ssr ← op1; +SSR ← Register(ssr); diff --git a/sh4/LDC Rm,VBR b/sh4/LDC Rm,VBR new file mode 100644 index 0000000..472f1be --- /dev/null +++ b/sh4/LDC Rm,VBR @@ -0,0 +1,7 @@ +0100mmmm00101110 +md ← ZeroExtend1(MD); +IF (md = 0) +THROW RESINST; +op1 ← SignExtend32(Rm); +vbr← op1; +VBR ← Register(vbr); diff --git a/sh4/LDC.L @Rm+,DBR b/sh4/LDC.L @Rm+,DBR new file mode 100644 index 0000000..cc1e5cc --- /dev/null +++ b/sh4/LDC.L @Rm+,DBR @@ -0,0 +1,10 @@ +0100mmmm11110110 +md ← ZeroExtend1(MD); +IF (md = 0) +THROW RESINST; +op1 ← SignExtend32(Rm); +address ← ZeroExtend32(op1); +dbr ← SignExtend32(ReadMemory32(address)); +op1 ← op1 + 4; +Rm ← Register(op1); +DBR ← Register(dbr); diff --git a/sh4/LDC.L @Rm+,GBR b/sh4/LDC.L @Rm+,GBR new file mode 100644 index 0000000..5658375 --- /dev/null +++ b/sh4/LDC.L @Rm+,GBR @@ -0,0 +1,7 @@ +0100mmmm00010111 +op1 ← SignExtend32(Rm); +address ← ZeroExtend32(op1); +gbr ← SignExtend32(ReadMemory32(address)); +op1 ← op1 + 4; +Rm ← Register(op1); +GBR ← Register(gbr); diff --git a/sh4/LDC.L @Rm+,Rn_BANK b/sh4/LDC.L @Rm+,Rn_BANK new file mode 100644 index 0000000..06cbdd3 --- /dev/null +++ b/sh4/LDC.L @Rm+,Rn_BANK @@ -0,0 +1,10 @@ +0100mmmm1nnn0111 +md ← ZeroExtend1(MD); +IF (md = 0) +THROW RESINST; +op1 ← SignExtend32(Rm); +address ← ZeroExtend32(op1); +rn_bank ← SignExtend32(ReadMemory32(address)); +op1 ← op1 + 4; +Rm ← Register(op1); +Rn_BANK ← Register(rn_bank); diff --git a/sh4/LDC.L @Rm+,SPC b/sh4/LDC.L @Rm+,SPC new file mode 100644 index 0000000..7044aa6 --- /dev/null +++ b/sh4/LDC.L @Rm+,SPC @@ -0,0 +1,10 @@ +0100mmmm01000111 +md ← ZeroExtend1(MD); +IF (md = 0) +THROW RESINST; +op1 ← SignExtend32(Rm); +address ← ZeroExtend32(op1); +spc ← SignExtend32(ReadMemory32(address)); +op1 ← op1 + 4; +Rm ← Register(op1); +SPC ← Register(spc); diff --git a/sh4/LDC.L @Rm+,SR b/sh4/LDC.L @Rm+,SR new file mode 100644 index 0000000..86d754a --- /dev/null +++ b/sh4/LDC.L @Rm+,SR @@ -0,0 +1,10 @@ +0100mmmm00000111 +md ← ZeroExtend1(MD); +IF (md = 0) +THROW RESINST; +op1 ← SignExtend32(Rm); +address ← ZeroExtend32(op1); +sr ← SignExtend32(ReadMemory32(address)); +op1 ← op1 + 4; +Rm ← Register(op1); +SR ← Register(sr); diff --git a/sh4/LDC.L @Rm+,SSR b/sh4/LDC.L @Rm+,SSR new file mode 100644 index 0000000..4f352de --- /dev/null +++ b/sh4/LDC.L @Rm+,SSR @@ -0,0 +1,10 @@ +0100mmmm00110111 +md ← ZeroExtend1(MD); +IF (md = 0) +THROW RESINST; +op1 ← SignExtend32(Rm); +address ← ZeroExtend32(op1); +ssr ← SignExtend32(ReadMemory32(address)); +op1 ← op1 + 4; +Rm ← Register(op1); +SSR ← Register(ssr); diff --git a/sh4/LDC.L @Rm+,VBR b/sh4/LDC.L @Rm+,VBR new file mode 100644 index 0000000..bd4f07e --- /dev/null +++ b/sh4/LDC.L @Rm+,VBR @@ -0,0 +1,10 @@ +0100mmmm00100111 +md ← ZeroExtend1(MD); +IF (md = 0) +THROW RESINST; +op1 ← SignExtend32(Rm); +address ← ZeroExtend32(op1); +vbr ← SignExtend32(ReadMemory32(address)); +op1 ← op1 + 4; +Rm ← Register(op1); +VBR ← Register(vbr); diff --git a/sh4/LDS Rm,FPSCR b/sh4/LDS Rm,FPSCR new file mode 100644 index 0000000..a2bdd84 --- /dev/null +++ b/sh4/LDS Rm,FPSCR @@ -0,0 +1,12 @@ +0100mmmm01101010 +sr ← ZeroExtend32(SR); +op1 ← SignExtend32(Rm); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +fps, pr, sz, fr ← UnpackFPSCR(op1); +FPSCR ← ZeroExtend32(fps); +SR.PR ← Bit(pr); +SR.SZ ← Bit(sz); +SR.FR ← Bit(fr); diff --git a/sh4/LDS Rm,FPUL b/sh4/LDS Rm,FPUL new file mode 100644 index 0000000..b961124 --- /dev/null +++ b/sh4/LDS Rm,FPUL @@ -0,0 +1,9 @@ +0100mmmm01011010 +sr ← ZeroExtend32(SR); +op1 ← SignExtend32(Rm); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +fpul ← op1; +FPUL ← ZeroExtend32(fpul); diff --git a/sh4/LDS Rm,MACH b/sh4/LDS Rm,MACH new file mode 100644 index 0000000..6f816d4 --- /dev/null +++ b/sh4/LDS Rm,MACH @@ -0,0 +1,4 @@ +0100mmmm00001010 +op1 ← SignExtend32(Rm); +mach ← op1; +MACH ← ZeroExtend32(mach); diff --git a/sh4/LDS Rm,MACL b/sh4/LDS Rm,MACL new file mode 100644 index 0000000..449ecb6 --- /dev/null +++ b/sh4/LDS Rm,MACL @@ -0,0 +1,4 @@ +0100mmmm00011010 +op1 ← SignExtend32(Rm); +macl ← op1; +MACL ← ZeroExtend32(macl); diff --git a/sh4/LDS Rm,PR b/sh4/LDS Rm,PR new file mode 100644 index 0000000..82da703 --- /dev/null +++ b/sh4/LDS Rm,PR @@ -0,0 +1,6 @@ +0100mmmm00101010 +op1 ← SignExtend32(Rm); +newpr ← op1; +delayedpr ← newpr; +PR’ ← Register(newpr); +PR’’ ← Register(delayedpr); diff --git a/sh4/LDS.L @Rm+,FPSCR b/sh4/LDS.L @Rm+,FPSCR new file mode 100644 index 0000000..eee8dfe --- /dev/null +++ b/sh4/LDS.L @Rm+,FPSCR @@ -0,0 +1,16 @@ +0100mmmm01100110 +sr ← ZeroExtend32(SR); +op1 ← SignExtend32(Rm); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +address ← ZeroExtend32(op1); +value ← ReadMemory32(address); +fps, pr, sz, fr ← UnpackFPSCR(value); +op1 ← op1 + 4; +Rm ← Register(op1); +FPSCR ← ZeroExtend32(fps); +SR.PR ← Bit(pr); +SR.SZ ← Bit(sz); +SR.FR ← Bit(fr); diff --git a/sh4/LDS.L @Rm+,FPUL b/sh4/LDS.L @Rm+,FPUL new file mode 100644 index 0000000..2172d15 --- /dev/null +++ b/sh4/LDS.L @Rm+,FPUL @@ -0,0 +1,12 @@ +0100mmmm01010110 +sr ← ZeroExtend32(SR); +op1 ← SignExtend32(Rm); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +address ← ZeroExtend32(op1); +fpul ← ReadMemory32(address); +op1 ← op1 + 4; +Rm ← Register(op1); +FPUL ← ZeroExtend32(fpul); diff --git a/sh4/LDS.L @Rm+,MACH b/sh4/LDS.L @Rm+,MACH new file mode 100644 index 0000000..e6170fe --- /dev/null +++ b/sh4/LDS.L @Rm+,MACH @@ -0,0 +1,7 @@ +0100mmmm00000110 +op1 ← SignExtend32(Rm); +address ← ZeroExtend32(op1); +mach ← SignExtend32(ReadMemory32(address)); +op1 ← op1 + 4; +Rm ← Register(op1); +MACH ← ZeroExtend32(mach); diff --git a/sh4/LDS.L @Rm+,MACL b/sh4/LDS.L @Rm+,MACL new file mode 100644 index 0000000..2a1563d --- /dev/null +++ b/sh4/LDS.L @Rm+,MACL @@ -0,0 +1,7 @@ +0100mmmm00010110 +op1 ← SignExtend32(Rm); +address ← ZeroExtend32(op1); +macl ← SignExtend32(ReadMemory32(address)); +op1 ← op1 + 4; +Rm ← Register(op1); +MACL ← ZeroExtend32(macl); diff --git a/sh4/LDS.L @Rm+,PR b/sh4/LDS.L @Rm+,PR new file mode 100644 index 0000000..b4a983a --- /dev/null +++ b/sh4/LDS.L @Rm+,PR @@ -0,0 +1,9 @@ +0100mmmm00100110 +op1 ← SignExtend32(Rm); +address ← ZeroExtend32(op1); +newpr ← SignExtend32(ReadMemory32(address)); +delayedpr ← newpr; +op1 ← op1 + 4; +Rm ← Register(op1); +PR’ ← Register(newpr); +PR’’ ← Register(delayedpr); diff --git a/sh4/LDTLB b/sh4/LDTLB new file mode 100644 index 0000000..24e51a3 --- /dev/null +++ b/sh4/LDTLB @@ -0,0 +1,14 @@ +0000000000111000 +md ← ZeroExtend1(MD); +IF (md = 0) +THROW RESINST; +UTLB[MMUCR.URC].ASID ← PTEH.ASID +UTLB[MMUCR.URC].VPN ← PTEH.VPN +UTLB[MMUCR.URC].PPN ← PTEH.PPN +UTLB[MMUCR.URC].SZ ← PTEL.SZ1<<1 + PTEL.SZ0 +UTLB[MMUCR.URC].SH ← PTEL.SH +UTLB[MMUCR.URC].PR ← PTEL.PR +UTLB[MMUCR.URC].WT ← PTEL.WT +UTLB[MMUCR.URC].C ← PTEL.C +UTLB[MMUCR.URC].D ← PTEL.D +UTLB[MMUCR.URC].V ← PTEL.V diff --git a/sh4/MAC.L @Rm+,@Rn+ b/sh4/MAC.L @Rm+,@Rn+ new file mode 100644 index 0000000..3b3b4a0 --- /dev/null +++ b/sh4/MAC.L @Rm+,@Rn+ @@ -0,0 +1,33 @@ +0000nnnnmmmm1111 +macl ← ZeroExtend32(MACL); +mach ← ZeroExtend32(MACH); +s ← ZeroExtend1(S); +m_field ← ZeroExtend4(m); +n_field ← ZeroExtend4(n); +m_address ← SignExtend32(Rm); +n_address ← SignExtend32(Rn); +value2 ← SignExtend32(ReadMemory32(ZeroExtend32(n_address))); +n_address ← n_address + 4; +IF (n_field = m_field) +{ +m_address ← m_address + 4; +n_address ← n_address + 4; +} +value1 ← SignExtend32(ReadMemory32(ZeroExtend32(m_address))); +m_address ← m_address + 4; +mul ← value2 × value1; +mac ← (mach << 32) + macl; +result ← mac + mul; +IF (s = 1) +IF (((result ⊕ mac) ∧ (result ⊕ mul))< 63 FOR 1 > = 1) +IF (mac< 63 FOR 1 > = 0) +result ← 247 - 1; +ELSE +ELSEresult ← - 247; +result ← SignedSaturate48(result); +macl ← result; +mach ← result >> 32; +Rm ← Register(m_address); +Rn ← Register(n_address); +MACL ← ZeroExtend32(macl); +MACH ← ZeroExtend32(mach); diff --git a/sh4/MAC.W @Rm+,@Rn+ b/sh4/MAC.W @Rm+,@Rn+ new file mode 100644 index 0000000..0b62bfc --- /dev/null +++ b/sh4/MAC.W @Rm+,@Rn+ @@ -0,0 +1,35 @@ +0100nnnnmmmm1111 +macl ← ZeroExtend32(MACL); +mach ← ZeroExtend32(MACH); +s ← ZeroExtend1(S); +m_field ← ZeroExtend4(m); +n_field ← ZeroExtend4(n); +m_address ← SignExtend32(Rm); +n_address ← SignExtend32(Rn); +value2 ← SignExtend16(ReadMemory16(ZeroExtend32(n_address))); +n_address ← n_address + 2; +IF (n_field = m_field) +{ +m_address ← m_address + 2; +n_address ← n_address + 2; +} +value1 ← SignExtend16(ReadMemory16(ZeroExtend32(m_address))); +m_address ← m_address + 2; +mul ← value2 × value1; +IF (s = 1) +{ +macl ← SignExtend32(macl) + mul; +temp ← SignedSaturate32(macl); +IF (macl = temp) +result ← (mach << 32) ∨ ZeroExtend32(macl); +ELSE +result ← (0x1 << 32) ∨ ZeroExtend32(temp); +} +ELSE +result ← ((mach << 32) + macl) + mul; +macl ← result; +mach ← result >> 32; +Rm ← Register(m_address); +Rn ← Register(n_address); +MACL ← ZeroExtend32(macl); +MACH ← ZeroExtend32(mach); diff --git a/sh4/MOV #imm,Rn b/sh4/MOV #imm,Rn new file mode 100644 index 0000000..8ce62da --- /dev/null +++ b/sh4/MOV #imm,Rn @@ -0,0 +1,4 @@ +1110nnnniiiiiiii +imm ← SignExtend8(s); +op2 ← imm; +Rn ← Register(op2); diff --git a/sh4/MOV Rm,Rn b/sh4/MOV Rm,Rn new file mode 100644 index 0000000..7f1b416 --- /dev/null +++ b/sh4/MOV Rm,Rn @@ -0,0 +1,4 @@ +0110nnnnmmmm0011 +op1 ← ZeroExtend32(Rm); +op2 ← op1; +Rn ← Register(op2); diff --git a/sh4/MOV.B @(R0,Rm),Rn b/sh4/MOV.B @(R0,Rm),Rn new file mode 100644 index 0000000..18ac481 --- /dev/null +++ b/sh4/MOV.B @(R0,Rm),Rn @@ -0,0 +1,6 @@ +0000nnnnmmmm1100 +r0 ← SignExtend32(R0); +op1 ← SignExtend32(Rm); +address ← ZeroExtend32(r0 + op1); +op2 ← SignExtend8(ReadMemory8(address)); +Rn ← Register(op2); diff --git a/sh4/MOV.B @(disp,GBR),R0 b/sh4/MOV.B @(disp,GBR),R0 new file mode 100644 index 0000000..1c48af5 --- /dev/null +++ b/sh4/MOV.B @(disp,GBR),R0 @@ -0,0 +1,6 @@ +11000100dddddddd +gbr ← SignExtend32(GBR); +disp ← ZeroExtend8(i); +address ← ZeroExtend32(disp + gbr); +r0 ← SignExtend8(ReadMemory8(address)); +R0 ← Register(r0); diff --git a/sh4/MOV.B @(disp,Rm),R0 b/sh4/MOV.B @(disp,Rm),R0 new file mode 100644 index 0000000..fb8a2c9 --- /dev/null +++ b/sh4/MOV.B @(disp,Rm),R0 @@ -0,0 +1,6 @@ +10000100mmmmdddd +disp ← ZeroExtend4(i); +op2 ← SignExtend32(Rm); +address ← ZeroExtend32(disp + op2); +r0 ← SignExtend8(ReadMemory8(address)); +R0 ← Register(r0); diff --git a/sh4/MOV.B @Rm+,Rn b/sh4/MOV.B @Rm+,Rn new file mode 100644 index 0000000..36aef8a --- /dev/null +++ b/sh4/MOV.B @Rm+,Rn @@ -0,0 +1,12 @@ +0110nnnnmmmm0100 +m_field ← ZeroExtend4(m); +n_field ← ZeroExtend4(n); +op1 ← SignExtend32(Rm); +address ← ZeroExtend32(op1); +op2 ← SignExtend8(ReadMemory8(address)); +IF (m_field = n_field) +op1 ← op2; +ELSE +op1 ← op1 + 1; +Rm ← Register(op1); +Rn ← Register(op2); diff --git a/sh4/MOV.B @Rm,Rn b/sh4/MOV.B @Rm,Rn new file mode 100644 index 0000000..777ce37 --- /dev/null +++ b/sh4/MOV.B @Rm,Rn @@ -0,0 +1,5 @@ +0110nnnnmmmm0000 +op1 ← SignExtend32(Rm); +address ← ZeroExtend32(op1); +op2 ← SignExtend8(ReadMemory8(address)); +Rn ← Register(op2); diff --git a/sh4/MOV.B R0,@(disp,GBR) b/sh4/MOV.B R0,@(disp,GBR) new file mode 100644 index 0000000..c252085 --- /dev/null +++ b/sh4/MOV.B R0,@(disp,GBR) @@ -0,0 +1,6 @@ +11000000dddddddd +gbr ← SignExtend32(GBR); +r0 ← SignExtend32(R0); +disp ← ZeroExtend8(i); +address ← ZeroExtend32(disp + gbr); +WriteMemory8(address, r0); diff --git a/sh4/MOV.B R0,@(disp,Rn) b/sh4/MOV.B R0,@(disp,Rn) new file mode 100644 index 0000000..1f0267f --- /dev/null +++ b/sh4/MOV.B R0,@(disp,Rn) @@ -0,0 +1,6 @@ +10000000nnnndddd +r0 ← SignExtend32(R0); +disp ← ZeroExtend4(i); +op2 ← SignExtend32(Rn); +address ← ZeroExtend32(disp + op2); +WriteMemory8(address, r0); diff --git a/sh4/MOV.B Rm,@(R0,Rn) b/sh4/MOV.B Rm,@(R0,Rn) new file mode 100644 index 0000000..388e6a4 --- /dev/null +++ b/sh4/MOV.B Rm,@(R0,Rn) @@ -0,0 +1,6 @@ +0000nnnnmmmm0100 +r0 ← SignExtend32(R0); +op1 ← SignExtend32(Rm); +op2 ← SignExtend32(Rn); +address ← ZeroExtend32(r0 + op2); +WriteMemory8(address, op1); diff --git a/sh4/MOV.B Rm,@-Rn b/sh4/MOV.B Rm,@-Rn new file mode 100644 index 0000000..40d9410 --- /dev/null +++ b/sh4/MOV.B Rm,@-Rn @@ -0,0 +1,7 @@ +0010nnnnmmmm0100 +op1 ← SignExtend32(Rm); +op2 ← SignExtend32(Rn); +address ← ZeroExtend32(op2 - 1); +WriteMemory8(address, op1); +op2 ← address; +Rn ← Register(op2); diff --git a/sh4/MOV.B Rm,@Rn b/sh4/MOV.B Rm,@Rn new file mode 100644 index 0000000..58d822b --- /dev/null +++ b/sh4/MOV.B Rm,@Rn @@ -0,0 +1,5 @@ +0010nnnnmmmm0000 +op1 ← SignExtend32(Rm); +op2 ← SignExtend32(Rn); +address ← ZeroExtend32(op2); +WriteMemory8(address, op1); diff --git a/sh4/MOV.L @(R0,Rm),Rn b/sh4/MOV.L @(R0,Rm),Rn new file mode 100644 index 0000000..057325c --- /dev/null +++ b/sh4/MOV.L @(R0,Rm),Rn @@ -0,0 +1,6 @@ +0000nnnnmmmm1110 +r0 ← SignExtend32(R0); +op1 ← SignExtend32(Rm); +address ← ZeroExtend32(r0 + op1); +op2 ← SignExtend32(ReadMemory32(address)); +Rn ← Register(op2); diff --git a/sh4/MOV.L @(disp,GBR),R0 b/sh4/MOV.L @(disp,GBR),R0 new file mode 100644 index 0000000..5ea21cd --- /dev/null +++ b/sh4/MOV.L @(disp,GBR),R0 @@ -0,0 +1,6 @@ +11000110dddddddd +gbr ← SignExtend32(GBR); +disp ← ZeroExtend8(i) << 2; +address ← ZeroExtend32(disp + gbr); +r0 ← SignExtend32(ReadMemory32(address)); +R0 ← Register(r0); diff --git a/sh4/MOV.L @(disp,PC),Rn b/sh4/MOV.L @(disp,PC),Rn new file mode 100644 index 0000000..c8038c1 --- /dev/null +++ b/sh4/MOV.L @(disp,PC),Rn @@ -0,0 +1,8 @@ +1101nnnndddddddd +pc ← SignExtend32(PC); +disp ← ZeroExtend8(i) << 2; +IF (IsDelaySlot()) +THROW ILLSLOT; +address ← ZeroExtend32(disp + ((pc + 4) ∧ (~ 0x3))); +op2 ← SignExtend32(ReadMemory32(address)); +Rn ← Register(op2); diff --git a/sh4/MOV.L @(disp,Rm),Rn b/sh4/MOV.L @(disp,Rm),Rn new file mode 100644 index 0000000..5713ba0 --- /dev/null +++ b/sh4/MOV.L @(disp,Rm),Rn @@ -0,0 +1,6 @@ +0101nnnnmmmmdddd +disp ← ZeroExtend4(i) << 2; +op2 ← SignExtend32(Rm); +address ← ZeroExtend32(disp + op2); +op3 ← SignExtend32(ReadMemory32(address)); +Rn ← Register(op3); diff --git a/sh4/MOV.L @Rm+,Rn b/sh4/MOV.L @Rm+,Rn new file mode 100644 index 0000000..0ad7cac --- /dev/null +++ b/sh4/MOV.L @Rm+,Rn @@ -0,0 +1,12 @@ +0110nnnnmmmm0110 +m_field ← ZeroExtend4(m); +n_field ← ZeroExtend4(n); +op1 ← SignExtend32(Rm); +address ← ZeroExtend32(op1); +op2 ← SignExtend32(ReadMemory32(address)); +IF (m_field = n_field) +op1 ← op2; +ELSE +op1 ← op1 + 4; +Rm ← Register(op1); +Rn ← Register(op2); diff --git a/sh4/MOV.L @Rm,Rn b/sh4/MOV.L @Rm,Rn new file mode 100644 index 0000000..6a9fe8f --- /dev/null +++ b/sh4/MOV.L @Rm,Rn @@ -0,0 +1,5 @@ +0110nnnnmmmm0010 +op1 ← SignExtend32(Rm); +address ← ZeroExtend32(op1); +op2 ← SignExtend32(ReadMemory32(address)); +Rn ← Register(op2); diff --git a/sh4/MOV.L R0,@(disp,GBR) b/sh4/MOV.L R0,@(disp,GBR) new file mode 100644 index 0000000..1059389 --- /dev/null +++ b/sh4/MOV.L R0,@(disp,GBR) @@ -0,0 +1,6 @@ +11000010dddddddd +gbr ← SignExtend32(GBR); +r0 ← SignExtend32(R0); +disp ← ZeroExtend8(i) << 2; +address ← ZeroExtend32(disp + gbr); +WriteMemory32(address, r0); diff --git a/sh4/MOV.L Rm,@(R0,Rn) b/sh4/MOV.L Rm,@(R0,Rn) new file mode 100644 index 0000000..7ce3f4d --- /dev/null +++ b/sh4/MOV.L Rm,@(R0,Rn) @@ -0,0 +1,6 @@ +0000nnnnmmmm0110 +r0 ← SignExtend32(R0); +op1 ← SignExtend32(Rm); +op2 ← SignExtend32(Rn); +address ← ZeroExtend32(r0 + op2); +WriteMemory32(address, op1); diff --git a/sh4/MOV.L Rm,@(disp,Rn) b/sh4/MOV.L Rm,@(disp,Rn) new file mode 100644 index 0000000..3005a39 --- /dev/null +++ b/sh4/MOV.L Rm,@(disp,Rn) @@ -0,0 +1,6 @@ +0001nnnnmmmmdddd +op1 ← SignExtend32(Rm); +disp ← ZeroExtend4(i) << 2; +op3 ← SignExtend32(Rn); +address ← ZeroExtend32(disp + op3); +WriteMemory32(address, op1); diff --git a/sh4/MOV.L Rm,@-Rn b/sh4/MOV.L Rm,@-Rn new file mode 100644 index 0000000..a239590 --- /dev/null +++ b/sh4/MOV.L Rm,@-Rn @@ -0,0 +1,7 @@ +0010nnnnmmmm0110 +op1 ← SignExtend32(Rm); +op2 ← SignExtend32(Rn); +address ← ZeroExtend32(op2 - 4); +WriteMemory32(address, op1); +op2 ← address; +Rn ← Register(op2); diff --git a/sh4/MOV.L Rm,@Rn b/sh4/MOV.L Rm,@Rn new file mode 100644 index 0000000..01ad44d --- /dev/null +++ b/sh4/MOV.L Rm,@Rn @@ -0,0 +1,5 @@ +0010nnnnmmmm0010 +op1 ← SignExtend32(Rm); +op2 ← SignExtend32(Rn); +address ← ZeroExtend32(op2); +WriteMemory32(address, op1); diff --git a/sh4/MOV.W @(R0,Rm),Rn b/sh4/MOV.W @(R0,Rm),Rn new file mode 100644 index 0000000..b697cf4 --- /dev/null +++ b/sh4/MOV.W @(R0,Rm),Rn @@ -0,0 +1,6 @@ +0000nnnnmmmm1101 +r0 ← SignExtend32(R0); +op1 ← SignExtend32(Rm); +address ← ZeroExtend32(r0 + op1); +op2 ← SignExtend16(ReadMemory16(address)); +Rn ← Register(op2); diff --git a/sh4/MOV.W @(disp,GBR),R0 b/sh4/MOV.W @(disp,GBR),R0 new file mode 100644 index 0000000..d67c155 --- /dev/null +++ b/sh4/MOV.W @(disp,GBR),R0 @@ -0,0 +1,6 @@ +11000101dddddddd +gbr ← SignExtend32(GBR); +disp ← ZeroExtend8(i) << 1; +address ← ZeroExtend32(disp + gbr); +r0 ← SignExtend16(ReadMemory16(address)); +R0 ← Register(r0); diff --git a/sh4/MOV.W @(disp,PC),Rn b/sh4/MOV.W @(disp,PC),Rn new file mode 100644 index 0000000..947f7cd --- /dev/null +++ b/sh4/MOV.W @(disp,PC),Rn @@ -0,0 +1,8 @@ +1001nnnndddddddd +pc ← SignExtend32(PC); +disp ← ZeroExtend8(i) << 1; +IF (IsDelaySlot()) +THROW ILLSLOT; +address ← ZeroExtend32(disp + (pc + 4)); +op2 ← SignExtend16(ReadMemory16(address)); +Rn ← Register(op2); diff --git a/sh4/MOV.W @(disp,Rm),R0 b/sh4/MOV.W @(disp,Rm),R0 new file mode 100644 index 0000000..e1b9016 --- /dev/null +++ b/sh4/MOV.W @(disp,Rm),R0 @@ -0,0 +1,6 @@ +10000101mmmmdddd +disp ← ZeroExtend4(i) << 1; +op2 ← SignExtend32(Rm); +address ← ZeroExtend32(disp + op2); +r0 ← SignExtend16(ReadMemory16(address)); +R0 ← Register(r0); diff --git a/sh4/MOV.W @Rm+,Rn b/sh4/MOV.W @Rm+,Rn new file mode 100644 index 0000000..daee2fa --- /dev/null +++ b/sh4/MOV.W @Rm+,Rn @@ -0,0 +1,12 @@ +0110nnnnmmmm0101 +m_field ← ZeroExtend4(m); +n_field ← ZeroExtend4(n); +op1 ← SignExtend32(Rm); +address ← ZeroExtend32(op1); +op2 ← SignExtend16(ReadMemory16(address)); +IF (m_field = n_field) +op1 ← op2; +ELSE +op1 ← op1 + 2; +Rm ← Register(op1); +Rn ← Register(op2); diff --git a/sh4/MOV.W @Rm,Rn b/sh4/MOV.W @Rm,Rn new file mode 100644 index 0000000..abd187e --- /dev/null +++ b/sh4/MOV.W @Rm,Rn @@ -0,0 +1,5 @@ +0110nnnnmmmm0001 +op1 ← SignExtend32(Rm); +address ← ZeroExtend32(op1); +op2 ← SignExtend16(ReadMemory16(address)); +Rn ← Register(op2); diff --git a/sh4/MOV.W R0,@(disp,GBR) b/sh4/MOV.W R0,@(disp,GBR) new file mode 100644 index 0000000..fca1bad --- /dev/null +++ b/sh4/MOV.W R0,@(disp,GBR) @@ -0,0 +1,6 @@ +11000001dddddddd +gbr ← SignExtend32(GBR); +r0 ← SignExtend32(R0); +disp ← ZeroExtend8(i) << 1; +address ← ZeroExtend32(disp + gbr); +WriteMemory16(address, r0); diff --git a/sh4/MOV.W R0,@(disp,Rn) b/sh4/MOV.W R0,@(disp,Rn) new file mode 100644 index 0000000..7cb74e7 --- /dev/null +++ b/sh4/MOV.W R0,@(disp,Rn) @@ -0,0 +1,6 @@ +10000001nnnndddd +r0 ← SignExtend32(R0); +disp ← ZeroExtend4(i) << 1; +op2 ← SignExtend32(Rn); +address ← ZeroExtend32(disp + op2); +WriteMemory16(address, r0); diff --git a/sh4/MOV.W Rm,@(R0,Rn) b/sh4/MOV.W Rm,@(R0,Rn) new file mode 100644 index 0000000..d7a1fc8 --- /dev/null +++ b/sh4/MOV.W Rm,@(R0,Rn) @@ -0,0 +1,6 @@ +0000nnnnmmmm0101 +r0 ← SignExtend32(R0); +op1 ← SignExtend32(Rm); +op2 ← SignExtend32(Rn); +address ← ZeroExtend32(r0 + op2); +WriteMemory16(address, op1); diff --git a/sh4/MOV.W Rm,@-Rn b/sh4/MOV.W Rm,@-Rn new file mode 100644 index 0000000..283be7f --- /dev/null +++ b/sh4/MOV.W Rm,@-Rn @@ -0,0 +1,7 @@ +0010nnnnmmmm0101 +op1 ← SignExtend32(Rm); +op2 ← SignExtend32(Rn); +address ← ZeroExtend32(op2 - 2); +WriteMemory16(address, op1); +op2 ← address; +Rn ← Register(op2); diff --git a/sh4/MOV.W Rm,@Rn b/sh4/MOV.W Rm,@Rn new file mode 100644 index 0000000..2d81b26 --- /dev/null +++ b/sh4/MOV.W Rm,@Rn @@ -0,0 +1,5 @@ +0010nnnnmmmm0001 +op1 ← SignExtend32(Rm); +op2 ← SignExtend32(Rn); +address ← ZeroExtend32(op2); +WriteMemory16(address, op1); diff --git a/sh4/MOVA @(disp,PC),R0 b/sh4/MOVA @(disp,PC),R0 new file mode 100644 index 0000000..4b56df8 --- /dev/null +++ b/sh4/MOVA @(disp,PC),R0 @@ -0,0 +1,7 @@ +11000111dddddddd +pc ← SignExtend32(PC); +disp ← ZeroExtend8(i) << 2; +IF (IsDelaySlot()) +THROW ILLSLOT; +r0 ← disp + ((pc + 4) ∧ (~ 0x3)); +R0 ← Register(r0); diff --git a/sh4/MOVCA.L R0,@Rn b/sh4/MOVCA.L R0,@Rn new file mode 100644 index 0000000..26a669e --- /dev/null +++ b/sh4/MOVCA.L R0,@Rn @@ -0,0 +1,14 @@ +0000nnnn11000011 +r0 ← SignExtend32(R0); +op1 ← SignExtend32(Rn); +IF (AddressUnavailable(op1)) +THROW WADDERR, op1; +IF (MMU() AND DataAccessMiss(op1)) +THROW WTLBMISS, op1; +IF (MMU() AND WriteProhibited(op1)) +THROW WRITEPROT, op1; +IF (MMU() AND NOT DirtyBit(op1)) +THROW FIRSTWRITE, op1 +ALLOCO(op1); +address ← ZeroExtend32(op1); +WriteMemory32(op1, r0); diff --git a/sh4/MOVT Rn b/sh4/MOVT Rn new file mode 100644 index 0000000..abccecd --- /dev/null +++ b/sh4/MOVT Rn @@ -0,0 +1,4 @@ +0000nnnn00101001 +t ← ZeroExtend1(T); +op1 ← t; +Rn ← Register(op1); diff --git a/sh4/MUL.L Rm,Rn b/sh4/MUL.L Rm,Rn new file mode 100644 index 0000000..a7a9700 --- /dev/null +++ b/sh4/MUL.L Rm,Rn @@ -0,0 +1,5 @@ +0000nnnnmmmm0111 +op1 ← SignExtend32(Rm); +op2 ← SignExtend32(Rn); +macl ← op1 × op2; +MACL ← ZeroExtend32(macl); diff --git a/sh4/MULS.W Rm,Rn b/sh4/MULS.W Rm,Rn new file mode 100644 index 0000000..b81d979 --- /dev/null +++ b/sh4/MULS.W Rm,Rn @@ -0,0 +1,5 @@ +0010nnnnmmmm1111 +op1 ← SignExtend16(SignExtend32(Rm)); +op2 ← SignExtend16(SignExtend32(Rn)); +macl ← op1 × op2; +MACL ← ZeroExtend32(macl); diff --git a/sh4/MULU.W Rm,Rn b/sh4/MULU.W Rm,Rn new file mode 100644 index 0000000..86bff8f --- /dev/null +++ b/sh4/MULU.W Rm,Rn @@ -0,0 +1,5 @@ +0010nnnnmmmm1110 +op1 ← ZeroExtend16(SignExtend32(Rm)); +op2 ← ZeroExtend16(SignExtend32(Rn)); +macl ← op1 × op2; +MACL ← ZeroExtend32(macl); diff --git a/sh4/NEG Rm,Rn b/sh4/NEG Rm,Rn new file mode 100644 index 0000000..e370084 --- /dev/null +++ b/sh4/NEG Rm,Rn @@ -0,0 +1,4 @@ +0110nnnnmmmm1011 +op1 ← SignExtend32(Rm); +op2 ← - op1; +Rn ← Register(op2); diff --git a/sh4/NEGC Rm,Rn b/sh4/NEGC Rm,Rn new file mode 100644 index 0000000..00d7c3f --- /dev/null +++ b/sh4/NEGC Rm,Rn @@ -0,0 +1,7 @@ +0110nnnnmmmm1010 +t ← ZeroExtend1(T); +op1 ← ZeroExtend32(Rm); +op2 ← (- op1) - t; +t ← op2< 32 FOR 1 >; +Rn ← Register(op2); +T ← Bit(t); diff --git a/sh4/NOP b/sh4/NOP new file mode 100644 index 0000000..5ea6cad --- /dev/null +++ b/sh4/NOP @@ -0,0 +1,2 @@ +0000000000001001 +NOP diff --git a/sh4/NOT Rm,Rn b/sh4/NOT Rm,Rn new file mode 100644 index 0000000..53982f2 --- /dev/null +++ b/sh4/NOT Rm,Rn @@ -0,0 +1,4 @@ +0110nnnnmmmm0111 +op1 ← ZeroExtend32(Rm); +op2 ← ~ op1; +Rn ← Register(op2); diff --git a/sh4/OCBI @Rn b/sh4/OCBI @Rn new file mode 100644 index 0000000..e576219 --- /dev/null +++ b/sh4/OCBI @Rn @@ -0,0 +1,11 @@ +0000nnnn10010011 +op1 ← SignExtend32(Rn); +IF (AddressUnavailable(op1)) +THROW WADDERR, op1; +IF (MMU() AND DataAccessMiss(op1)) +THROW WTLBMISS, op1; +IF (MMU() AND WriteProhibited(op1)) +THROW WRITEPROT, op1; +IF (MMU() AND NOT DirtyBit(op1)) +THROW FIRSTWRITE, op1 +OCBI(op1); diff --git a/sh4/OCBP @Rn b/sh4/OCBP @Rn new file mode 100644 index 0000000..4682c49 --- /dev/null +++ b/sh4/OCBP @Rn @@ -0,0 +1,9 @@ +0000nnnn10100011 +op1 ← SignExtend32(Rn); +IF (AddressUnavailable(op1)) +THROW RADDERR, op1; +IF (MMU() AND DataAccessMiss(op1)) +THROW RTLBMISS, op1; +IF (MMU() AND (ReadProhibited(op1) AND WriteProhibited(op1))) +THROW READPROT, op1; +OCBP(op1); diff --git a/sh4/OCBWB @Rn b/sh4/OCBWB @Rn new file mode 100644 index 0000000..b8c157d --- /dev/null +++ b/sh4/OCBWB @Rn @@ -0,0 +1,9 @@ +0000nnnn10110011 +op1 ← SignExtend32(Rn); +IF (AddressUnavailable(op1)) +THROW RADDERR, op1; +IF (MMU() AND DataAccessMiss(op1)) +THROW RTLBMISS, op1; +IF (MMU() AND (ReadProhibited(op1) AND WriteProhibited(op1))) +THROW READPROT, op1; +OCBWB(op1); diff --git a/sh4/OR #imm,R0 b/sh4/OR #imm,R0 new file mode 100644 index 0000000..6320620 --- /dev/null +++ b/sh4/OR #imm,R0 @@ -0,0 +1,5 @@ +11001011iiiiiiii +r0 ← ZeroExtend32(R0); +imm ← ZeroExtend8(i); +r0 ← r0 ∨ imm; +R0 ← Register(r0); diff --git a/sh4/OR Rm,Rn b/sh4/OR Rm,Rn new file mode 100644 index 0000000..8076576 --- /dev/null +++ b/sh4/OR Rm,Rn @@ -0,0 +1,5 @@ +0010nnnnmmmm1011 +op1 ← ZeroExtend32(Rm); +op2 ← ZeroExtend32(Rn); +op2 ← op2 ∨ op1; +Rn ← Register(op2); diff --git a/sh4/OR.B #imm,@(R0,GBR) b/sh4/OR.B #imm,@(R0,GBR) new file mode 100644 index 0000000..8b09322 --- /dev/null +++ b/sh4/OR.B #imm,@(R0,GBR) @@ -0,0 +1,8 @@ +11001111iiiiiiii +r0 ← SignExtend32(R0); +gbr ← SignExtend32(GBR); +imm ← ZeroExtend8(i); +address ← ZeroExtend32(r0 + gbr); +value ← ZeroExtend8(ReadMemory8(address)); +value ← value ∨ imm; +WriteMemory8(address, value); diff --git a/sh4/PREF @Rn b/sh4/PREF @Rn new file mode 100644 index 0000000..ff0a131 --- /dev/null +++ b/sh4/PREF @Rn @@ -0,0 +1,7 @@ +0000nnnn10000011 +op1 ← SignExtend32(Rn); +IF (AddressUnavailable(op1)) +THROW RADDERR, op1 +IF (NOT (MMU() AND DataAccessMiss(op1))) +IF (NOT (MMU() AND ReadProhibited(op1))) +PREF(op1); diff --git a/sh4/ROTCL Rn b/sh4/ROTCL Rn new file mode 100644 index 0000000..f33b19a --- /dev/null +++ b/sh4/ROTCL Rn @@ -0,0 +1,7 @@ +0100nnnn00100100 +t ← ZeroExtend1(T); +op1 ← ZeroExtend32(Rn); +op1 ← (op1 << 1) ∨ t; +t ← op1< 32 FOR 1 >; +Rn ← Register(op1); +T ← Bit(t); diff --git a/sh4/ROTCR Rn b/sh4/ROTCR Rn new file mode 100644 index 0000000..5280d08 --- /dev/null +++ b/sh4/ROTCR Rn @@ -0,0 +1,8 @@ +0100nnnn00100101 +t ← ZeroExtend1(T); +op1 ← ZeroExtend32(Rn); +oldt ← t; +t ← op1< 0 FOR 1 >; +op1 ← (op1 >> 1) ∨ (oldt << 31); +Rn ← Register(op1); +T ← Bit(t); diff --git a/sh4/ROTL Rn b/sh4/ROTL Rn new file mode 100644 index 0000000..d83d47e --- /dev/null +++ b/sh4/ROTL Rn @@ -0,0 +1,6 @@ +0100nnnn00000100 +op1 ← ZeroExtend32(Rn); +t ← op1< 31 FOR 1 >; +op1 ← (op1 << 1) ∨ t; +Rn ← Register(op1); +T ← Bit(t); diff --git a/sh4/ROTR Rn b/sh4/ROTR Rn new file mode 100644 index 0000000..7c2c7a6 --- /dev/null +++ b/sh4/ROTR Rn @@ -0,0 +1,6 @@ +0100nnnn00000101 +op1 ← ZeroExtend32(Rn); +t ← op1< 0 FOR 1 >; +op1 ← (op1 >> 1) ∨ (t << 31); +Rn ← Register(op1); +T ← Bit(t); diff --git a/sh4/RTE b/sh4/RTE new file mode 100644 index 0000000..8c3a2b3 --- /dev/null +++ b/sh4/RTE @@ -0,0 +1,11 @@ +0000000000101011 +md ← ZeroExtend1(MD); +IF (md = 0) +THROW RESINST; +ssr ← SignExtend32(SSR); +pc ← SignExtend32(PC) +IF (IsDelaySlot()) +THROW ILLSLOT; +target ← pc; +delayedpc ← target ∧ (~ 0x1); +PC’’ ← Register(delayedpc); diff --git a/sh4/RTS b/sh4/RTS new file mode 100644 index 0000000..8721ed7 --- /dev/null +++ b/sh4/RTS @@ -0,0 +1,7 @@ +0000000000001011 +pr ← SignExtend32(PR); +IF (IsDelaySlot()) +THROW ILLSLOT; +target ← pr; +delayedpc ← target ∧ (~ 0x1); +PC’’ ← Register(delayedpc); diff --git a/sh4/SETS b/sh4/SETS new file mode 100644 index 0000000..18f4a06 --- /dev/null +++ b/sh4/SETS @@ -0,0 +1,3 @@ +0000000001011000 +s ← 1; +S ← Bit(s); diff --git a/sh4/SETT b/sh4/SETT new file mode 100644 index 0000000..76ceb1d --- /dev/null +++ b/sh4/SETT @@ -0,0 +1,3 @@ +0000000000011000 +t ← 1; +T ← Bit(t); diff --git a/sh4/SHAD Rm,Rn b/sh4/SHAD Rm,Rn new file mode 100644 index 0000000..7de8240 --- /dev/null +++ b/sh4/SHAD Rm,Rn @@ -0,0 +1,13 @@ +0100nnnnmmmm1100 +op1 ← SignExtend32(Rm); +op2 ← SignExtend32(Rn); +shift_amount ← ZeroExtend5(op1); +IF (op1 ≥ 0) +op2 ← op2 << shift_amount; +ELSE IF (shift_amount ≠ 0) +op2 ← op2 >> (32 - shift_amount); +ELSE IF (op2 < 0) +op2 ← - 1; +ELSE +op2 ← 0; +Rn ← Register(op2); diff --git a/sh4/SHAL Rn b/sh4/SHAL Rn new file mode 100644 index 0000000..62f9109 --- /dev/null +++ b/sh4/SHAL Rn @@ -0,0 +1,6 @@ +0100nnnn00100000 +op1 ← SignExtend32(Rn); +t ← op1< 31 FOR 1 >; +op1 ← op1 << 1; +Rn ← Register(op1); +T ← Bit(t); diff --git a/sh4/SHAR Rn b/sh4/SHAR Rn new file mode 100644 index 0000000..b7e4e1c --- /dev/null +++ b/sh4/SHAR Rn @@ -0,0 +1,6 @@ +0100nnnn00100001 +op1 ← SignExtend32(Rn); +t ← op1< 0 FOR 1 >; +op1 ← op1 >> 1; +Rn ← Register(op1); +T ← Bit(t); diff --git a/sh4/SHLD Rm,Rn b/sh4/SHLD Rm,Rn new file mode 100644 index 0000000..0fd6dff --- /dev/null +++ b/sh4/SHLD Rm,Rn @@ -0,0 +1,11 @@ +0100nnnnmmmm1101 +op1 ← SignExtend32(Rm); +op2 ← ZeroExtend32(Rn); +shift_amount ← ZeroExtend5(op1); +IF (op1 ≥ 0) +op2 ← op2 << shift_amount; +ELSE IF (shift_amount ≠ 0) +op2 ← op2 >> (32 - shift_amount); +ELSE +op2 ← 0; +Rn ← Register(op2); diff --git a/sh4/SHLL Rn b/sh4/SHLL Rn new file mode 100644 index 0000000..b4c5b6b --- /dev/null +++ b/sh4/SHLL Rn @@ -0,0 +1,6 @@ +0100nnnn00000000 +op1 ← ZeroExtend32(Rn); +t ← op1< 31 FOR 1 >; +op1 ← op1 << 1; +Rn ← Register(op1); +T ← Bit(t); diff --git a/sh4/SHLL16 Rn b/sh4/SHLL16 Rn new file mode 100644 index 0000000..fa2bebd --- /dev/null +++ b/sh4/SHLL16 Rn @@ -0,0 +1,4 @@ +0100nnnn00101000 +op1 ← ZeroExtend32(Rn); +op1 ← op1 << 16; +Rn ← Register(op1); diff --git a/sh4/SHLL2 Rn b/sh4/SHLL2 Rn new file mode 100644 index 0000000..64b9e0d --- /dev/null +++ b/sh4/SHLL2 Rn @@ -0,0 +1,4 @@ +0100nnnn00001000 +op1 ← ZeroExtend32(Rn); +op1 ← op1 << 2; +Rn ← Register(op1); diff --git a/sh4/SHLL8 Rn b/sh4/SHLL8 Rn new file mode 100644 index 0000000..8aa9bba --- /dev/null +++ b/sh4/SHLL8 Rn @@ -0,0 +1,4 @@ +0100nnnn00011000 +op1 ← ZeroExtend32(Rn); +op1 ← op1 << 8; +Rn ← Register(op1); diff --git a/sh4/SHLR Rn b/sh4/SHLR Rn new file mode 100644 index 0000000..1a0c8fe --- /dev/null +++ b/sh4/SHLR Rn @@ -0,0 +1,6 @@ +0100nnnn00000001 +op1 ← ZeroExtend32(Rn); +t ← op1< 0 FOR 1 >; +op1 ← op1 >> 1; +Rn ← Register(op1); +T ← Bit(t); diff --git a/sh4/SHLR16 Rn b/sh4/SHLR16 Rn new file mode 100644 index 0000000..9920d08 --- /dev/null +++ b/sh4/SHLR16 Rn @@ -0,0 +1,4 @@ +0100nnnn00101001 +op1 ← ZeroExtend32(Rn); +op1 ← op1 >> 16; +Rn ← Register(op1); diff --git a/sh4/SHLR2 Rn b/sh4/SHLR2 Rn new file mode 100644 index 0000000..93b5fcf --- /dev/null +++ b/sh4/SHLR2 Rn @@ -0,0 +1,4 @@ +0100nnnn00001001 +op1 ← ZeroExtend32(Rn); +op1 ← op1 >> 2; +Rn ← Register(op1); diff --git a/sh4/SHLR8 Rn b/sh4/SHLR8 Rn new file mode 100644 index 0000000..94556ce --- /dev/null +++ b/sh4/SHLR8 Rn @@ -0,0 +1,4 @@ +0100nnnn00011001 +op1 ← ZeroExtend32(Rn); +op1 ← op1 >> 8; +Rn ← Register(op1); diff --git a/sh4/SLEEP b/sh4/SLEEP new file mode 100644 index 0000000..a22624c --- /dev/null +++ b/sh4/SLEEP @@ -0,0 +1,5 @@ +0000000000011011 +md ← ZeroExtend1(MD); +IF (md = 0) +THROW RESINST; +SLEEP() diff --git a/sh4/STC DBR,Rn b/sh4/STC DBR,Rn new file mode 100644 index 0000000..4f57ecd --- /dev/null +++ b/sh4/STC DBR,Rn @@ -0,0 +1,7 @@ +0000nnnn11111010 +md ← ZeroExtend1(MD); +IF (md = 0) +THROW RESINST; +dbr ← SignExtend32(DBR); +op1 ← dbr +Rn ← Register(op1); diff --git a/sh4/STC GBR,Rn b/sh4/STC GBR,Rn new file mode 100644 index 0000000..af85d5e --- /dev/null +++ b/sh4/STC GBR,Rn @@ -0,0 +1,4 @@ +0000nnnn00010010 +gbr ← SignExtend32(GBR); +op1 ← gbr; +Rn ← Register(op1); diff --git a/sh4/STC Rm_BANK,Rn b/sh4/STC Rm_BANK,Rn new file mode 100644 index 0000000..277a896 --- /dev/null +++ b/sh4/STC Rm_BANK,Rn @@ -0,0 +1,7 @@ +0000nnnn1mmm0010 +md ← ZeroExtend1(MD); +IF (md = 0) +THROW RESINST; +op1 ← SignExtend32(Rm_BANK); +op2 ← op1; +Rn ← Register(op2); diff --git a/sh4/STC SGR,Rn b/sh4/STC SGR,Rn new file mode 100644 index 0000000..c484fa6 --- /dev/null +++ b/sh4/STC SGR,Rn @@ -0,0 +1,7 @@ +0000nnnn00111010 +md ← ZeroExtend1(MD); +IF (md = 0) +THROW RESINST; +sgr ← SignExtend32(SGR); +op1 ← sgr +Rn ← Register(op1); diff --git a/sh4/STC SPC,Rn b/sh4/STC SPC,Rn new file mode 100644 index 0000000..7f0482c --- /dev/null +++ b/sh4/STC SPC,Rn @@ -0,0 +1,7 @@ +0000nnnn01000010 +md ← ZeroExtend1(MD); +IF (md = 0) +THROW RESINST; +spc ← SignExtend32(SPC); +op1 ← spc +Rn ← Register(op1); diff --git a/sh4/STC SR,Rn b/sh4/STC SR,Rn new file mode 100644 index 0000000..71e1aba --- /dev/null +++ b/sh4/STC SR,Rn @@ -0,0 +1,7 @@ +0000nnnn00000010 +md ← ZeroExtend1(MD); +IF (md = 0) +THROW RESINST; +sr ← SignExtend32(SR); +op1 ← sr +Rn ← Register(op1); diff --git a/sh4/STC SSR,Rn b/sh4/STC SSR,Rn new file mode 100644 index 0000000..70b7b88 --- /dev/null +++ b/sh4/STC SSR,Rn @@ -0,0 +1,7 @@ +0000nnnn00110010 +md ← ZeroExtend1(MD); +IF (md = 0) +THROW RESINST; +ssr ← SignExtend32(SSR); +op1 ← ssr +Rn ← Register(op1); diff --git a/sh4/STC VBR,Rn b/sh4/STC VBR,Rn new file mode 100644 index 0000000..b15a795 --- /dev/null +++ b/sh4/STC VBR,Rn @@ -0,0 +1,7 @@ +0000nnnn00100010 +md ← ZeroExtend1(MD); +IF (md = 0) +THROW RESINST; +vbr ← SignExtend32(VBR); +op1 ← vbr +Rn ← Register(op1); diff --git a/sh4/STC.L DBR,@-Rn b/sh4/STC.L DBR,@-Rn new file mode 100644 index 0000000..f10be15 --- /dev/null +++ b/sh4/STC.L DBR,@-Rn @@ -0,0 +1,10 @@ +0100nnnn11110010 +md ← ZeroExtend1(MD); +IF (md = 0) +THROW RESINST; +dbr ← SignExtend32(DBR); +op1 ← SignExtend32(Rn); +address ← ZeroExtend32(op1 - 4); +WriteMemory32(address, dbr); +op1 ← address; +Rn ← Register(op1); diff --git a/sh4/STC.L GBR,@-Rn b/sh4/STC.L GBR,@-Rn new file mode 100644 index 0000000..9419cf7 --- /dev/null +++ b/sh4/STC.L GBR,@-Rn @@ -0,0 +1,7 @@ +0100nnnn00010011 +gbr ← SignExtend32(GBR); +op1 ← SignExtend32(Rn); +address ← ZeroExtend32(op1 - 4); +WriteMemory32(address, gbr); +op1 ← address; +Rn ← Register(op1); diff --git a/sh4/STC.L Rm_BANK,@-Rn b/sh4/STC.L Rm_BANK,@-Rn new file mode 100644 index 0000000..427dfcf --- /dev/null +++ b/sh4/STC.L Rm_BANK,@-Rn @@ -0,0 +1,10 @@ +0100nnnn1mmm0011 +md ← ZeroExtend1(MD); +IF (md = 0) +THROW RESINST; +op1 ← SignExtend32(Rm_BANK); +op2 ← SignExtend32(Rn); +address ← ZeroExtend32(op2 - 4); +WriteMemory32(address, op1); +op2 ← address; +Rn ← Register(op2); diff --git a/sh4/STC.L SGR,@-Rn b/sh4/STC.L SGR,@-Rn new file mode 100644 index 0000000..622ede5 --- /dev/null +++ b/sh4/STC.L SGR,@-Rn @@ -0,0 +1,10 @@ +0100nnnn00110010 +md ← ZeroExtend1(MD); +IF (md = 0) +THROW RESINST; +sgr ← SignExtend32(SGR); +op1 ← SignExtend32(Rn); +address ← ZeroExtend32(op1 - 4); +WriteMemory32(address, sgr); +op1 ← address; +Rn ← Register(op1); diff --git a/sh4/STC.L SPC,@-Rn b/sh4/STC.L SPC,@-Rn new file mode 100644 index 0000000..700beb5 --- /dev/null +++ b/sh4/STC.L SPC,@-Rn @@ -0,0 +1,10 @@ +0100nnnn01000011 +md ← ZeroExtend1(MD); +IF (md = 0) +THROW RESINST; +spc ← SignExtend32(SPC); +op1 ← SignExtend32(Rn); +address ← ZeroExtend32(op1 - 4); +WriteMemory32(address, spc); +op1 ← address; +Rn ← Register(op1); diff --git a/sh4/STC.L SR,@-Rn b/sh4/STC.L SR,@-Rn new file mode 100644 index 0000000..d8e8690 --- /dev/null +++ b/sh4/STC.L SR,@-Rn @@ -0,0 +1,10 @@ +0100nnnn00000011 +md ← ZeroExtend1(MD); +IF (md = 0) +THROW RESINST; +sr ← SignExtend32(SR); +op1 ← SignExtend32(Rn); +address ← ZeroExtend32(op1 - 4); +WriteMemory32(address, sr); +op1 ← address; +Rn ← Register(op1); diff --git a/sh4/STC.L SSR,@-Rn b/sh4/STC.L SSR,@-Rn new file mode 100644 index 0000000..202114f --- /dev/null +++ b/sh4/STC.L SSR,@-Rn @@ -0,0 +1,10 @@ +0100nnnn00110011 +md ← ZeroExtend1(MD); +IF (md = 0) +THROW RESINST; +ssr ← SignExtend32(SSR); +op1 ← SignExtend32(Rn); +address ← ZeroExtend32(op1 - 4); +WriteMemory32(address, ssr); +op1 ← address; +Rn ← Register(op1); diff --git a/sh4/STC.L VBR,@-Rn b/sh4/STC.L VBR,@-Rn new file mode 100644 index 0000000..e913dac --- /dev/null +++ b/sh4/STC.L VBR,@-Rn @@ -0,0 +1,10 @@ +0100nnnn00100011 +md ← ZeroExtend1(MD); +IF (md = 0) +THROW RESINST; +vbr ← SignExtend32(VBR); +op1 ← SignExtend32(Rn); +address ← ZeroExtend32(op1 - 4); +WriteMemory32(address, vbr); +op1 ← address; +Rn ← Register(op1); diff --git a/sh4/STS FPSCR,Rn b/sh4/STS FPSCR,Rn new file mode 100644 index 0000000..e8f96a5 --- /dev/null +++ b/sh4/STS FPSCR,Rn @@ -0,0 +1,9 @@ +0000nnnn01101010 +sr ← ZeroExtend32(SR); +fps ← ZeroExtend32(FPSCR); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +op1 ← fps; +Rn ← Register(op1); diff --git a/sh4/STS FPUL,Rn b/sh4/STS FPUL,Rn new file mode 100644 index 0000000..7953cd6 --- /dev/null +++ b/sh4/STS FPUL,Rn @@ -0,0 +1,9 @@ +0000nnnn01011010 +sr ← ZeroExtend32(SR); +fpul ← SignExtend32(FPUL); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +op1 ← fpul; +Rn ← Register(op1); diff --git a/sh4/STS MACH,Rn b/sh4/STS MACH,Rn new file mode 100644 index 0000000..be8c09a --- /dev/null +++ b/sh4/STS MACH,Rn @@ -0,0 +1,4 @@ +0000nnnn00001010 +mach ← SignExtend32(MACH); +op1 ← mach; +Rn ← Register(op1); diff --git a/sh4/STS MACL,Rn b/sh4/STS MACL,Rn new file mode 100644 index 0000000..79a5d1f --- /dev/null +++ b/sh4/STS MACL,Rn @@ -0,0 +1,4 @@ +0000nnnn00011010 +macl ← SignExtend32(MACL); +op1 ← macl; +Rn ← Register(op1); diff --git a/sh4/STS PR,Rn b/sh4/STS PR,Rn new file mode 100644 index 0000000..a766bad --- /dev/null +++ b/sh4/STS PR,Rn @@ -0,0 +1,4 @@ +0000nnnn00101010 +pr ← SignExtend32(PR’); +op1 ← pr; +Rn ← Register(op1); diff --git a/sh4/STS.L FPSCR,@-Rn b/sh4/STS.L FPSCR,@-Rn new file mode 100644 index 0000000..4e8b71e --- /dev/null +++ b/sh4/STS.L FPSCR,@-Rn @@ -0,0 +1,13 @@ +0100nnnn01100010 +sr ← ZeroExtend32(SR); +fps ← ZeroExtend32(FPSCR); +op1 ← SignExtend32(Rn); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +value ← fps; +address ← ZeroExtend32(op1 - 4); +WriteMemory32(address, value); +op1 ← address; +Rn ← Register(op1); diff --git a/sh4/STS.L FPUL,@-Rn b/sh4/STS.L FPUL,@-Rn new file mode 100644 index 0000000..dd42f47 --- /dev/null +++ b/sh4/STS.L FPUL,@-Rn @@ -0,0 +1,12 @@ +0100nnnn01010010 +sr ← ZeroExtend32(SR); +fpul ← SignExtend32(FPUL); +op1 ← SignExtend32(Rn); +IF (FpuIsDisabled(sr) AND IsDelaySlot()) +THROW SLOTFPUDIS; +IF (FpuIsDisabled(sr)) +THROW FPUDIS; +address ← ZeroExtend32(op1 - 4); +WriteMemory32(address, fpul); +op1 ← address; +Rn ← Register(op1); diff --git a/sh4/STS.L MACH,@-Rn b/sh4/STS.L MACH,@-Rn new file mode 100644 index 0000000..90f2182 --- /dev/null +++ b/sh4/STS.L MACH,@-Rn @@ -0,0 +1,7 @@ +0100nnnn00000010 +mach ← SignExtend32(MACH); +op1 ← SignExtend32(Rn); +address ← ZeroExtend32(op1 - 4); +WriteMemory32(address, mach); +op1 ← address; +Rn ← Register(op1); diff --git a/sh4/STS.L MACL,@-Rn b/sh4/STS.L MACL,@-Rn new file mode 100644 index 0000000..b365032 --- /dev/null +++ b/sh4/STS.L MACL,@-Rn @@ -0,0 +1,7 @@ +0100nnnn00010010 +macl ← SignExtend32(MACL); +op1 ← SignExtend32(Rn); +address ← ZeroExtend32(op1 - 4); +WriteMemory32(address, macl); +op1 ← address; +Rn ← Register(op1); diff --git a/sh4/STS.L PR,@-Rn b/sh4/STS.L PR,@-Rn new file mode 100644 index 0000000..d7c8813 --- /dev/null +++ b/sh4/STS.L PR,@-Rn @@ -0,0 +1,7 @@ +0100nnnn00100010 +pr ← SignExtend32(PR’); +op1 ← SignExtend32(Rn); +address ← ZeroExtend32(op1 - 4); +WriteMemory32(address, pr); +op1 ← address; +Rn ← Register(op1); diff --git a/sh4/SUB Rm,Rn b/sh4/SUB Rm,Rn new file mode 100644 index 0000000..675e754 --- /dev/null +++ b/sh4/SUB Rm,Rn @@ -0,0 +1,5 @@ +0011nnnnmmmm1000 +op1 ← SignExtend32(Rm); +op2 ← SignExtend32(Rn); +op2 ← op2 - op1; +Rn ← Register(op2); diff --git a/sh4/SUBC Rm,Rn b/sh4/SUBC Rm,Rn new file mode 100644 index 0000000..58374f6 --- /dev/null +++ b/sh4/SUBC Rm,Rn @@ -0,0 +1,8 @@ +0011nnnnmmmm1010 +t ← ZeroExtend1(T); +op1 ← ZeroExtend32(SignExtend32(Rm)); +op2 ← ZeroExtend32(SignExtend32(Rn)); +op2 ← (op2 - op1) - t; +t ← op2< 32 FOR 1 >; +Rn ← Register(op2); +T ← Bit(t); diff --git a/sh4/SUBV Rm,Rn b/sh4/SUBV Rm,Rn new file mode 100644 index 0000000..3add34c --- /dev/null +++ b/sh4/SUBV Rm,Rn @@ -0,0 +1,7 @@ +0011nnnnmmmm1011 +op1 ← SignExtend32(Rm); +op2 ← SignExtend32(Rn); +op2 ← op2 - op1; +t ← INT ((op2 < (- 231)) OR (op2 ≥ 231)); +Rn ← Register(op2); +T ← Bit(t); diff --git a/sh4/SWAP.B Rm,Rn b/sh4/SWAP.B Rm,Rn new file mode 100644 index 0000000..c5fb903 --- /dev/null +++ b/sh4/SWAP.B Rm,Rn @@ -0,0 +1,4 @@ +0110nnnnmmmm1000 +op1 ← ZeroExtend32(Rm); +op2 ← ((op1< 16 FOR 16 > << 16) ∨ (op1< 0 FOR 8 > << 8)) ∨ op1< 8 FOR 8 >; +Rn ← Register(op2); diff --git a/sh4/SWAP.W Rm,Rn b/sh4/SWAP.W Rm,Rn new file mode 100644 index 0000000..edfb231 --- /dev/null +++ b/sh4/SWAP.W Rm,Rn @@ -0,0 +1,4 @@ +0110nnnnmmmm1001 +op1 ← ZeroExtend32(Rm); +op2 ← (op1< 0 FOR 16 > << 16) ∨ op1< 16 FOR 16 >; +Rn ← Register(op2); diff --git a/sh4/TAS.B @Rn b/sh4/TAS.B @Rn new file mode 100644 index 0000000..721b277 --- /dev/null +++ b/sh4/TAS.B @Rn @@ -0,0 +1,9 @@ +0100nnnn00011011 +op1 ← SignExtend32(Rn); +address ← ZeroExtend32(op1); +OCBP(address) +value ← ZeroExtend8(ReadMemory8(address)); +t ← INT (value = 0); +value ← value ∨ (1 << 7); +WriteMemory8(address, value); +T ← Bit(t); diff --git a/sh4/TRAPA #imm b/sh4/TRAPA #imm new file mode 100644 index 0000000..02aef1c --- /dev/null +++ b/sh4/TRAPA #imm @@ -0,0 +1,5 @@ +11000011iiiiiiii +imm ← ZeroExtend8(i); +IF (IsDelaySlot()) +THROW ILLSLOT; +THROW TRAP, imm; diff --git a/sh4/TST #imm,R0 b/sh4/TST #imm,R0 new file mode 100644 index 0000000..528b07e --- /dev/null +++ b/sh4/TST #imm,R0 @@ -0,0 +1,5 @@ +11001000iiiiiiii +r0 ← SignExtend32(R0); +imm ← ZeroExtend8(i); +t ← INT ((r0 ∧ imm) = 0); +T ← Bit(t); diff --git a/sh4/TST Rm,Rn b/sh4/TST Rm,Rn new file mode 100644 index 0000000..045c84a --- /dev/null +++ b/sh4/TST Rm,Rn @@ -0,0 +1,5 @@ +0010nnnnmmmm1000 +op1 ← SignExtend32(Rm); +op2 ← SignExtend32(Rn); +t ← INT ((op1 ∧ op2) = 0); +T ← Bit(t); diff --git a/sh4/TST.B #imm,@(R0,GBR) b/sh4/TST.B #imm,@(R0,GBR) new file mode 100644 index 0000000..25a1919 --- /dev/null +++ b/sh4/TST.B #imm,@(R0,GBR) @@ -0,0 +1,8 @@ +11001100iiiiiiii +r0 ← SignExtend32(R0); +gbr ← SignExtend32(GBR); +imm ← ZeroExtend8(i); +address ← ZeroExtend32(r0 + gbr); +value ← ZeroExtend8(ReadMemory8(address)); +t ← ((value ∧ imm) = 0); +T ← Bit(t); diff --git a/sh4/XOR #imm,R0 b/sh4/XOR #imm,R0 new file mode 100644 index 0000000..bcb5428 --- /dev/null +++ b/sh4/XOR #imm,R0 @@ -0,0 +1,5 @@ +11001010iiiiiiii +r0 ← ZeroExtend32(R0); +imm ← ZeroExtend8(i); +r0 ← r0 ⊕ imm; +R0 ← Register(r0); diff --git a/sh4/XOR Rm,Rn b/sh4/XOR Rm,Rn new file mode 100644 index 0000000..637b5ed --- /dev/null +++ b/sh4/XOR Rm,Rn @@ -0,0 +1,5 @@ +0010nnnnmmmm1010 +op1 ← ZeroExtend32(Rm); +op2 ← ZeroExtend32(Rn); +op2 ← op2 ⊕ op1; +Rn ← Register(op2); diff --git a/sh4/XOR.B #imm,@(R0,GBR) b/sh4/XOR.B #imm,@(R0,GBR) new file mode 100644 index 0000000..a99cc4e --- /dev/null +++ b/sh4/XOR.B #imm,@(R0,GBR) @@ -0,0 +1,8 @@ +11001110iiiiiiii +r0 ← SignExtend32(R0); +gbr ← SignExtend32(GBR); +imm ← ZeroExtend8(i); +address ← ZeroExtend32(r0 + gbr); +value ← ZeroExtend8(ReadMemory8(address)); +value ← value ⊕ imm; +WriteMemory8(address, value); diff --git a/sh4/XTRCT Rm,Rn b/sh4/XTRCT Rm,Rn new file mode 100644 index 0000000..043cbfd --- /dev/null +++ b/sh4/XTRCT Rm,Rn @@ -0,0 +1,5 @@ +0010nnnnmmmm1101 +op1 ← ZeroExtend32(Rm); +op2 ← ZeroExtend32(Rn); +op2 ← op2< 16 FOR 16 > ∨ (op1< 0 FOR 16 > << 16); +Rn ← Register(op2);