bilbo/sh-dis
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

sh4: fix documentation typos for SH2 instructions

Browse Source 
These changes fix logical consistency and correctness issues with the
instruction definitions as printed in the SH4 manual.

The most serious issues were:

- div0u/div0s/div1 use `m` as a temporary variable which
  contradicts the existence of the `m` register number

- missing semicolons

- inconsistent references to immediate and displacement variable names
This commit is contained in:
Zack Buhman 2024-04-21 13:11:30 +08:00
parent d1ce9a2d5a
commit 4a165d02ed
47 changed files with 64 additions and 71 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
sh4/ADD #imm,Rn
View File

@ -1,5 +1,5 @@
0111nnnniiiiiiii 0111nnnniiiiiiii
imm ← SignExtend8(s); imm ← SignExtend8(i);
op2 ← SignExtend32(Rn); op2 ← SignExtend32(Rn);
op2 ← op2 + imm; op2 ← op2 + imm;
Rn ← Register(op2); Rn ← Register(op2);

2
sh4/BF label
View File

@ -3,7 +3,7 @@ t ← ZeroExtend1(T);
pc ← SignExtend32(PC); pc ← SignExtend32(PC);
newpc ← SignExtend32(PC’); newpc ← SignExtend32(PC’);
delayedpc ← SignExtend32(PC’’); delayedpc ← SignExtend32(PC’’);
label ← SignExtend8(s) << 1; label ← SignExtend8(d) << 1;
IF (IsDelaySlot()) IF (IsDelaySlot())
THROW ILLSLOT; THROW ILLSLOT;
IF (t = 0) IF (t = 0)

2
sh4/BF_S label
View File

@ -2,7 +2,7 @@
t ← ZeroExtend1(T); t ← ZeroExtend1(T);
pc ← SignExtend32(PC); pc ← SignExtend32(PC);
delayedpc ← SignExtend32(PC’’); delayedpc ← SignExtend32(PC’’);
label ← SignExtend8(s) << 1; label ← SignExtend8(d) << 1;
IF (IsDelaySlot()) IF (IsDelaySlot())
THROW ILLSLOT; THROW ILLSLOT;
IF (t = 0) IF (t = 0)

2
sh4/BRA label
View File

@ -1,6 +1,6 @@
1010dddddddddddd 1010dddddddddddd
pc ← SignExtend32(PC); pc ← SignExtend32(PC);
label ← SignExtend12(s) << 1; label ← SignExtend12(d) << 1;
IF (IsDelaySlot()) IF (IsDelaySlot())
THROW ILLSLOT; THROW ILLSLOT;
temp ← ZeroExtend32(pc + 4 + label); temp ← ZeroExtend32(pc + 4 + label);

2
sh4/BSR label
View File

@ -1,6 +1,6 @@
1011dddddddddddd 1011dddddddddddd
pc ← SignExtend32(PC); pc ← SignExtend32(PC);
label ← SignExtend12(s) << 1; label ← SignExtend12(d) << 1;
IF (IsDelaySlot()) IF (IsDelaySlot())
THROW ILLSLOT; THROW ILLSLOT;
delayedpr ← pc + 4; delayedpr ← pc + 4;

2
sh4/BT label
View File

@ -3,7 +3,7 @@ t ← ZeroExtend1(T);
pc ← SignExtend32(PC); pc ← SignExtend32(PC);
newpc ← SignExtend32(PC’); newpc ← SignExtend32(PC’);
delayedpc ← SignExtend32(PC’’); delayedpc ← SignExtend32(PC’’);
label ← SignExtend8(s) << 1; label ← SignExtend8(d) << 1;
IF (IsDelaySlot()) IF (IsDelaySlot())
THROW ILLSLOT; THROW ILLSLOT;
IF (t = 1) IF (t = 1)

2
sh4/BT_S label
View File

@ -2,7 +2,7 @@
t ← ZeroExtend1(T); t ← ZeroExtend1(T);
pc ← SignExtend32(PC); pc ← SignExtend32(PC);
delayedpc ← SignExtend32(PC’’); delayedpc ← SignExtend32(PC’’);
label ← SignExtend8(s) << 1; label ← SignExtend8(d) << 1;
IF (IsDelaySlot()) IF (IsDelaySlot())
THROW ILLSLOT; THROW ILLSLOT;
IF (t = 1) IF (t = 1)

2
sh4/CMP_EQ #imm,R0
View File

@ -1,5 +1,5 @@
10001000iiiiiiii 10001000iiiiiiii
r0 ← SignExtend32(R0); r0 ← SignExtend32(R0);
imm ← SignExtend8(s); imm ← SignExtend8(i);
t ← INT (r0 = imm); t ← INT (r0 = imm);
T ← Bit(t); T ← Bit(t);

6
sh4/DIV0S Rm,Rn
View File

@ -2,8 +2,8 @@
op1 ← SignExtend32(Rm); op1 ← SignExtend32(Rm);
op2 ← SignExtend32(Rn); op2 ← SignExtend32(Rn);
q ← op2< 31 FOR 1 >; q ← op2< 31 FOR 1 >;
m ← op1< 31 FOR 1 >; _m ← op1< 31 FOR 1 >;
t ← m ⊕ q; t ← _m ⊕ q;
Q ← Bit(q); Q ← Bit(q);
M ← Bit(m); M ← Bit(_m);
T ← Bit(t); T ← Bit(t);

4
sh4/DIV0U
View File

@ -1,7 +1,7 @@
0000000000011001 0000000000011001
q ← 0; q ← 0;
m ← 0; _m ← 0;
t ← 0; t ← 0;
Q ← Bit(q); Q ← Bit(q);
M ← Bit(m); M ← Bit(_m);
T ← Bit(t); T ← Bit(t);

8
sh4/DIV1 Rm,Rn
View File

@ -1,18 +1,18 @@
0011nnnnmmmm0100 0011nnnnmmmm0100
q ← ZeroExtend1(Q); q ← ZeroExtend1(Q);
m ← ZeroExtend1(M); _m ← ZeroExtend1(M);
t ← ZeroExtend1(T); t ← ZeroExtend1(T);
op1 ← ZeroExtend32(SignExtend32(Rm)); op1 ← ZeroExtend32(SignExtend32(Rm));
op2 ← ZeroExtend32(SignExtend32(Rn)); op2 ← ZeroExtend32(SignExtend32(Rn));
oldq ← q; oldq ← q;
q ← op2< 31 FOR 1 >; q ← op2< 31 FOR 1 >;
op2 ← ZeroExtend32(op2 << 1) ∨ t; op2 ← ZeroExtend32(op2 << 1) ∨ t;
IF (oldq = m) IF (oldq = _m)
op2 ← op2 - op1; op2 ← op2 - op1;
ELSE ELSE
op2 ← op2 + op1; op2 ← op2 + op1;
q ← (q ⊕ m) ⊕ op2< 32 FOR 1 >; q ← (q ⊕ _m) ⊕ op2< 32 FOR 1 >;
t ← 1 - (q ⊕ m); t ← 1 - (q ⊕ _m);
Rn ← Register(op2); Rn ← Register(op2);
Q ← Bit(q); Q ← Bit(q);
T ← Bit(t); T ← Bit(t);

4
sh4/FSCHG
View File

@ -1,10 +1,10 @@
1111001111111101 1111001111111101
Available only when PR=0 Available only when PR=0
sr ← ZeroExtend32(SR); sr ← ZeroExtend32(SR);
sz ← ZeroExtend1(SR.SZ); sz ← ZeroExtend1(FPSCR.SZ);
IF (FpuIsDisabled(sr) AND IsDelaySlot()) IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS; THROW SLOTFPUDIS;
IF (FpuIsDisabled(sr)) IF (FpuIsDisabled(sr))
THROW FPUDIS; THROW FPUDIS;
sz ← sz ⊕ 1; sz ← sz ⊕ 1;
SR.SZ ← Bit(sz); FPSCR.SZ ← Bit(sz);

2
sh4/LDC Rm,DBR
View File

@ -3,5 +3,5 @@ md ← ZeroExtend1(MD);
IF (md = 0) IF (md = 0)
THROW RESINST; THROW RESINST;
op1 ← SignExtend32(Rm); op1 ← SignExtend32(Rm);
dbr← op1; dbr ← op1;
DBR ← Register(dbr); DBR ← Register(dbr);

2
sh4/LDC Rm,VBR
View File

@ -3,5 +3,5 @@ md ← ZeroExtend1(MD);
IF (md = 0) IF (md = 0)
THROW RESINST; THROW RESINST;
op1 ← SignExtend32(Rm); op1 ← SignExtend32(Rm);
vbr← op1; vbr ← op1;
VBR ← Register(vbr); VBR ← Register(vbr);

6
sh4/LDS Rm,FPSCR
View File

@ -5,8 +5,4 @@ IF (FpuIsDisabled(sr) AND IsDelaySlot())
THROW SLOTFPUDIS; THROW SLOTFPUDIS;
IF (FpuIsDisabled(sr)) IF (FpuIsDisabled(sr))
THROW FPUDIS; THROW FPUDIS;
fps, pr, sz, fr ← UnpackFPSCR(op1); FPSCR ← ZeroExtend32(op1);
FPSCR ← ZeroExtend32(fps);
SR.PR ← Bit(pr);
SR.SZ ← Bit(sz);
SR.FR ← Bit(fr);

6
sh4/LDS.L @Rm+,FPSCR
View File

@ -7,10 +7,6 @@ IF (FpuIsDisabled(sr))
THROW FPUDIS; THROW FPUDIS;
address ← ZeroExtend32(op1); address ← ZeroExtend32(op1);
value ← ReadMemory32(address); value ← ReadMemory32(address);
fps, pr, sz, fr ← UnpackFPSCR(value);
op1 ← op1 + 4; op1 ← op1 + 4;
Rm ← Register(op1); Rm ← Register(op1);
FPSCR ← ZeroExtend32(fps); FPSCR ← ZeroExtend32(value);
SR.PR ← Bit(pr);
SR.SZ ← Bit(sz);
SR.FR ← Bit(fr);

20
sh4/LDTLB
View File

@ -2,13 +2,13 @@
md ← ZeroExtend1(MD); md ← ZeroExtend1(MD);
IF (md = 0) IF (md = 0)
THROW RESINST; THROW RESINST;
UTLB[MMUCR.URC].ASID ← PTEH.ASID UTLB[MMUCR.URC].ASID ← PTEH.ASID;
UTLB[MMUCR.URC].VPN ← PTEH.VPN UTLB[MMUCR.URC].VPN ← PTEH.VPN;
UTLB[MMUCR.URC].PPN ← PTEH.PPN UTLB[MMUCR.URC].PPN ← PTEH.PPN;
UTLB[MMUCR.URC].SZ ← PTEL.SZ1<<1 + PTEL.SZ0 UTLB[MMUCR.URC].SZ ← PTEL.SZ1<<1 + PTEL.SZ0;
UTLB[MMUCR.URC].SH ← PTEL.SH UTLB[MMUCR.URC].SH ← PTEL.SH;
UTLB[MMUCR.URC].PR ← PTEL.PR UTLB[MMUCR.URC].PR ← PTEL.PR;
UTLB[MMUCR.URC].WT ← PTEL.WT UTLB[MMUCR.URC].WT ← PTEL.WT;
UTLB[MMUCR.URC].C ← PTEL.C UTLB[MMUCR.URC].C ← PTEL.C;
UTLB[MMUCR.URC].D ← PTEL.D UTLB[MMUCR.URC].D ← PTEL.D;
UTLB[MMUCR.URC].V ← PTEL.V UTLB[MMUCR.URC].V ← PTEL.V;

3
sh4/MAC.W @Rm+,@Rn+
View File

@ -16,6 +16,7 @@ n_address ← n_address + 2;
value1 ← SignExtend16(ReadMemory16(ZeroExtend32(m_address))); value1 ← SignExtend16(ReadMemory16(ZeroExtend32(m_address)));
m_address ← m_address + 2; m_address ← m_address + 2;
mul ← value2 × value1; mul ← value2 × value1;
result ← 0;
IF (s = 1) IF (s = 1)
{ {
macl ← SignExtend32(macl) + mul; macl ← SignExtend32(macl) + mul;
@ -23,7 +24,7 @@ temp ← SignedSaturate32(macl);
IF (macl = temp) IF (macl = temp)
result ← (mach << 32) ∨ ZeroExtend32(macl); result ← (mach << 32) ∨ ZeroExtend32(macl);
ELSE ELSE
result ← (0x1 << 32) ∨ ZeroExtend32(temp); result ← (1 << 32) ∨ ZeroExtend32(temp);
} }
ELSE ELSE
result ← ((mach << 32) + macl) + mul; result ← ((mach << 32) + macl) + mul;

2
sh4/MOV #imm,Rn
View File

@ -1,4 +1,4 @@
1110nnnniiiiiiii 1110nnnniiiiiiii
imm ← SignExtend8(s); imm ← SignExtend8(i);
op2 ← imm; op2 ← imm;
Rn ← Register(op2); Rn ← Register(op2);

2
sh4/MOV.B @(disp,GBR),R0
View File

@ -1,6 +1,6 @@
11000100dddddddd 11000100dddddddd
gbr ← SignExtend32(GBR); gbr ← SignExtend32(GBR);
disp ← ZeroExtend8(i); disp ← ZeroExtend8(d);
address ← ZeroExtend32(disp + gbr); address ← ZeroExtend32(disp + gbr);
r0 ← SignExtend8(ReadMemory8(address)); r0 ← SignExtend8(ReadMemory8(address));
R0 ← Register(r0); R0 ← Register(r0);

2
sh4/MOV.B @(disp,Rm),R0
View File

@ -1,5 +1,5 @@
10000100mmmmdddd 10000100mmmmdddd
disp ← ZeroExtend4(i); disp ← ZeroExtend4(d);
op2 ← SignExtend32(Rm); op2 ← SignExtend32(Rm);
address ← ZeroExtend32(disp + op2); address ← ZeroExtend32(disp + op2);
r0 ← SignExtend8(ReadMemory8(address)); r0 ← SignExtend8(ReadMemory8(address));

2
sh4/MOV.B R0,@(disp,GBR)
View File

@ -1,6 +1,6 @@
11000000dddddddd 11000000dddddddd
gbr ← SignExtend32(GBR); gbr ← SignExtend32(GBR);
r0 ← SignExtend32(R0); r0 ← SignExtend32(R0);
disp ← ZeroExtend8(i); disp ← ZeroExtend8(d);
address ← ZeroExtend32(disp + gbr); address ← ZeroExtend32(disp + gbr);
WriteMemory8(address, r0); WriteMemory8(address, r0);

2
sh4/MOV.B R0,@(disp,Rn)
View File

@ -1,6 +1,6 @@
10000000nnnndddd 10000000nnnndddd
r0 ← SignExtend32(R0); r0 ← SignExtend32(R0);
disp ← ZeroExtend4(i); disp ← ZeroExtend4(d);
op2 ← SignExtend32(Rn); op2 ← SignExtend32(Rn);
address ← ZeroExtend32(disp + op2); address ← ZeroExtend32(disp + op2);
WriteMemory8(address, r0); WriteMemory8(address, r0);

2
sh4/MOV.L @(disp,GBR),R0
View File

@ -1,6 +1,6 @@
11000110dddddddd 11000110dddddddd
gbr ← SignExtend32(GBR); gbr ← SignExtend32(GBR);
disp ← ZeroExtend8(i) << 2; disp ← ZeroExtend8(d) << 2;
address ← ZeroExtend32(disp + gbr); address ← ZeroExtend32(disp + gbr);
r0 ← SignExtend32(ReadMemory32(address)); r0 ← SignExtend32(ReadMemory32(address));
R0 ← Register(r0); R0 ← Register(r0);

2
sh4/MOV.L @(disp,PC),Rn
View File

@ -1,6 +1,6 @@
1101nnnndddddddd 1101nnnndddddddd
pc ← SignExtend32(PC); pc ← SignExtend32(PC);
disp ← ZeroExtend8(i) << 2; disp ← ZeroExtend8(d) << 2;
IF (IsDelaySlot()) IF (IsDelaySlot())
THROW ILLSLOT; THROW ILLSLOT;
address ← ZeroExtend32(disp + ((pc + 4) ∧ (~ 0x3))); address ← ZeroExtend32(disp + ((pc + 4) ∧ (~ 0x3)));

2
sh4/MOV.L @(disp,Rm),Rn
View File

@ -1,5 +1,5 @@
0101nnnnmmmmdddd 0101nnnnmmmmdddd
disp ← ZeroExtend4(i) << 2; disp ← ZeroExtend4(d) << 2;
op2 ← SignExtend32(Rm); op2 ← SignExtend32(Rm);
address ← ZeroExtend32(disp + op2); address ← ZeroExtend32(disp + op2);
op3 ← SignExtend32(ReadMemory32(address)); op3 ← SignExtend32(ReadMemory32(address));

2
sh4/MOV.L R0,@(disp,GBR)
View File

@ -1,6 +1,6 @@
11000010dddddddd 11000010dddddddd
gbr ← SignExtend32(GBR); gbr ← SignExtend32(GBR);
r0 ← SignExtend32(R0); r0 ← SignExtend32(R0);
disp ← ZeroExtend8(i) << 2; disp ← ZeroExtend8(d) << 2;
address ← ZeroExtend32(disp + gbr); address ← ZeroExtend32(disp + gbr);
WriteMemory32(address, r0); WriteMemory32(address, r0);

2
sh4/MOV.L Rm,@(disp,Rn)
View File

@ -1,6 +1,6 @@
0001nnnnmmmmdddd 0001nnnnmmmmdddd
op1 ← SignExtend32(Rm); op1 ← SignExtend32(Rm);
disp ← ZeroExtend4(i) << 2; disp ← ZeroExtend4(d) << 2;
op3 ← SignExtend32(Rn); op3 ← SignExtend32(Rn);
address ← ZeroExtend32(disp + op3); address ← ZeroExtend32(disp + op3);
WriteMemory32(address, op1); WriteMemory32(address, op1);

2
sh4/MOV.W @(disp,GBR),R0
View File

@ -1,6 +1,6 @@
11000101dddddddd 11000101dddddddd
gbr ← SignExtend32(GBR); gbr ← SignExtend32(GBR);
disp ← ZeroExtend8(i) << 1; disp ← ZeroExtend8(d) << 1;
address ← ZeroExtend32(disp + gbr); address ← ZeroExtend32(disp + gbr);
r0 ← SignExtend16(ReadMemory16(address)); r0 ← SignExtend16(ReadMemory16(address));
R0 ← Register(r0); R0 ← Register(r0);

2
sh4/MOV.W @(disp,PC),Rn
View File

@ -1,6 +1,6 @@
1001nnnndddddddd 1001nnnndddddddd
pc ← SignExtend32(PC); pc ← SignExtend32(PC);
disp ← ZeroExtend8(i) << 1; disp ← ZeroExtend8(d) << 1;
IF (IsDelaySlot()) IF (IsDelaySlot())
THROW ILLSLOT; THROW ILLSLOT;
address ← ZeroExtend32(disp + (pc + 4)); address ← ZeroExtend32(disp + (pc + 4));

2
sh4/MOV.W @(disp,Rm),R0
View File

@ -1,5 +1,5 @@
10000101mmmmdddd 10000101mmmmdddd
disp ← ZeroExtend4(i) << 1; disp ← ZeroExtend4(d) << 1;
op2 ← SignExtend32(Rm); op2 ← SignExtend32(Rm);
address ← ZeroExtend32(disp + op2); address ← ZeroExtend32(disp + op2);
r0 ← SignExtend16(ReadMemory16(address)); r0 ← SignExtend16(ReadMemory16(address));

2
sh4/MOV.W R0,@(disp,GBR)
View File

@ -1,6 +1,6 @@
11000001dddddddd 11000001dddddddd
gbr ← SignExtend32(GBR); gbr ← SignExtend32(GBR);
r0 ← SignExtend32(R0); r0 ← SignExtend32(R0);
disp ← ZeroExtend8(i) << 1; disp ← ZeroExtend8(d) << 1;
address ← ZeroExtend32(disp + gbr); address ← ZeroExtend32(disp + gbr);
WriteMemory16(address, r0); WriteMemory16(address, r0);

2
sh4/MOV.W R0,@(disp,Rn)
View File

@ -1,6 +1,6 @@
10000001nnnndddd 10000001nnnndddd
r0 ← SignExtend32(R0); r0 ← SignExtend32(R0);
disp ← ZeroExtend4(i) << 1; disp ← ZeroExtend4(d) << 1;
op2 ← SignExtend32(Rn); op2 ← SignExtend32(Rn);
address ← ZeroExtend32(disp + op2); address ← ZeroExtend32(disp + op2);
WriteMemory16(address, r0); WriteMemory16(address, r0);

2
sh4/MOVA @(disp,PC),R0
View File

@ -1,6 +1,6 @@
11000111dddddddd 11000111dddddddd
pc ← SignExtend32(PC); pc ← SignExtend32(PC);
disp ← ZeroExtend8(i) << 2; disp ← ZeroExtend8(d) << 2;
IF (IsDelaySlot()) IF (IsDelaySlot())
THROW ILLSLOT; THROW ILLSLOT;
r0 ← disp + ((pc + 4) ∧ (~ 0x3)); r0 ← disp + ((pc + 4) ∧ (~ 0x3));

2
sh4/MOVCA.L R0,@Rn
View File

@ -8,7 +8,7 @@ THROW WTLBMISS, op1;
IF (MMU() AND WriteProhibited(op1)) IF (MMU() AND WriteProhibited(op1))
THROW WRITEPROT, op1; THROW WRITEPROT, op1;
IF (MMU() AND NOT DirtyBit(op1)) IF (MMU() AND NOT DirtyBit(op1))
THROW FIRSTWRITE, op1 THROW FIRSTWRITE, op1;
ALLOCO(op1); ALLOCO(op1);
address ← ZeroExtend32(op1); address ← ZeroExtend32(op1);
WriteMemory32(op1, r0); WriteMemory32(op1, r0);

2
sh4/NOP
View File

@ -1,2 +1,2 @@
0000000000001001 0000000000001001
NOP NOP;

2
sh4/OCBI @Rn
View File

@ -7,5 +7,5 @@ THROW WTLBMISS, op1;
IF (MMU() AND WriteProhibited(op1)) IF (MMU() AND WriteProhibited(op1))
THROW WRITEPROT, op1; THROW WRITEPROT, op1;
IF (MMU() AND NOT DirtyBit(op1)) IF (MMU() AND NOT DirtyBit(op1))
THROW FIRSTWRITE, op1 THROW FIRSTWRITE, op1;
OCBI(op1); OCBI(op1);

2
sh4/PREF @Rn
View File

@ -1,7 +1,7 @@
0000nnnn10000011 0000nnnn10000011
op1 ← SignExtend32(Rn); op1 ← SignExtend32(Rn);
IF (AddressUnavailable(op1)) IF (AddressUnavailable(op1))
THROW RADDERR, op1 THROW RADDERR, op1;
IF (NOT (MMU() AND DataAccessMiss(op1))) IF (NOT (MMU() AND DataAccessMiss(op1)))
IF (NOT (MMU() AND ReadProhibited(op1))) IF (NOT (MMU() AND ReadProhibited(op1)))
PREF(op1); PREF(op1);

2
sh4/RTE
View File

@ -3,7 +3,7 @@ md ← ZeroExtend1(MD);
IF (md = 0) IF (md = 0)
THROW RESINST; THROW RESINST;
ssr ← SignExtend32(SSR); ssr ← SignExtend32(SSR);
pc ← SignExtend32(PC) pc ← SignExtend32(PC);
IF (IsDelaySlot()) IF (IsDelaySlot())
THROW ILLSLOT; THROW ILLSLOT;
target ← pc; target ← pc;

2
sh4/SLEEP
View File

@ -2,4 +2,4 @@
md ← ZeroExtend1(MD); md ← ZeroExtend1(MD);
IF (md = 0) IF (md = 0)
THROW RESINST; THROW RESINST;
SLEEP() SLEEP();

2
sh4/STC DBR,Rn
View File

@ -3,5 +3,5 @@ md ← ZeroExtend1(MD);
IF (md = 0) IF (md = 0)
THROW RESINST; THROW RESINST;
dbr ← SignExtend32(DBR); dbr ← SignExtend32(DBR);
op1 ← dbr op1 ← dbr;
Rn ← Register(op1); Rn ← Register(op1);

2
sh4/STC SGR,Rn
View File

@ -3,5 +3,5 @@ md ← ZeroExtend1(MD);
IF (md = 0) IF (md = 0)
THROW RESINST; THROW RESINST;
sgr ← SignExtend32(SGR); sgr ← SignExtend32(SGR);
op1 ← sgr op1 ← sgr;
Rn ← Register(op1); Rn ← Register(op1);

2
sh4/STC SPC,Rn
View File

@ -3,5 +3,5 @@ md ← ZeroExtend1(MD);
IF (md = 0) IF (md = 0)
THROW RESINST; THROW RESINST;
spc ← SignExtend32(SPC); spc ← SignExtend32(SPC);
op1 ← spc op1 ← spc;
Rn ← Register(op1); Rn ← Register(op1);

2
sh4/STC SR,Rn
View File

@ -3,5 +3,5 @@ md ← ZeroExtend1(MD);
IF (md = 0) IF (md = 0)
THROW RESINST; THROW RESINST;
sr ← SignExtend32(SR); sr ← SignExtend32(SR);
op1 ← sr op1 ← sr;
Rn ← Register(op1); Rn ← Register(op1);

2
sh4/STC SSR,Rn
View File

@ -3,5 +3,5 @@ md ← ZeroExtend1(MD);
IF (md = 0) IF (md = 0)
THROW RESINST; THROW RESINST;
ssr ← SignExtend32(SSR); ssr ← SignExtend32(SSR);
op1 ← ssr op1 ← ssr;
Rn ← Register(op1); Rn ← Register(op1);

2
sh4/STC VBR,Rn
View File

@ -3,5 +3,5 @@ md ← ZeroExtend1(MD);
IF (md = 0) IF (md = 0)
THROW RESINST; THROW RESINST;
vbr ← SignExtend32(VBR); vbr ← SignExtend32(VBR);
op1 ← vbr op1 ← vbr;
Rn ← Register(op1); Rn ← Register(op1);

2
sh4/TAS.B @Rn
View File

@ -1,7 +1,7 @@
0100nnnn00011011 0100nnnn00011011
op1 ← SignExtend32(Rn); op1 ← SignExtend32(Rn);
address ← ZeroExtend32(op1); address ← ZeroExtend32(op1);
OCBP(address) OCBP(address);
value ← ZeroExtend8(ReadMemory8(address)); value ← ZeroExtend8(ReadMemory8(address));
t ← INT (value = 0); t ← INT (value = 0);
value ← value ∨ (1 << 7); value ← value ∨ (1 << 7);