diff --git a/sh4/FLDS FRm,FPUL b/sh4/FLDS FRm,FPUL
index ef6ab7e..93e65cf 100644
--- a/sh4/FLDS FRm,FPUL	
+++ b/sh4/FLDS FRm,FPUL	
@@ -5,5 +5,5 @@ IF (FpuIsDisabled(sr) AND IsDelaySlot())
 THROW SLOTFPUDIS;
 IF (FpuIsDisabled(sr))
 THROW FPUDIS;
-fpul ← op1;
+fpul ← FloatRegister32(op1);
 FPUL ← ZeroExtend32(fpul);
diff --git a/sh4/FMOV @Rm+,DRn b/sh4/FMOV @Rm+,DRn
index ad721b7..13e07bf 100644
--- a/sh4/FMOV @Rm+,DRn	
+++ b/sh4/FMOV @Rm+,DRn	
@@ -1,7 +1,6 @@
 1111nnn0mmmm1001
 Available only when PR=0 and SZ=1
 sr ← ZeroExtend32(SR);
-fps ← ZeroExtend32(FPSCR);
 op1 ← SignExtend32(Rm);
 IF (FpuIsDisabled(sr) AND IsDelaySlot())
 THROW SLOTFPUDIS;
diff --git a/sh4/FMOV @Rm+,XDn b/sh4/FMOV @Rm+,XDn
index 2337b18..5186182 100644
--- a/sh4/FMOV @Rm+,XDn	
+++ b/sh4/FMOV @Rm+,XDn	
@@ -1,7 +1,6 @@
 1111nnn1mmmm1001
 Available only when PR=0 and SZ=1
 sr ← ZeroExtend32(SR);
-fps ← ZeroExtend32(FPSCR);
 op1 ← SignExtend32(Rm);
 IF (FpuIsDisabled(sr) AND IsDelaySlot())
 THROW SLOTFPUDIS;
diff --git a/sh4/FMOV @Rm,XDn b/sh4/FMOV @Rm,XDn
index b1b74a3..d4986b8 100644
--- a/sh4/FMOV @Rm,XDn	
+++ b/sh4/FMOV @Rm,XDn	
@@ -1,7 +1,6 @@
 1111nnn1mmmm1000
 Available only when PR=0 and SZ=1
 sr ← ZeroExtend32(SR);
-fps ← ZeroExtend32(FPSCR);
 op1 ← SignExtend32(Rm);
 IF (FpuIsDisabled(sr) AND IsDelaySlot())
 THROW SLOTFPUDIS;
diff --git a/sh4/FMOV DRm,@-Rn b/sh4/FMOV DRm,@-Rn
index c78644f..29e92a1 100644
--- a/sh4/FMOV DRm,@-Rn	
+++ b/sh4/FMOV DRm,@-Rn	
@@ -1,7 +1,6 @@
 1111nnnnmmm01011
 Available only when PR=0 and SZ=1
 sr ← ZeroExtend32(SR);
-fps ← ZeroExtend32(FPSCR);
 op1 ← FloatValuePair32(FP2m);
 op2 ← SignExtend32(Rn);
 IF (FpuIsDisabled(sr) AND IsDelaySlot())
diff --git a/sh4/FMOV DRm,@Rn b/sh4/FMOV DRm,@Rn
index e0cf5a7..9d8a599 100644
--- a/sh4/FMOV DRm,@Rn	
+++ b/sh4/FMOV DRm,@Rn	
@@ -1,7 +1,6 @@
 1111nnnnmmm01010
 Available only when PR=0 and SZ=1
 sr ← ZeroExtend32(SR);
-fps ← ZeroExtend32(FPSCR);
 op1 ← FloatValuePair32(FP2m);
 op2 ← SignExtend32(Rn);
 IF (FpuIsDisabled(sr) AND IsDelaySlot())
diff --git a/sh4/FMOV FRm,FRn b/sh4/FMOV FRm,FRn
index ee810f1..819d541 100644
--- a/sh4/FMOV FRm,FRn	
+++ b/sh4/FMOV FRm,FRn	
@@ -1,7 +1,6 @@
 1111nnnnmmmm1100
 Available only when SZ=0
 sr ← ZeroExtend32(SR);
-fps ← ZeroExtend32(FPSCR);
 op1 ← FloatValue32(FRm);
 IF (FpuIsDisabled(sr) AND IsDelaySlot())
 THROW SLOTFPUDIS;
diff --git a/sh4/FMOV XDm,@-Rn b/sh4/FMOV XDm,@-Rn
index d1fe6a8..55c5dfb 100644
--- a/sh4/FMOV XDm,@-Rn	
+++ b/sh4/FMOV XDm,@-Rn	
@@ -1,7 +1,6 @@
 1111nnnnmmm11011
 Available only when PR=0 and SZ=1
 sr ← ZeroExtend32(SR);
-fps ← ZeroExtend32(FPSCR);
 op1 ← FloatValuePair32(XD2m);
 op2 ← SignExtend32(Rn);
 IF (FpuIsDisabled(sr) AND IsDelaySlot())
@@ -12,4 +11,4 @@ address ← ZeroExtend32(op2 - 8);
 WriteMemoryPair32(address, op1);
 op2 ← address;
 Rn ← Register(op2);
-FPSCR ← ZeroExtend32(fps);
+
diff --git a/sh4/FMOV XDm,@Rn b/sh4/FMOV XDm,@Rn
index c5c5cc2..dc89888 100644
--- a/sh4/FMOV XDm,@Rn	
+++ b/sh4/FMOV XDm,@Rn	
@@ -1,7 +1,6 @@
 1111nnnnmmm11010
 Available only when PR=0 and SZ=1
 sr ← ZeroExtend32(SR);
-fps ← ZeroExtend32(FPSCR);
 op1 ← FloatValuePair32(XD2m);
 op2 ← SignExtend32(Rn);
 IF (FpuIsDisabled(sr) AND IsDelaySlot())
diff --git a/sh4/FMOV XDm,DRn b/sh4/FMOV XDm,DRn
index 8259b74..d62f542 100644
--- a/sh4/FMOV XDm,DRn	
+++ b/sh4/FMOV XDm,DRn	
@@ -1,7 +1,6 @@
 1111nnn0mmm11100
 Available only when PR=0 and SZ=1
 sr ← ZeroExtend32(SR);
-fps ← ZeroExtend32(FPSCR);
 op1 ← FloatValuePair32(XD2m);
 IF (FpuIsDisabled(sr) AND IsDelaySlot())
 THROW SLOTFPUDIS;
diff --git a/sh4/FMOV XDm,XDn b/sh4/FMOV XDm,XDn
index 341c6f1..852d359 100644
--- a/sh4/FMOV XDm,XDn	
+++ b/sh4/FMOV XDm,XDn	
@@ -1,7 +1,6 @@
 1111nnn1mmm11100
 Available only when PR=0 and SZ=1
 sr ← ZeroExtend32(SR);
-fps ← ZeroExtend32(FPSCR);
 op1 ← FloatValue64(XD2m);
 IF (FpuIsDisabled(sr) AND IsDelaySlot())
 THROW SLOTFPUDIS;
diff --git a/sh4/FMOV.S @(R0,Rm),FRn b/sh4/FMOV.S @(R0,Rm),FRn
index 7ae6cb0..b7b5417 100644
--- a/sh4/FMOV.S @(R0,Rm),FRn	
+++ b/sh4/FMOV.S @(R0,Rm),FRn	
@@ -8,5 +8,5 @@ THROW SLOTFPUDIS;
 IF (FpuIsDisabled(sr))
 THROW FPUDIS;
 address ← ZeroExtend32(r0 + op1);
-op2 ← ReadMemory32(address);
+op2 ← FloatValue32(ReadMemory32(address));
 FRn ← FloatRegister32(op2);
diff --git a/sh4/FMOV.S @Rm+,FRn b/sh4/FMOV.S @Rm+,FRn
index 8626fed..8121a6e 100644
--- a/sh4/FMOV.S @Rm+,FRn	
+++ b/sh4/FMOV.S @Rm+,FRn	
@@ -7,7 +7,7 @@ THROW SLOTFPUDIS;
 IF (FpuIsDisabled(sr))
 THROW FPUDIS;
 address ← ZeroExtend32(op1);
-op2 ← ReadMemory32(address);
+op2 ← FloatValue32(ReadMemory32(address));
 op1 ← op1 + 4;
 Rm ← Register(op1);
 FRn ← FloatRegister32(op2);
diff --git a/sh4/FMOV.S @Rm,FRn b/sh4/FMOV.S @Rm,FRn
index 71bce75..e379302 100644
--- a/sh4/FMOV.S @Rm,FRn	
+++ b/sh4/FMOV.S @Rm,FRn	
@@ -1,12 +1,11 @@
 1111nnnnmmmm1000
 Available only when SZ=0
 sr ← ZeroExtend32(SR);
-fps ← ZeroExtend32(FPSCR);
 op1 ← SignExtend32(Rm);
 IF (FpuIsDisabled(sr) AND IsDelaySlot())
 THROW SLOTFPUDIS;
 IF (FpuIsDisabled(sr))
 THROW FPUDIS;
 address ← ZeroExtend32(op1);
-op2 ← ReadMemory32(address);
+op2 ← FloatValue32(ReadMemory32(address));
 FRn ← FloatRegister32(op2);
diff --git a/sh4/FMOV.S FRm,@(R0,Rn) b/sh4/FMOV.S FRm,@(R0,Rn)
index 3d1f469..d67c6ba 100644
--- a/sh4/FMOV.S FRm,@(R0,Rn)	
+++ b/sh4/FMOV.S FRm,@(R0,Rn)	
@@ -9,4 +9,5 @@ THROW SLOTFPUDIS;
 IF (FpuIsDisabled(sr))
 THROW FPUDIS;
 address ← ZeroExtend32(r0 + op2);
-WriteMemory32(address, op1);
+value ← FloatRegister32(op1);
+WriteMemory32(address, value);
diff --git a/sh4/FMOV.S FRm,@-Rn b/sh4/FMOV.S FRm,@-Rn
index 38eb54d..0a190f7 100644
--- a/sh4/FMOV.S FRm,@-Rn	
+++ b/sh4/FMOV.S FRm,@-Rn	
@@ -1,7 +1,6 @@
 1111nnnnmmmm1011
 Available only when SZ=0
 sr ← ZeroExtend32(SR);
-fps ← ZeroExtend32(FPSCR);
 op1 ← FloatValue32(FRm);
 op2 ← SignExtend32(Rn);
 IF (FpuIsDisabled(sr) AND IsDelaySlot())
@@ -9,6 +8,7 @@ THROW SLOTFPUDIS;
 IF (FpuIsDisabled(sr))
 THROW FPUDIS;
 address ← ZeroExtend32(op2 - 4);
-WriteMemory32(address, op1);
+value ← FloatRegister32(op1);
+WriteMemory32(address, value);
 op2 ← address;
 Rn ← Register(op2);
diff --git a/sh4/FMOV.S FRm,@Rn b/sh4/FMOV.S FRm,@Rn
index d6ae317..fc5f56d 100644
--- a/sh4/FMOV.S FRm,@Rn	
+++ b/sh4/FMOV.S FRm,@Rn	
@@ -1,7 +1,6 @@
 1111nnnnmmmm1010
 Available only when SZ=0
 sr ← ZeroExtend32(SR);
-fps ← ZeroExtend32(FPSCR);
 op1 ← FloatValue32(FRm);
 op2 ← SignExtend32(Rn);
 IF (FpuIsDisabled(sr) AND IsDelaySlot())
@@ -9,4 +8,5 @@ THROW SLOTFPUDIS;
 IF (FpuIsDisabled(sr))
 THROW FPUDIS;
 address ← ZeroExtend32(op2);
-WriteMemory32(address, op1);
+value ← FloatRegister32(op1);
+WriteMemory32(address, value);
diff --git a/sh4/FNEG FRn b/sh4/FNEG FRn
index 48f0f7c..d463447 100644
--- a/sh4/FNEG FRn	
+++ b/sh4/FNEG FRn	
@@ -1,7 +1,6 @@
 1111nnnn01001101
 Available only when PR=0
 sr ← ZeroExtend32(SR);
-fps ← ZeroExtend32(FPSCR);
 op1 ← FloatValue32(FRn);
 IF (FpuIsDisabled(sr) AND IsDelaySlot())
 THROW SLOTFPUDIS;
diff --git a/sh4/FRCHG b/sh4/FRCHG
index 6a023a3..0642b64 100644
--- a/sh4/FRCHG
+++ b/sh4/FRCHG
@@ -1,10 +1,10 @@
 1111101111111101
 Available only when PR=0
 sr ← ZeroExtend32(SR);
-fr ← ZeroExtend1(SR.FR);
+fr ← ZeroExtend1(FPSCR.FR);
 IF (FpuIsDisabled(sr) AND IsDelaySlot())
 THROW SLOTFPUDIS;
 IF (FpuIsDisabled(sr))
 THROW FPUDIS;
 fr ← fr ⊕ 1;
-SR.FR ← Bit(fr);
+FPSCR.FR ← Bit(fr);
diff --git a/sh4/FSTS FPUL,FRn b/sh4/FSTS FPUL,FRn
index 6c21e69..d11a2b8 100644
--- a/sh4/FSTS FPUL,FRn	
+++ b/sh4/FSTS FPUL,FRn	
@@ -5,5 +5,5 @@ IF (FpuIsDisabled(sr) AND IsDelaySlot())
 THROW SLOTFPUDIS;
 IF (FpuIsDisabled(sr))
 THROW FPUDIS;
-op1 ← fpul;
+op1 ← FloatValue32(fpul);
 FRn ← FloatRegister32(op1);