smpc/input_intback.cpp: created
This commit is contained in:
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4
Makefile
4
Makefile
@ -1,5 +1,5 @@
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CFLAGS = -Isaturn
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OPT = -O0
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OPT = -Og
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LIBGCC = $(shell $(CC) -print-file-name=libgcc.a)
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all: raytracing/raytracing.iso vdp2/nbg0.iso
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@ -42,6 +42,8 @@ res/mai.data: res/mai00.data res/mai01.data res/mai02.data res/mai03.data res/ma
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vdp1/normal_sprite_animated.elf: vdp1/normal_sprite_animated.o res/mai.data.o res/mai.data.pal.o
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smpc/input_intback.elf: smpc/input_intback.o sh/lib1funcs.o
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# clean
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clean: clean-sh
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clean-sh:
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415
smpc/input_intback.cpp
Normal file
415
smpc/input_intback.cpp
Normal file
@ -0,0 +1,415 @@
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#include <stdint.h>
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#include "vdp1.h"
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#include "vdp2.h"
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#include "smpc.h"
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#include "sh2.h"
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#include "scu.h"
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struct color {
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uint8_t r;
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uint8_t g;
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uint8_t b;
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};
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const static color colors[16] = {
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{255, 255, 255}, // (SPD / transparent) 0
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{0, 255, 255}, // I (cyan) 1
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{255, 255, 0}, // O (yellow) 2
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{128, 0, 128}, // T (purple) 3
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{0, 255, 0}, // S (green) 4
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{0, 0, 255}, // J (blue) 5
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{255, 0, 0}, // Z (red) 6
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{255, 128, 0}, // L (orange) 7
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{0}, // 8
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{0}, // 9
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{0}, // 10 (a)
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{0}, // 11 (b)
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{0}, // 12 (c)
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{0}, // 13 (d)
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{0}, // 14 (e)
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{250, 128, 114} // (ECD) f
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};
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inline constexpr uint16_t rgb15(const color& color)
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{
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return ((color.b >> 3) << 10) // blue
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| ((color.g >> 3) << 5 ) // green
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| ((color.r >> 3) << 0 ); // red
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}
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uint32_t color_lookup_table(const uint32_t top)
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{
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// "The size of a color lookup table is 20H (32) bytes"
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// (assume top is already aligned to 0x20)
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const uint32_t table_address = top - 0x20;
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// "The color lookup table defines the respective color codes of 16 colors in
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// VRAM as 16-bit data"
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uint16_t * table = &vdp1.vram.u16[(table_address / 2)];
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uint32_t buf_ix = 0;
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for (uint32_t i = 0; i < 16; i++) {
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// there is a typo in "5.2 Color Lookup Tables" "If RGB code, MSB = 0"
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// should be "MSB = 1". The "MSB = 0" claim is correctly contradicted later.
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table[i] = 1 << 15 | rgb15(colors[i]);
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// _mai_data_pal is rgb24, 3 bytes per color
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buf_ix += 3;
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}
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return table_address;
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}
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template <class T>
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inline constexpr T round(const T n)
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{
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return (n + 0x20 - 1) & (-0x20);
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}
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constexpr uint32_t sprite_stride = 16;
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constexpr uint32_t sprite_height = 10;
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constexpr uint32_t sprite_width = 10;
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uint32_t character_pattern_table(const uint32_t top, int color)
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{
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constexpr uint32_t canvas_size = sprite_stride * 10;
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// 1 pixel = 4 bits
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constexpr uint32_t table_size = round(canvas_size / 2);
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const uint32_t table_address = top - table_size;
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uint32_t * table = &vdp1.vram.u32[(table_address / 4)];
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// `table_size` is in bytes; divide by two to get uint16_t indicies.
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uint32_t table_ix = 0;
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for (uint32_t row = 0; row < sprite_height; row++) {
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table[table_ix++] =
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(color << 28) | (color << 24) | (color << 20) | (color << 16)
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| (color << 12) | (color << 8 ) | (color << 4 ) | (color << 0 );
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// 0xf is the "end code" for 4-bit row/pixel data; there must be two
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// bit-consecutive codes for vdp2 to interpret it as an end code.
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constexpr int ecd = 0xf;
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table[table_ix++] =
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(color << 28) | (color << 24) | (ecd << 20) | (ecd << 16);
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}
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return table_address;
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}
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static inline const reg8& get_oreg(uint32_t ix) {
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switch (ix & 31) {
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default:
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case 0: return smpc.reg.OREG0;
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case 1: return smpc.reg.OREG1;
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case 2: return smpc.reg.OREG2;
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case 3: return smpc.reg.OREG3;
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case 4: return smpc.reg.OREG4;
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case 5: return smpc.reg.OREG5;
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case 6: return smpc.reg.OREG6;
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case 7: return smpc.reg.OREG7;
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case 8: return smpc.reg.OREG8;
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case 9: return smpc.reg.OREG9;
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case 10: return smpc.reg.OREG10;
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case 11: return smpc.reg.OREG11;
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case 12: return smpc.reg.OREG12;
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case 13: return smpc.reg.OREG13;
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case 14: return smpc.reg.OREG14;
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case 15: return smpc.reg.OREG15;
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case 16: return smpc.reg.OREG16;
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case 17: return smpc.reg.OREG17;
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case 18: return smpc.reg.OREG18;
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case 19: return smpc.reg.OREG19;
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case 20: return smpc.reg.OREG20;
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case 21: return smpc.reg.OREG21;
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case 22: return smpc.reg.OREG22;
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case 23: return smpc.reg.OREG23;
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case 24: return smpc.reg.OREG24;
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case 25: return smpc.reg.OREG25;
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case 26: return smpc.reg.OREG26;
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case 27: return smpc.reg.OREG27;
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case 28: return smpc.reg.OREG28;
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case 29: return smpc.reg.OREG29;
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case 30: return smpc.reg.OREG30;
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case 31: return smpc.reg.OREG31;
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}
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}
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struct controller_state {
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uint8_t up;
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uint8_t down;
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uint8_t left;
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uint8_t right;
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};
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#define assert(n) if ((n) == 0) while (1);
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enum intback_fsm {
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PORT_STATUS = 0,
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PERIPHERAL_ID,
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DATA1,
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DATA2,
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FSM_NEXT,
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};
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struct intback_state {
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int fsm;
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int controller_ix;
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int port_ix;
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controller_state controller[2];
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};
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static intback_state intback;
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static int oreg_ix;
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struct xy {
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int x;
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int y;
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};
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static xy foo[2] = {
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{100, 100},
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{200, 100}
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};
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void smpc_int(void) __attribute__ ((interrupt_handler));
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void smpc_int(void) {
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scu.reg.IST &= ~(IST__SMPC);
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scu.reg.IMS = ~(IMS__SMPC | IMS__V_BLANK_IN);
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if ((smpc.reg.SR & SR__PDL) != 0) {
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// PDL == 1; 1st peripheral data
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oreg_ix = 0;
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intback.controller_ix = 0;
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intback.port_ix = 0;
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intback.fsm = PORT_STATUS;
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}
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int port_connected = 0;
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/*
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This intback handling is oversimplified:
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- up to 2 controllers may be connected
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- controller port 1 must be connected (could relax this)
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- both controllers must be "digital pad" controllers
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*/
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while (oreg_ix < 31) {
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const reg8& oreg = get_oreg(oreg_ix++);
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switch (intback.fsm++) {
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case PORT_STATUS:
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port_connected = (PORT_STATUS__CONNECTORS(oreg) == 1);
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break;
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case PERIPHERAL_ID:
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if (port_connected) {
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assert(PERIPHERAL_ID__IS_DIGITAL_PAD(oreg));
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assert(PERIPHERAL_ID__DATA_SIZE(oreg) == 2);
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}
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break;
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case DATA1:
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if (port_connected) {
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controller_state& c = intback.controller[intback.controller_ix];
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c.right = (DIGITAL__1__RIGHT & oreg) == 0;
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c.left = (DIGITAL__1__LEFT & oreg) == 0;
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c.down = (DIGITAL__1__DOWN & oreg) == 0;
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c.up = (DIGITAL__1__UP & oreg) == 0;
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}
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break;
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case DATA2:
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// ignore data2
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break;
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}
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if (intback.fsm == FSM_NEXT) {
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if (intback.port_ix == 1)
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break;
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else {
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intback.port_ix++;
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intback.controller_ix++;
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intback.fsm = PORT_STATUS;
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}
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}
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}
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if ((smpc.reg.SR & SR__NPE) != 0) {
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smpc.reg.IREG0 = INTBACK__IREG0__CONTINUE;
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} else {
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smpc.reg.IREG0 = INTBACK__IREG0__BREAK;
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}
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}
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void v_blank_in_int(void) __attribute__ ((interrupt_handler));
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void v_blank_in_int() {
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scu.reg.IST &= ~(IST__V_BLANK_IN);
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scu.reg.IMS = ~(IMS__SMPC | IMS__V_BLANK_IN);
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sh2.reg.FRC.H = 0;
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sh2.reg.FRC.L = 0;
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sh2.reg.FTCSR = 0; // clear flags
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for (int i = 0; i < 2; i++) {
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const controller_state& c = intback.controller[i];
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if (c.left) vdp1.vram.cmd[2 + i].XA = --foo[i].x;
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if (c.right) vdp1.vram.cmd[2 + i].XA = ++foo[i].x;
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if (c.up) vdp1.vram.cmd[2 + i].YA = --foo[i].y;
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if (c.down) vdp1.vram.cmd[2 + i].YA = ++foo[i].y;
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}
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// wait 300us, as specified in the SMPC manual.
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// It appears reading FRC.H is mandatory and *must* occur before FRC.L on real
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// hardware.
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while ((sh2.reg.FTCSR & FTCSR__OVF) == 0 && sh2.reg.FRC.H == 0 && sh2.reg.FRC.L < 63);
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if ((vdp2.reg.TVSTAT & TVSTAT__VBLANK) != 0) {
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// on real hardware, SF contains uninitialized garbage bits other than the
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// lsb.
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while ((smpc.reg.SF & 1) != 0);
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smpc.reg.SF = 0;
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smpc.reg.IREG0 = INTBACK__IREG0__STATUS_DISABLE;
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smpc.reg.IREG1 = ( INTBACK__IREG1__PERIPHERAL_DATA_ENABLE
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| INTBACK__IREG1__PORT2_15BYTE
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| INTBACK__IREG1__PORT1_15BYTE
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);
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smpc.reg.IREG2 = INTBACK__IREG2__MAGIC;
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smpc.reg.COMREG = COMREG__INTBACK;
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}
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}
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static inline void v_blank_in() {
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/*
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v
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_____
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____| |____
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*/
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while ((vdp2.reg.TVSTAT & TVSTAT__VBLANK) != 0);
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while ((vdp2.reg.TVSTAT & TVSTAT__VBLANK) == 0);
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}
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void main()
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{
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uint32_t color_address, character_address[16];
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uint32_t top = (sizeof (union vdp1_vram));
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top = color_address = color_lookup_table(top);
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top = character_address[0] = character_pattern_table(top, 1);
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top = character_address[1] = character_pattern_table(top, 2);
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// wait for the beginning of a V blank
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v_blank_in();
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// DISP: Please make sure to change this bit from 0 to 1 during V blank.
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vdp2.reg.TVMD = ( TVMD__DISP | TVMD__LSMD__NON_INTERLACE
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| TVMD__VRESO__240 | TVMD__HRESO__NORMAL_320);
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// disable all VDP2 backgrounds (e.g: the Sega bios logo)
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vdp2.reg.BGON = 0;
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// zeroize BACK color
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vdp2.reg.BKTAU = 0;
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vdp2.reg.BKTAL = 0;
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vdp2.vram.u16[0] = 0;
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// VDP2 User's Manual:
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// "When sprite data is in an RGB format, sprite register 0 is selected"
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// "When the value of a priority number is 0h, it is read as transparent"
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//
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// From a VDP2 perspective: in VDP1 16-color lookup table mode, VDP1 is still
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// sending RGB data to VDP2. This sprite color data as configured in
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// `color_lookup_table` from a VDP2 priority perspective uses sprite register 0.
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//
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// The power-on value of PRISA is zero. Set the priority for sprite register 0
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// to some number greater than zero, so that the color data is not interpreted
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// as "transparent".
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vdp2.reg.PRISA = PRISA__S0PRIN(1); // Sprite register 0 PRIority Number
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/* TVM settings must be performed from the second H-blank IN interrupt after the
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V-blank IN interrupt to the H-blank IN interrupt immediately after the V-blank
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OUT interrupt. */
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// "normal" display resolution, 16 bits per pixel, 512x256 framebuffer
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vdp1.reg.TVMR = TVMR__TVM__NORMAL;
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// swap framebuffers every 1 cycle; non-interlace
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vdp1.reg.FBCR = 0;
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// during a framebuffer erase cycle, write the color "black" to each pixel
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constexpr uint16_t black = 0x0000;
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vdp1.reg.EWDR = black;
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// the EWLR/EWRR macros use somewhat nontrivial math for the X coordinates
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// erase upper-left coordinate
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vdp1.reg.EWLR = EWLR__16BPP_X1(0) | EWLR__Y1(0);
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// erase lower-right coordinate
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vdp1.reg.EWRR = EWRR__16BPP_X3(319) | EWRR__Y3(239);
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vdp1.vram.cmd[0].CTRL = CTRL__JP__JUMP_NEXT | CTRL__COMM__SYSTEM_CLIP_COORDINATES;
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vdp1.vram.cmd[0].LINK = 0;
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vdp1.vram.cmd[0].XC = 319;
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vdp1.vram.cmd[0].YC = 239;
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vdp1.vram.cmd[1].CTRL = CTRL__JP__JUMP_NEXT | CTRL__COMM__LOCAL_COORDINATE;
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vdp1.vram.cmd[1].LINK = 0;
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vdp1.vram.cmd[1].XA = 0;
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vdp1.vram.cmd[1].YA = 0;
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vdp1.vram.cmd[2].CTRL = CTRL__JP__JUMP_NEXT | CTRL__COMM__NORMAL_SPRITE;
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vdp1.vram.cmd[2].LINK = 0;
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// The "end code" is 0xf, which is being used in the mai sprite palette. If
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// both transparency and end codes are enabled, it seems there are only 14
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// usable colors in the 4-bit color mode.
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vdp1.vram.cmd[2].PMOD = PMOD__COLOR_MODE__LOOKUP_TABLE_16;
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// It appears Kronos does not correctly calculate the color address in the
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// VDP1 debugger. Kronos will report FFFC when the actual color table address
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// in this example is 7FFE0.
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vdp1.vram.cmd[2].COLR = COLR__ADDRESS(color_address); // non-palettized (rgb15) color data
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vdp1.vram.cmd[2].SRCA = SRCA(character_address[0]);
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vdp1.vram.cmd[2].SIZE = SIZE__X(sprite_stride) | SIZE__Y(sprite_height);
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vdp1.vram.cmd[2].XA = foo[0].x;
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vdp1.vram.cmd[2].YA = foo[0].y;
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vdp1.vram.cmd[3].CTRL = CTRL__JP__JUMP_NEXT | CTRL__COMM__NORMAL_SPRITE;
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vdp1.vram.cmd[3].LINK = 0;
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// The "end code" is 0xf, which is being used in the mai sprite palette. If
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// both transparency and end codes are enabled, it seems there are only 14
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// usable colors in the 4-bit color mode.
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vdp1.vram.cmd[3].PMOD = PMOD__COLOR_MODE__LOOKUP_TABLE_16;
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// It appears Kronos does not correctly calculate the color address in the
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// VDP1 debugger. Kronos will report FFFC when the actual color table address
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// in this example is 7FFE0.
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vdp1.vram.cmd[3].COLR = COLR__ADDRESS(color_address); // non-palettized (rgb15) color data
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vdp1.vram.cmd[3].SRCA = SRCA(character_address[1]);
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vdp1.vram.cmd[3].SIZE = SIZE__X(sprite_stride) | SIZE__Y(sprite_height);
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vdp1.vram.cmd[3].XA = foo[1].x;
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vdp1.vram.cmd[3].YA = foo[1].y;
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vdp1.vram.cmd[4].CTRL = CTRL__END;
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// start drawing (execute the command list) on every frame
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vdp1.reg.PTMR = PTMR__PTM__FRAME_CHANGE;
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// free-running timer
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sh2.reg.TCR = TCR__CKS__INTERNAL_DIV128;
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sh2.reg.FTCSR = 0;
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// initialize smpc
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smpc.reg.DDR1 = 0; // INPUT
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smpc.reg.DDR2 = 0; // INPUT
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smpc.reg.IOSEL = 0; // SMPC control
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smpc.reg.EXLE = 0; //
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// interrupts
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sh2_vec[SCU_VEC__SMPC] = (u32)(&smpc_int);
|
||||
sh2_vec[SCU_VEC__V_BLANK_IN] = (u32)(&v_blank_in_int);
|
||||
|
||||
scu.reg.IST = 0;
|
||||
scu.reg.IMS = ~(IMS__SMPC | IMS__V_BLANK_IN);
|
||||
}
|
||||
|
||||
extern "C"
|
||||
void start(void)
|
||||
{
|
||||
main();
|
||||
while (1);
|
||||
}
|
||||
Loading…
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Reference in New Issue
Block a user