19 lines
1.5 KiB
Plaintext
19 lines
1.5 KiB
Plaintext
Field Name Bits Description
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PVS_DST_OPCODE 5:0 Selects the Operation which is to be performed.
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PVS_DST_MATH_INST 6 Specifies a Math Engine Operation
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PVS_DST_MACRO_INST 7 Specifies a Macro Operation
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PVS_DST_REG_TYPE 11:8 Defines the Memory Select (Register Type) for the Dest Operand.
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PVS_DST_ADDR_MODE_1 12 Combine ADDR_MODE_1 (msb) with ADDR_MODE_0 (lsb) to form 2-bit ADDR_MODE
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PVS_DST_OFFSET 19:13 Vector Offset into the Selected Memory
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PVS_DST_WE_X 20 Write Enable for X Component
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PVS_DST_WE_Y 21 Write Enable for Y Component
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PVS_DST_WE_Z 22 Write Enable for Z Component
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PVS_DST_WE_W 23 Write Enable for W Component
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PVS_DST_VE_SAT 24 Vector engine operation is saturate clamped between 0 and 1 (all components)
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PVS_DST_ME_SAT 25 Math engine operation is saturate clamped between 0 and 1 (all components)
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PVS_DST_PRED_ENABLE 26 Operation is predicated – Operation writes if predicate bit matches predicate sense.
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PVS_DST_PRED_SENSE 27 Operation predication sense – If set, operation writes if predicate bit is set. If reset, operation writes if predicate bit is reset.
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PVS_DST_DUAL_MATH_OP 28 Set to describe a dual-math op.
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PVS_DST_ADDR_SEL 30:29 When PVS_DST_ADDR_MODE is set, this selects which component of the 4-component address register to use.
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PVS_DST_ADDR_MODE_0 31 Combine ADDR_MODE_1 (msb) with ADDR_MODE_0 (lsb) to form 2-bit ADDR_MODE
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