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assembler/fs/emitter: set default float addr if unspecified

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This commit is contained in:
Zack Buhman 2025-10-20 18:33:13 -05:00
parent efecb277c8
commit 3df0aed6ba
2 changed files with 25 additions and 32 deletions
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48
regs/assembler/fs/emitter.py
View File

@ -137,38 +137,26 @@ def emit_rgb_op(code, rgb_op):
mod_func(code, sel.mod) mod_func(code, sel.mod)
def emit_addr(code, addr): def emit_addr(code, addr):
if addr.alpha.src0 is not None: srcs = [
is_const = int(addr.alpha.src0.type is SrcAddrType.const) (addr.alpha.src0 , US_ALU_ALPHA_ADDR.ADDR0 , US_ALU_ALPHA_ADDR.ADDR0_CONST),
is_float = int(addr.alpha.src0.type is SrcAddrType.float) (addr.alpha.src1 , US_ALU_ALPHA_ADDR.ADDR1 , US_ALU_ALPHA_ADDR.ADDR1_CONST),
US_ALU_ALPHA_ADDR.ADDR0(code, (is_float << 7) | addr.alpha.src0.value) (addr.alpha.src2 , US_ALU_ALPHA_ADDR.ADDR2 , US_ALU_ALPHA_ADDR.ADDR2_CONST),
US_ALU_ALPHA_ADDR.ADDR0_CONST(code, is_const) (addr.rgb.src0 , US_ALU_RGB_ADDR.ADDR0 , US_ALU_RGB_ADDR.ADDR0_CONST),
if addr.alpha.src1 is not None: (addr.rgb.src1 , US_ALU_RGB_ADDR.ADDR1 , US_ALU_RGB_ADDR.ADDR1_CONST),
is_const = int(addr.alpha.src1.type is SrcAddrType.const) (addr.rgb.src2 , US_ALU_RGB_ADDR.ADDR2 , US_ALU_RGB_ADDR.ADDR2_CONST),
is_float = int(addr.alpha.src1.type is SrcAddrType.float) ]
US_ALU_ALPHA_ADDR.ADDR1(code, (is_float << 7) | addr.alpha.src1.value)
US_ALU_ALPHA_ADDR.ADDR1_CONST(code, is_const) for src, ADDR, ADDR_CONST in srcs:
if addr.alpha.src2 is not None: if src is not None:
is_const = int(addr.alpha.src2.type is SrcAddrType.const) is_const = int(src.type is SrcAddrType.const)
is_float = int(addr.alpha.src2.type is SrcAddrType.float) is_float = int(src.type is SrcAddrType.float)
US_ALU_ALPHA_ADDR.ADDR2(code, (is_float << 7) | addr.alpha.src2.value) ADDR(code, (is_float << 7) | addr.alpha.src0.value)
US_ALU_ALPHA_ADDR.ADDR2_CONST(code, is_const) ADDR_CONST(code, is_const)
else:
ADDR(code, (1 << 7) | 0)
if addr.alpha.srcp is not None: if addr.alpha.srcp is not None:
US_ALU_ALPHA_ADDR.SRCP_OP(code, addr.alpha.srcp.value) US_ALU_ALPHA_ADDR.SRCP_OP(code, addr.alpha.srcp.value)
if addr.rgb.src0 is not None:
is_const = int(addr.rgb.src0.type is SrcAddrType.const)
is_float = int(addr.rgb.src0.type is SrcAddrType.float)
US_ALU_RGB_ADDR.ADDR0(code, (is_float << 7) | addr.rgb.src0.value)
US_ALU_RGB_ADDR.ADDR0_CONST(code, is_const)
if addr.rgb.src1 is not None:
is_const = int(addr.rgb.src1.type is SrcAddrType.const)
is_float = int(addr.rgb.src1.type is SrcAddrType.float)
US_ALU_RGB_ADDR.ADDR1(code, (is_float << 7) | addr.rgb.src1.value)
US_ALU_RGB_ADDR.ADDR1_CONST(code, is_const)
if addr.rgb.src2 is not None:
is_const = int(addr.rgb.src2.type is SrcAddrType.const)
is_float = int(addr.rgb.src2.type is SrcAddrType.float)
US_ALU_RGB_ADDR.ADDR2(code, (is_float << 7) | addr.rgb.src2.value)
US_ALU_RGB_ADDR.ADDR2_CONST(code, is_const)
if addr.rgb.srcp is not None: if addr.rgb.srcp is not None:
US_ALU_RGB_ADDR.SRCP_OP(code, addr.rgb.srcp.value) US_ALU_RGB_ADDR.SRCP_OP(code, addr.rgb.srcp.value)

9
regs/us_disassemble.py
View File

@ -101,8 +101,7 @@ def disassemble(code, ix):
field_pv_name = get_field_pv_name(value, d) field_pv_name = get_field_pv_name(value, d)
yield ' '.join([d.field_name.ljust(max_length), f"{field_pv_name}"]) yield ' '.join([d.field_name.ljust(max_length), f"{field_pv_name}"])
def inner(register_name_list): def inner_columns(register_name_list):
columns = [] columns = []
for i, register_name in enumerate(register_name_list): for i, register_name in enumerate(register_name_list):
columns.append(list(inner2(i, register_name))) columns.append(list(inner2(i, register_name)))
@ -124,6 +123,12 @@ def disassemble(code, ix):
]) ])
print(" ", row) print(" ", row)
def inner_rows(register_name_list):
for i, register_name in enumerate(register_name_list):
print('\n'.join(inner2(i, register_name)))
inner = inner_rows
inst_type = get_field_pv_name(us_cmn_inst, US_CMN_INST["TYPE"]) inst_type = get_field_pv_name(us_cmn_inst, US_CMN_INST["TYPE"])
if inst_type in {"US_INST_TYPE_OUT", "US_INST_TYPE_ALU"}: if inst_type in {"US_INST_TYPE_OUT", "US_INST_TYPE_ALU"}:
inner(alu_output) inner(alu_output)