6.9 KiB
6.9 KiB
1 | block | offset | address | size | name | r/w | description |
---|---|---|---|---|---|---|---|
2 | CCN | 00 | 0000 | 4 | PTEH | RW | Page table entry high register |
3 | CCN | 00 | 0004 | 4 | PTEL | RW | Page table entry low register |
4 | CCN | 00 | 0008 | 4 | TTB | RW | Translation table base register |
5 | CCN | 00 | 000c | 4 | TEA | RW | TLB exception address register |
6 | CCN | 00 | 0010 | 4 | MMUCR | RW | MMU control register |
7 | CCN | 00 | 0014 | 1 | BASRA | RW | Break ASID register A |
8 | CCN | 00 | 0018 | 1 | BASRB | RW | Break ASID register B |
9 | CCN | 00 | 001c | 4 | CCR | RW | Cache control register |
10 | CCN | 00 | 0020 | 4 | TRA | RW | TRAPA exception register |
11 | CCN | 00 | 0024 | 4 | EXPEVT | RW | Exception event register |
12 | CCN | 00 | 0028 | 4 | INTEVT | RW | Interrupt event register |
13 | CCN | 00 | 0034 | 4 | PTEA | RW | Page table entry assistance register |
14 | CCN | 00 | 0038 | 4 | QACR0 | RW | Queue address control register 0 |
15 | CCN | 00 | 003c | 4 | QACR1 | RW | Queue address control register 1 |
16 | |||||||
17 | UBC | 20 | 0000 | 4 | BARA | RW | Break address register A |
18 | UBC | 20 | 0004 | 1 | BAMRA | RW | Break address mask register A |
19 | UBC | 20 | 0008 | 2 | BBRA | RW | Break bus cycle register A |
20 | UBC | 20 | 000c | 4 | BARB | RW | Break address register B |
21 | UBC | 20 | 0010 | 1 | BAMRB | RW | Break address mask register B |
22 | UBC | 20 | 0014 | 2 | BBRB | RW | Break bus cycle register B |
23 | UBC | 20 | 0018 | 4 | BDRB | RW | Break data register B |
24 | UBC | 20 | 001c | 4 | BDMRB | RW | Break data mask register B |
25 | UBC | 20 | 0020 | 2 | BRCR | RW | Break control register |
26 | |||||||
27 | BSC | 80 | 0000 | 4 | BCR1 | RW | Bus control register 1 |
28 | BSC | 80 | 0004 | 2 | BCR2 | RW | Bus control register 2 |
29 | BSC | 80 | 0008 | 4 | WCR1 | RW | Wait state control register 1 |
30 | BSC | 80 | 000c | 4 | WCR2 | RW | Wait state control register 2 |
31 | BSC | 80 | 0010 | 4 | WCR3 | RW | Wait state control register 3 |
32 | BSC | 80 | 0014 | 4 | MCR | RW | Memory control register |
33 | BSC | 80 | 0018 | 2 | PCR | RW | PCMCIA control register |
34 | BSC | 80 | 001c | 2 | RTCSR | RW | Refresh timer control/status register |
35 | BSC | 80 | 0020 | 2 | RTCNT | RW | Refresh timer counter |
36 | BSC | 80 | 0024 | 2 | RTCOR | RW | Refresh timer constant counter |
37 | BSC | 80 | 0028 | 2 | RFCR | RW | Refresh count register |
38 | BSC | 80 | 002c | 4 | PCTRA | RW | Port control register A |
39 | BSC | 80 | 0030 | 2 | PDTRA | RW | Port data register A |
40 | BSC | 80 | 0040 | 4 | PCTRB | RW | Port control register B |
41 | BSC | 80 | 0044 | 2 | PDTRB | RW | Port data register B |
42 | BSC | 80 | 0048 | 2 | GPIOIC | RW | GPIO interrupt control register |
43 | BSC | 90 | 0000 | 65536 | SDMR2 | W | Synchronous DRAM mode registers |
44 | BSC | 94 | 0000 | 65536 | SDMR3 | W | Synchronous DRAM mode registers |
45 | |||||||
46 | DMAC | a0 | 0000 | 4 | SAR0 | RW | DMA source address register 0 |
47 | DMAC | a0 | 0004 | 4 | DAR0 | RW | DMA destination address register 0 |
48 | DMAC | a0 | 0008 | 4 | DMATCR0 | RW | DMA transfer count register 0 |
49 | DMAC | a0 | 000c | 4 | CHCR0 | RW | DMA control register 0 |
50 | DMAC | a0 | 0010 | 4 | SAR1 | RW | DMA source address register 1 |
51 | DMAC | a0 | 0014 | 4 | DAR1 | RW | DMA destination address register 1 |
52 | DMAC | a0 | 0018 | 4 | DMATCR1 | RW | DMA transfer count register 1 |
53 | DMAC | a0 | 001c | 4 | CHCR1 | RW | DMA control register 1 |
54 | DMAC | a0 | 0020 | 4 | SAR2 | RW | DMA source address register 2 |
55 | DMAC | a0 | 0024 | 4 | DAR2 | RW | DMA destination address register 2 |
56 | DMAC | a0 | 0028 | 4 | DMATCR2 | RW | DMA transfer count register 2 |
57 | DMAC | a0 | 002c | 4 | CHCR2 | RW | DMA control register 2 |
58 | DMAC | a0 | 0030 | 4 | SAR3 | RW | DMA source address register 3 |
59 | DMAC | a0 | 0034 | 4 | DAR3 | RW | DMA destination address register 3 |
60 | DMAC | a0 | 0038 | 4 | DMATCR3 | RW | DMA transfer count register 3 |
61 | DMAC | a0 | 003c | 4 | CHCR3 | RW | DMA control register 3 |
62 | DMAC | a0 | 0040 | 4 | DMAOR | RW | DMA operation register |
63 | |||||||
64 | CPG | c0 | 0000 | 2 | FRQCR | RW | Frequency control register |
65 | CPG | c0 | 0004 | 1 | STBCR | RW | Standby control register |
66 | CPG | c0 | 0008 | 2 | WTCNT | RW | Watchdog timer counter |
67 | CPG | c0 | 000c | 2 | WTCSR | RW | Watchdog timer control/status register |
68 | CPG | c0 | 0010 | 1 | STBCR2 | RW | Standby control register 2 |
69 | |||||||
70 | RTC | c8 | 0000 | 1 | R64CNT | R | 64 Hz counter |
71 | RTC | c8 | 0004 | 1 | RSECCNT | RW | Second counter |
72 | RTC | c8 | 0008 | 1 | RMINCNT | RW | Minute counter |
73 | RTC | c8 | 000c | 1 | RHRCNT | RW | Hour counter |
74 | RTC | c8 | 0010 | 1 | RWKCNT | RW | Day-of-week counter |
75 | RTC | c8 | 0014 | 1 | RDAYCNT | RW | Day counter |
76 | RTC | c8 | 0018 | 1 | RMONCNT | RW | Month counter |
77 | RTC | c8 | 001c | 2 | RYRCNT | RW | Year counter |
78 | RTC | c8 | 0020 | 1 | RSECAR | RW | Second alarm register |
79 | RTC | c8 | 0024 | 1 | RMINAR | RW | Minute alarm register |
80 | RTC | c8 | 0028 | 1 | RHRAR | RW | Hour alarm register |
81 | RTC | c8 | 002c | 1 | RWKAR | RW | Day-of-week alarm register |
82 | RTC | c8 | 0030 | 1 | RDAYAR | RW | Day alarm register |
83 | RTC | c8 | 0034 | 1 | RMONAR | RW | Month alarm register |
84 | RTC | c8 | 0038 | 1 | RCR1 | RW | RTC control register 1 |
85 | RTC | c8 | 003c | 1 | RCR2 | RW | RTC control register 2 |
86 | |||||||
87 | INTC | d0 | 0000 | 2 | ICR | RW | Interrupt control register |
88 | INTC | d0 | 0004 | 2 | IPRA | RW | Interrupt priority register A |
89 | INTC | d0 | 0008 | 2 | IPRB | RW | Interrupt priority register B |
90 | INTC | d0 | 000c | 2 | IPRC | RW | Interrupt priority register C |
91 | |||||||
92 | TMU | d8 | 0000 | 1 | TOCR | RW | Timer output control register |
93 | TMU | d8 | 0004 | 1 | TSTR | RW | Timer start register |
94 | TMU | d8 | 0008 | 4 | TCOR0 | RW | Timer constant register 0 |
95 | TMU | d8 | 000c | 4 | TCNT0 | RW | Timer counter 0 |
96 | TMU | d8 | 0010 | 2 | TCR0 | RW | Timer control register 0 |
97 | TMU | d8 | 0014 | 4 | TCOR1 | RW | Timer constant register 1 |
98 | TMU | d8 | 0018 | 4 | TCNT1 | RW | Timer counter 1 |
99 | TMU | d8 | 001c | 2 | TCR1 | RW | Timer control register 1 |
100 | TMU | d8 | 0020 | 4 | TCOR2 | RW | Timer constant register 2 |
101 | TMU | d8 | 0024 | 4 | TCNT2 | RW | Timer counter 2 |
102 | TMU | d8 | 0028 | 2 | TCR2 | RW | Timer control register 2 |
103 | TMU | d8 | 002c | 4 | TCPR2 | R | Timer input capture register 2 |
104 | |||||||
105 | SCI | e0 | 0000 | 1 | SCSMR1 | RW | Serial mode register 1 |
106 | SCI | e0 | 0004 | 1 | SCBRR1 | RW | Bit rate register 1 |
107 | SCI | e0 | 0008 | 1 | SCSCR1 | RW | Serial control register 1 |
108 | SCI | e0 | 000c | 1 | SCTDR1 | RW | Transmit data register 1 |
109 | SCI | e0 | 0010 | 1 | SCSSR1 | RW | Serial status register 1 |
110 | SCI | e0 | 0014 | 1 | SCRDR1 | R | Receive data register 1 |
111 | SCI | e0 | 0018 | 1 | SCSCMR1 | RW | Smart card mode register 1 |
112 | SCI | e0 | 001c | 1 | SCSPTR1 | RW | Serial port register |
113 | |||||||
114 | SCIF | e8 | 0000 | 2 | SCSMR2 | RW | Serial mode register 2 |
115 | SCIF | e8 | 0004 | 1 | SCBRR2 | RW | Bit rate register 2 |
116 | SCIF | e8 | 0008 | 2 | SCSCR2 | RW | Serial control register 2 |
117 | SCIF | e8 | 000c | 1 | SCFTDR2 | W | Transmit FIFO data register 2 |
118 | SCIF | e8 | 0010 | 2 | SCFSR2 | RW | Serial status register 2 |
119 | SCIF | e8 | 0014 | 1 | SCFRDR2 | R | Receive FIFO data register 2 |
120 | SCIF | e8 | 0018 | 2 | SCFCR2 | RW | FIFO control register |
121 | SCIF | e8 | 001c | 2 | SCFDR2 | R | FIFO data count register |
122 | SCIF | e8 | 0020 | 2 | SCSPTR2 | RW | Serial port register 2 |
123 | SCIF | e8 | 0024 | 2 | SCLSR2 | RW | Line status register 2 |
124 | |||||||
125 | UDI | f0 | 0000 | 2 | SDIR | R | Instruction register |
126 | UDI | f0 | 0008 | 4 | SDDR | R | Data register |