dreamcast/dreamcast2/regs/systembus/systembus.csv

1	block	address	size	name	r/w	description
2	SYSTEMBUS	000	4	C2DSTAT	RW	CH2-DMA destination address
3	SYSTEMBUS	004	4	C2DLEN	RW	CH2-DMA length
4	SYSTEMBUS	008	4	C2DST	RW	CH2-DMA start
5
6	SYSTEMBUS	010	4	SDSTAW	RW	Sort-DMA start link table address
7	SYSTEMBUS	014	4	SDBAAW	RW	Sort-DMA link base address
8	SYSTEMBUS	018	4	SDWLT	RW	Sort-DMA link address bit width
9	SYSTEMBUS	01c	4	SDLAS	RW	Sort-DMA link address shift control
10	SYSTEMBUS	020	4	SDST	RW	Sort-DMA start
11
12	SYSTEMBUS	040	4	DBREQM	RW	DBREQ# signal mask control
13	SYSTEMBUS	044	4	BAVLWC	RW	BAVL# signal wait count
14	SYSTEMBUS	048	4	C2DPYRC	RW	DMA (TA/Root Bus) priority count
15	SYSTEMBUS	04c	4	DMAXL	RW	CH2-DMA maximum burst length
16
17	SYSTEMBUS	080	4	TFREM	R	TA FIFO remaining amount
18	SYSTEMBUS	084	4	LMMODE0	RW	Via TA texture memory bus select 0
19	SYSTEMBUS	088	4	LMMODE1	RW	Via TA texture memory bus select 1
20	SYSTEMBUS	08c	4	FFST	R	FIFO status
21	SYSTEMBUS	090	4	SFRES	W	System reset
22
23	SYSTEMBUS	09c	4	SBREV	R	System bus revision number
24	SYSTEMBUS	0a0	4	RBSPLT	RW	SH4 Root Bus split enable
25
26	SYSTEMBUS	100	4	ISTNRM	RW	Normal interrupt status
27	SYSTEMBUS	104	4	ISTEXT	R	External interrupt status
28	SYSTEMBUS	108	4	ISTERR	RW	Error interrupt status
29
30	SYSTEMBUS	110	4	IML2NRM	RW	Level 2 normal interrupt mask
31	SYSTEMBUS	114	4	IML2EXT	RW	Level 2 external interrupt mask
32	SYSTEMBUS	118	4	IML2ERR	RW	Level 2 error interrupt mask
33
34	SYSTEMBUS	120	4	IML4NRM	RW	Level 4 normal interrupt mask
35	SYSTEMBUS	124	4	IML4EXT	RW	Level 4 external interrupt mask
36	SYSTEMBUS	128	4	IML4ERR	RW	Level 4 error interrupt mask
37
38	SYSTEMBUS	130	4	IML6NRM	RW	Level 6 normal interrupt mask
39	SYSTEMBUS	134	4	IML6EXT	RW	Level 6 external interrupt mask
40	SYSTEMBUS	138	4	IML6ERR	RW	Level 6 error interrupt mask
41
42	SYSTEMBUS	140	4	PDTNRM	RW	Normal interrupt PVR-DMA startup mask
43	SYSTEMBUS	144	4	PDTEXT	RW	External interrupt PVR-DMA startup mask
44
45	SYSTEMBUS	150	4	G2DTNRM	RW	Normal interrupt G2-DMA startup mask
46	SYSTEMBUS	154	4	G2DTEXT	RW	External interrupt G2-DMA startup mask
47
48	MAPLE_IF	04	4	MDSTAR	RW	Maple-DMA command table address
49
50	MAPLE_IF	10	4	MDTSEL	RW	Maple-DMA trigger select
51	MAPLE_IF	14	4	MDEN	RW	Maple-DMA enable
52	MAPLE_IF	18	4	MDST	RW	Maple-DMA start
53
54	MAPLE_IF	80	4	MSYS	RW	Maple system control
55	MAPLE_IF	84	4	MST	R	Maple status
56	MAPLE_IF	88	4	MSHTCL	W	Maple-DMA hard trigger clear
57	MAPLE_IF	8c	4	MDAPRO	W	Maple-DMA address range
58
59	MAPLE_IF	e8	4	MMSEL	RW	Maple MSP selection
60
61	MAPLE_IF	f4	4	MTXDAD	R	Maple TXD address counter
62	MAPLE_IF	f8	4	MRXDAD	R	Maple RXD address counter
63	MAPLE_IF	fc	4	MRXDBD	R	Maple RXD address base
64
65	G1_IF	04	4	GDSTAR	RW	GD-DMA start address
66	G1_IF	08	4	GDLEN	RW	GD-DMA length
67	G1_IF	0c	4	GDDIR	RW	GD-DMA direction
68
69	G1_IF	14	4	GDEN	RW	GD-DMA enable
70	G1_IF	18	4	GDST	RW	GD-DMA start
71
72	G1_IF	80	4	G1RRC	W	System ROM read access timing
73	G1_IF	84	4	G1RWC	W	System ROM write access timing
74	G1_IF	88	4	G1FRC	W	Flash ROM read access timing
75	G1_IF	8c	4	G1FWC	W	Flash ROM write access timing
76	G1_IF	90	4	G1CRC	W	GD PIO read access timing
77	G1_IF	94	4	G1CWC	W	GD PIO write access timing
78
79	G1_IF	a0	4	G1GDRC	W	GD-DMA read access timing
80	G1_IF	a4	4	G1GDWC	W	GD-DMA write access timing
81
82	G1_IF	b0	4	G1SYSM	R	System mode
83	G1_IF	b4	4	G1CRDYC	W	G1IORDY signal control
84	G1_IF	b8	4	GDAPRO	W	GD-DMA address range
85
86	G1_IF	e4	4	GDUNLOCK	W	(undocumented unlock register)
87	G1_IF	f4	4	GDSTARD	R	GD-DMA address count (on Root Bus)
88	G1_IF	f8	4	GDLEND	R	GD-DMA transfer counter
89
90	G2_IF	00	4	ADSTAG	RW	ACIA:G2-DMA G2 start address
91	G2_IF	04	4	ADSTAR	RW	ACIA:G2-DMA system memory start address
92	G2_IF	08	4	ADLEN	RW	ACIA:G2-DMA length
93	G2_IF	0c	4	ADDIR	RW	ACIA:G2-DMA direction
94	G2_IF	10	4	ADTSEL	RW	ACIA:G2-DMA trigger select
95	G2_IF	14	4	ADEN	RW	ACIA:G2-DMA enable
96	G2_IF	18	4	ADST	RW	ACIA:G2-DMA start
97	G2_IF	1c	4	ADSUSP	RW	ACIA:G2-DMA suspend
98
99	G2_IF	20	4	E1STAG	RW	Ext1:G2-DMA start address
100	G2_IF	24	4	E1STAR	RW	Ext1:G2-DMA system memory start address
101	G2_IF	28	4	E1LEN	RW	Ext1:G2-DMA length
102	G2_IF	2c	4	E1DIR	RW	Ext1:G2-DMA direction
103	G2_IF	30	4	E1TSEL	RW	Ext1:G2-DMA trigger select
104	G2_IF	34	4	E1EN	RW	Ext1:G2-DMA enable
105	G2_IF	38	4	E1ST	RW	Ext1:G2-DMA start
106	G2_IF	3c	4	E1SUSP	RW	Ext1:G2-DMA suspend
107
108	G2_IF	40	4	E2STAG	RW	Ext2:G2-DMA start address
109	G2_IF	44	4	E2STAR	RW	Ext2:G2-DMA system memory start address
110	G2_IF	48	4	E2LEN	RW	Ext2:G2-DMA length
111	G2_IF	4c	4	E2DIR	RW	Ext2:G2-DMA direction
112	G2_IF	50	4	E2TSEL	RW	Ext2:G2-DMA trigger select
113	G2_IF	54	4	E2EN	RW	Ext2:G2-DMA enable
114	G2_IF	58	4	E2ST	RW	Ext2:G2-DMA start
115	G2_IF	5c	4	E2SUSP	RW	Ext2:G2-DMA suspend
116
117	G2_IF	60	4	DDSTAG	RW	Dev:G2-DMA start address
118	G2_IF	64	4	DDSTAR	RW	Dev:G2-DMA system memory start address
119	G2_IF	68	4	DDLEN	RW	Dev:G2-DMA length
120	G2_IF	6c	4	DDDIR	RW	Dev:G2-DMA direction
121	G2_IF	70	4	DDTSEL	RW	Dev:G2-DMA trigger select
122	G2_IF	74	4	DDEN	RW	Dev:G2-DMA enable
123	G2_IF	78	4	DDST	RW	Dev:G2-DMA start
124	G2_IF	7c	4	DDSUSP	RW	Dev:G2-DMA suspend
125
126	G2_IF	80	4	G2ID	R	G2 bus version
127
128	G2_IF	90	4	G2DSTO	RW	G2/DS timeout
129	G2_IF	94	4	G2TRTO	RW	G2/TR timeout
130	G2_IF	98	4	G2MDMTO	RW	Modem unit wait timeout
131	G2_IF	9c	4	G2MDMW	RW	Modem unit wait time
132
133	G2_IF	bc	4	G2APRO	W	G2-DMA address range
134
135	G2_IF	c0	4	ADSTAGD	R	AICA-DMA address counter (on AICA)
136	G2_IF	c4	4	ADSTARD	R	AICA-DMA address counter (on root bus)
137	G2_IF	c8	4	ADLEND	R	AICA-DMA transfer counter
138
139	G2_IF	d0	4	E1STAGD	R	Ext-DMA1 address counter (on Ext)
140	G2_IF	d4	4	E1STARD	R	Ext-DMA1 address counter (on root bus)
141	G2_IF	d8	4	E1LEND	R	Ext-DMA1 transfer counter
142
143	G2_IF	e0	4	E2STAGD	R	Ext-DMA2 address counter (on Ext)
144	G2_IF	e4	4	E2STARD	R	Ext-DMA2 address counter (on root bus)
145	G2_IF	e8	4	E2LEND	R	Ext-DMA2 transfer counter
146
147	G2_IF	f0	4	DDSTAGD	R	Dev-DMA address counter (on Dev)
148	G2_IF	f4	4	DDSTARD	R	Dev-DMA address counter (on root bus)
149	G2_IF	f8	4	DDLEND	R	Dev-DMA transfer counter
150
151	PVR_IF	00	4	PDSTAP	RW	PVR-DMA start address
152	PVR_IF	04	4	PDSTAR	RW	PVR-DMA system memory start address
153	PVR_IF	08	4	PDLEN	RW	PVR-DMA length
154	PVR_IF	0c	4	PDDIR	RW	PVR-DMA direction
155	PVR_IF	10	4	PDTSEL	RW	PVR-DMA trigger select
156	PVR_IF	14	4	PDEN	RW	PVR-DMA enable
157	PVR_IF	18	4	PDST	RW	PVR-DMA start
158
159	PVR_IF	80	4	PDAPRO	W	PVR-DMA address range
160
161	PVR_IF	f0	4	PDSTAPD	R	PVR-DMA address counter (on Ext)
162	PVR_IF	f4	4	PDSTARD	R	PVR-DMA address counter (on root bus)
163	PVR_IF	f8	4	PDLEND	R	PVR-DMA transfer counter