maple: add ft8 data transfer

example/maple_controller.cpp

@@ -65,7 +65,7 @@ void do_get_condition(uint32_t port)
   }
 
   state[port].controller_connected = 1;
-  bool a = data_fields.data.digital_button & ft0::data_transfer::digital_button::a;
+  bool a = ft0::data_transfer::digital_button::a(data_fields.data.digital_button);
   if (a == 0) {
     serial::string("port ");
     serial::integer<uint8_t>(port);
@@ -108,6 +108,8 @@ void main()
   command_buf = align_32byte(_command_buf);
   receive_buf = align_32byte(_receive_buf);
 
+  vga();
+
   while (1) {
     v_sync_out();
     v_sync_in();

maple/maple_bus_ft0.hpp

@@ -1,22 +1,54 @@
 namespace ft0 {
   namespace data_transfer {
     namespace digital_button {
-      constexpr uint32_t ra = 1 << 7;
-      constexpr uint32_t la = 1 << 6;
-      constexpr uint32_t da = 1 << 5;
-      constexpr uint32_t ua = 1 << 4;
-      constexpr uint32_t start = 1 << 3;
-      constexpr uint32_t a = 1 << 2;
-      constexpr uint32_t b = 1 << 1;
-      constexpr uint32_t c = 1 << 0;
-      constexpr uint32_t rb = 1 << 15;
-      constexpr uint32_t lb = 1 << 14;
-      constexpr uint32_t db = 1 << 13;
-      constexpr uint32_t ub = 1 << 12;
-      constexpr uint32_t d = 1 << 11;
-      constexpr uint32_t x = 1 << 10;
-      constexpr uint32_t y = 1 << 9;
-      constexpr uint32_t z = 1 << 8;
+      constexpr uint32_t ra() { return 0b1 << 7; }
+      constexpr uint32_t ra(uint32_t reg) { return (reg >> 7) & 0b1; }
+      
+      constexpr uint32_t la() { return 0b1 << 6; }
+      constexpr uint32_t la(uint32_t reg) { return (reg >> 6) & 0b1; }
+      
+      constexpr uint32_t da() { return 0b1 << 5; }
+      constexpr uint32_t da(uint32_t reg) { return (reg >> 5) & 0b1; }
+      
+      constexpr uint32_t ua() { return 0b1 << 4; }
+      constexpr uint32_t ua(uint32_t reg) { return (reg >> 4) & 0b1; }
+      
+      constexpr uint32_t start() { return 0b1 << 3; }
+      constexpr uint32_t start(uint32_t reg) { return (reg >> 3) & 0b1; }
+      
+      constexpr uint32_t a() { return 0b1 << 2; }
+      constexpr uint32_t a(uint32_t reg) { return (reg >> 2) & 0b1; }
+      
+      constexpr uint32_t b() { return 0b1 << 1; }
+      constexpr uint32_t b(uint32_t reg) { return (reg >> 1) & 0b1; }
+      
+      constexpr uint32_t c() { return 0b1 << 0; }
+      constexpr uint32_t c(uint32_t reg) { return (reg >> 0) & 0b1; }
+      
+      constexpr uint32_t rb() { return 0b1 << 15; }
+      constexpr uint32_t rb(uint32_t reg) { return (reg >> 15) & 0b1; }
+      
+      constexpr uint32_t lb() { return 0b1 << 14; }
+      constexpr uint32_t lb(uint32_t reg) { return (reg >> 14) & 0b1; }
+      
+      constexpr uint32_t db() { return 0b1 << 13; }
+      constexpr uint32_t db(uint32_t reg) { return (reg >> 13) & 0b1; }
+      
+      constexpr uint32_t ub() { return 0b1 << 12; }
+      constexpr uint32_t ub(uint32_t reg) { return (reg >> 12) & 0b1; }
+      
+      constexpr uint32_t d() { return 0b1 << 11; }
+      constexpr uint32_t d(uint32_t reg) { return (reg >> 11) & 0b1; }
+      
+      constexpr uint32_t x() { return 0b1 << 10; }
+      constexpr uint32_t x(uint32_t reg) { return (reg >> 10) & 0b1; }
+      
+      constexpr uint32_t y() { return 0b1 << 9; }
+      constexpr uint32_t y(uint32_t reg) { return (reg >> 9) & 0b1; }
+      
+      constexpr uint32_t z() { return 0b1 << 8; }
+      constexpr uint32_t z(uint32_t reg) { return (reg >> 8) & 0b1; }
+      
     }
     
     struct data_format {

maple/maple_bus_ft8.hpp

@@ -0,0 +1,37 @@
+namespace ft8 {
+  namespace data_transfer {
+    namespace vset {
+      constexpr uint32_t vn() { return 0b1111 << 4; }
+      constexpr uint32_t vn(uint32_t reg) { return (reg >> 4) & 0b1111; }
+      
+      constexpr uint32_t vp() { return 0b11 << 2; }
+      constexpr uint32_t vp(uint32_t reg) { return (reg >> 2) & 0b11; }
+      
+      constexpr uint32_t vd() { return 0b11 << 0; }
+      constexpr uint32_t vd(uint32_t reg) { return (reg >> 0) & 0b11; }
+      
+      constexpr uint32_t pf() { return 0b1 << 15; }
+      constexpr uint32_t pf(uint32_t reg) { return (reg >> 15) & 0b1; }
+      
+      constexpr uint32_t cv() { return 0b1 << 14; }
+      constexpr uint32_t cv(uint32_t reg) { return (reg >> 14) & 0b1; }
+      
+      constexpr uint32_t pd() { return 0b1 << 13; }
+      constexpr uint32_t pd(uint32_t reg) { return (reg >> 13) & 0b1; }
+      
+      constexpr uint32_t owf() { return 0b1 << 12; }
+      constexpr uint32_t owf(uint32_t reg) { return (reg >> 12) & 0b1; }
+      
+      constexpr uint32_t va() { return 0b1111 << 8; }
+      constexpr uint32_t va(uint32_t reg) { return (reg >> 8) & 0b1111; }
+      
+    }
+    
+    struct data_format {
+      uint16_t vset;
+      uint16_t fm;
+    };
+    static_assert((sizeof (struct data_format)) == 4);
+  }
+}
+

regs/gen/maple_data_format.py

@@ -5,6 +5,12 @@ from collections import defaultdict
 
 from generate import renderer
 
+@dataclass
+class Bit:
+    name: str
+    length: int
+    position: int
+
 @dataclass
 class Field:
     name: str
@@ -26,6 +32,17 @@ def read_input(filename):
         ]
     return rows
 
+def parse_bits(bits: list[str]):
+    bit_order = [7, 6, 5, 4, 3, 2, 1, 0]
+    by_name = defaultdict(list)
+    for bit_ix, bit in zip(bit_order, bits):
+        by_name[bit].append(bit_ix)
+    for name, indicies in by_name.items():
+        yield Bit(name=name,
+                  length=len(indicies),
+                  position=min(indicies),
+                  )
+
 def parse_data_format(ix, rows):
     if ix >= len(rows):
         return None
@@ -50,7 +67,8 @@ def parse_data_format(ix, rows):
         assert excess_bits == []
         bits = [b for b in _bits[:8] if b != ""]
         assert len(bits) in {0, 8}, bits
-        fields[field_name].append(Field(field_name, list(bits)))
+        fields[field_name].append(Field(field_name,
+                                        list(parse_bits(bits))))
         size += 1
         if field_name not in field_order:
             field_order.append(field_name)
@@ -71,8 +89,6 @@ def parse(rows):
     assert len(formats) > 0
     return formats
 
-bit_order = [7, 6, 5, 4, 3, 2, 1, 0]
-
 def render_format(format):
     yield f"namespace {format.name} {{"
     for field_name in format.field_order:
@@ -83,11 +99,13 @@ def render_format(format):
         yield f"namespace {field_name} {{"
         for ix, field in enumerate(subfields):
             bit_offset = 8 * ix
-            if field.bits != []:
-                assert len(field.bits) == 8
-                for byte_ix, bit in zip(bit_order, field.bits):
-                    bit_ix = byte_ix + bit_offset
-                    yield f"constexpr uint32_t {bit.lower()} = 1 << {bit_ix};"
+            for bit in field.bits:
+                name = bit.name.lower()
+                pos = bit_offset + bit.position
+                mask = bin(2 ** bit.length - 1)
+                yield f"constexpr uint32_t {name}() {{ return {mask} << {pos}; }}"
+                yield f"constexpr uint32_t {name}(uint32_t reg) {{ return (reg >> {pos}) & {mask}; }}"
+                yield ""
         yield "}"
         yield ""
 

regs/maple_bus_ft8.csv

@@ -0,0 +1,5 @@
+"data_transfer",7,6,5,4,3,2,1,0
+"vset","vn","vn","vn","vn","vp","vp","vd","vd"
+"vset","pf","cv","pd","owf","va","va","va","va"
+"fm",,,,,,,,
+"fm",,,,,,,,