sh7091_bits.ods: partial
Notably missing is: - BSC (PDTRA / PCTRA) This also updates a handful of files to use the new sh7091_bits.hpp.
This commit is contained in:
parent
0b6c650ebd
commit
dcb9f36120
34
cache.cpp
34
cache.cpp
@ -1,34 +0,0 @@
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#include "type.hpp"
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#include "sh7091.hpp"
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#include "sh7091_bits.hpp"
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#include "cache.hpp"
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extern volatile reg32 sh7091_ic_a[256][(1 << 5) / 4] __asm("sh7091_ic_a");
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extern volatile reg32 sh7091_oc_a[512][(1 << 5) / 4] __asm("sh7091_oc_a");
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namespace cache {
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void init()
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{
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for (int i = 0; i < 256; i++) {
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sh7091_ic_a[i][0] = 0;
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}
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for (int i = 0; i < 512; i++) {
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sh7091_oc_a[i][0] = 0;
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}
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sh7091.CCN.CCR = CCR__ICI // instruction cache invalidate
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| CCR__ICE // instruction cache enable
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| CCR__OCI // operand cache invalidate
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| CCR__OCE // operand cache enable
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// | CCR__CB // enable copy-back mode for the P1 area
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;
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sh7091.CCN.MMUCR = 0;
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asm volatile ("nop;nop;nop;nop;nop;nop;nop;nop;");
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}
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}
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14
common.mk
14
common.mk
@ -55,7 +55,7 @@ IP_OBJ = \
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START_OBJ = \
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start.o \
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runtime.o \
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cache.o
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sh7091/cache.o
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%.bin.o: %.bin
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$(BUILD_BINARY_O)
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@ -139,12 +139,24 @@ maple/maple_bus_commands.hpp: regs/maple_bus_commands.csv regs/gen/maple_bus_com
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maple/maple_bus_bits.hpp: regs/maple_bus_bits.csv regs/gen/core_bits.py
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python regs/gen/core_bits.py $< > $@
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holly/core_bits.hpp: regs/core_bits.csv regs/gen/core_bits.py
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python regs/gen/core_bits.py $< > $@
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holly/holly.hpp: regs/holly.csv regs/gen/holly.py
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python regs/gen/holly.py $< > $@
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holly/ta_global_parameter.hpp: regs/global_parameter_format.csv regs/gen/ta_parameter_format.py
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python regs/gen/ta_parameter_format.py $< ta_global_parameter > $@
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holly/ta_vertex_parameter.hpp: regs/vertex_parameter_format.csv regs/gen/ta_parameter_format.py
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python regs/gen/ta_parameter_format.py $< ta_vertex_parameter > $@
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sh7091/sh7091.hpp: regs/sh7091.csv regs/gen/sh7091.py
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python regs/gen/sh7091.py $< > $@
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sh7091/sh7091_bits.hpp: regs/sh7091_bits.csv regs/gen/core_bits.py
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python regs/gen/core_bits.py $< > $@
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clean:
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find -P \
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-regextype posix-egrep \
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@ -4,7 +4,7 @@
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#include "vga.hpp"
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#include "holly/texture_memory_alloc.hpp"
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#include "holly.hpp"
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#include "holly/holly.hpp"
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#include "holly/core.hpp"
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#include "holly/core_bits.hpp"
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#include "holly/ta_fifo_polygon_converter.hpp"
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@ -1,9 +1,9 @@
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#include <cstdint>
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#include "sh7091.hpp"
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#include "sh7091_bits.hpp"
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#include "sh7091/sh7091.hpp"
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#include "sh7091/sh7091_bits.hpp"
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#include "sh7091/cache.hpp"
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#include "cache.hpp"
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#include "serial_load.hpp"
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extern uint32_t __bss_link_start __asm("__bss_link_start");
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@ -22,13 +22,15 @@ void main()
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load_init();
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while (1) {
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while ((sh7091.SCIF.SCFSR2 & SCFSR2__TDFE) == 0) {
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using namespace scif;
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while ((sh7091.SCIF.SCFSR2 & scfsr2::tdfe::bit_mask) == 0) {
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// wait
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}
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while ((sh7091.SCIF.SCFDR2 & 0b11111) > 0) {
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while ((scfdr2::receive_data_bytes(sh7091.SCIF.SCFDR2)) > 0) {
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uint8_t c = sh7091.SCIF.SCFRDR2;
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load_recv(c);
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}
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sh7091.SCIF.SCFSR2 = sh7091.SCIF.SCFSR2 & (~SCFSR2__RDF);
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sh7091.SCIF.SCFSR2 = sh7091.SCIF.SCFSR2 & (~scfsr2::rdf::bit_mask);
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}
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}
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@ -1,13 +1,12 @@
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#include "../float_uint32.hpp"
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#include "core_bits.hpp"
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#include "../holly.hpp"
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#include "../memorymap.hpp"
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#include "../systembus.hpp"
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#include "../systembus_bits.hpp"
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#include "float_uint32.hpp"
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#include "memorymap.hpp"
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#include "systembus.hpp"
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#include "systembus_bits.hpp"
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#include "texture_memory_alloc.hpp"
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#include "holly.hpp"
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#include "core.hpp"
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#include "core_bits.hpp"
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#include "background.hpp"
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#include "region_array.hpp"
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@ -1,13 +1,13 @@
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#include <cstdint>
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#include "systembus.hpp"
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#include "systembus_bits.hpp"
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#include "sh7091/sh7091.hpp"
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#include "sh7091/sh7091_bits.hpp"
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#include "core_bits.hpp"
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#include "ta_bits.hpp"
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#include "../holly.hpp"
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#include "../systembus.hpp"
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#include "../systembus_bits.hpp"
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#include "../sh7091.hpp"
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#include "../sh7091_bits.hpp"
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#include "holly.hpp"
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#include "texture_memory_alloc.hpp"
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#include "ta_fifo_polygon_converter.hpp"
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@ -79,23 +79,25 @@ void ta_polygon_converter_transfer(volatile uint32_t * buf, uint32_t size)
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volatile uint32_t _dummy = sh7091.DMAC.CHCR2;
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(void)_dummy;
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using namespace dmac;
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/* start a new CH2-DMA transfer from "system memory" to "TA FIFO polygon converter" */
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sh7091.DMAC.CHCR2 = 0; /* disable DMA channel */
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sh7091.DMAC.SAR2 = reinterpret_cast<uint32_t>(&buf[0]); /* start address, must be aligned to a CHCHR__TS-sized (32-byte) boundary */
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sh7091.DMAC.DMATCR2 = DMATCR2__TRANSFER_COUNT(size / 32); /* transfer count, in CHCHR__TS-sized (32-byte) units */
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sh7091.DMAC.CHCR2 = CHCR2__DM__DESTINATION_ADDRESS_FIXED
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| CHCR2__SM__SOURCE_ADDRESS_INCREMENTED
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| CHCR2__RS(0b0010) /* external request, single address mode;
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sh7091.DMAC.DMATCR2 = dmatcr::transfer_count(size / 32); /* transfer count, in CHCHR__TS-sized (32-byte) units */
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sh7091.DMAC.CHCR2 = chcr::dm::destination_address_fixed
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| chcr::sm::source_address_incremented
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| chcr::rs::resource_select(0b0010) /* external request, single address mode;
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external address space → external device */
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| CHCR2__TM__BURST_MODE /* transmit mode */
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| CHCR2__TS__32_BYTE /* transfer size */
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| CHCR2__DE; /* DMAC (channel) enable */
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| chcr::tm::cycle_burst_mode /* transmit mode */
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| chcr::ts::_32_byte /* transfer size */
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| chcr::de::channel_operation_enabled;
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sh7091.DMAC.DMAOR = DMAOR__DDT /* on-demand data transfer mode */
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| DMAOR__PR__CH2_CH0_CH1_CH3 /* priority mode; CH2 > CH0 > CH1 > CH3 */
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| DMAOR__DME; /* DMAC master enable */
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sh7091.DMAC.DMAOR = dmaor::ddt::on_demand_data_transfer_mode /* on-demand data transfer mode */
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| dmaor::pr::ch2_ch0_ch1_ch3 /* priority mode; CH2 > CH0 > CH1 > CH3 */
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| dmaor::dme::operation_enabled_on_all_channels; /* DMAC master enable */
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system.C2DSTAT = C2DSTAT__ADDRESS(0x10000000); /* CH2-DMA destination address */
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system.C2DLEN = CD2LEN__LENGTH(size) ; /* CH2-DMA length (must be a multiple of 32) */
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system.C2DLEN = CD2LEN__LENGTH(size); /* CH2-DMA length (must be a multiple of 32) */
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system.C2DST = 1; /* CH2-DMA start (an 'external' request from SH7091's perspective) */
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// wait for CH2-DMA completion
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@ -18,11 +18,19 @@ def parse_bit_number(s):
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assert '-' not in s
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return int(s, 10)
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def parse_bit_set(s, split_char):
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assert len(list(c for c in s if c == split_char)) == 1
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left, right = map(parse_bit_number, s.split(split_char, maxsplit=1))
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assert left > right, (left, right)
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return left, right
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def parse_bit_range(s):
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if '-' in s:
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left, right = map(parse_bit_number, s.split('-', maxsplit=1))
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assert left > right, (left, right)
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left, right = parse_bit_set(s, '-')
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return set(range(right, left+1))
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elif ',' in s:
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left, right = parse_bit_set(s, ',')
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return set([right, left])
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else:
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num = parse_bit_number(s)
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return set([num])
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@ -41,7 +49,7 @@ def aggregate_enums(aggregated_rows):
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for row in aggregated_rows:
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bits = parse_bit_range(row["bits"])
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assert row["bit_name"] != ""
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assert row["bit_name"] != "", row
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if row["enum_name"] == "":
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assert_unique_ordered(bits)
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non_enum.append(row)
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@ -50,7 +58,7 @@ def aggregate_enums(aggregated_rows):
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assert_unique_ordered(bits)
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non_enum.append(row["enum_name"])
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else:
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assert enum_bits[row["enum_name"]] == bits
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assert enum_bits[row["enum_name"]] == bits, row
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enum_bits[row["enum_name"]] = bits
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enum_aggregated[row["enum_name"]].append(row)
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@ -64,6 +72,7 @@ class enum:
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@dataclass
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class register:
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block: Union[None, str]
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name: str
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defs: list[Union[dict, enum]]
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@ -79,9 +88,17 @@ def aggregate_all_enums(aggregated):
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return row_or_string
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else:
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assert False, (row_or_string, type(row_or_string))
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defs = [resolve(aggregate) for aggregate in non_enum]
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if 'block' in rows[0]:
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blocks = set(row['block'] for row in rows)
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assert len(blocks) == 1, blocks
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block_name = next(iter(blocks))
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out.append(
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register(register_name,
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[resolve(aggregate) for aggregate in non_enum]))
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register(block_name, register_name, defs))
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else:
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out.append(
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register(None, register_name, defs))
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return out
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'''
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@ -107,19 +124,26 @@ def aggregate_all_enums(aggregated):
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'''
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def mask_from_bits(bits):
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mask = 2 ** len(bits) - 1
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h, l = max(bits), min(bits)
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mask = 2 ** ((h - l) + 1) - 1
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return mask
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def parse_value(value):
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return eval(value)
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def escape(bit_name):
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if bit_name[0] in {'0', '1', '2', '3', '4', '5', '6', '7', '8', '9'}:
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return '_' + bit_name
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else:
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return bit_name
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def render_read_only(bit_def):
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assert bit_def["value"] == ""
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assert bit_def["mask"] == ""
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bits = parse_bit_range(bit_def["bits"])
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mask_value = mask_from_bits(bits)
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yield (
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f"constexpr uint32_t {bit_def['bit_name']}(uint32_t reg) {{ "
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f"constexpr uint32_t {escape(bit_def['bit_name'])}(uint32_t reg) {{ "
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f"return (reg >> {min(bits)}) & {hex(mask_value)};"
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" }"
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)
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@ -145,7 +169,7 @@ def render_mask(bit_def):
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bits = parse_bit_range(bit_def["bits"])
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if mask.startswith("float_"):
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yield (
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f"constexpr uint32_t {bit_def['bit_name']}(float num) {{ "
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f"inline uint32_t {escape(bit_def['bit_name'])}(float num) {{ "
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f"return {render_float_mask(mask)};"
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" }"
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)
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@ -155,7 +179,7 @@ def render_mask(bit_def):
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assert mask_value & mask_from_bits(bits) == mask_value, (mask_value, mask_from_bits(bits))
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yield (
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f"constexpr uint32_t {bit_def['bit_name']}(uint32_t num) {{ "
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f"constexpr uint32_t {escape(bit_def['bit_name'])}(uint32_t num) {{ "
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f"return (num & {hex(mask_value)}) << {min(bits)};"
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" }"
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)
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@ -163,9 +187,9 @@ def render_mask(bit_def):
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def render_value(bit_def):
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assert bit_def["mask"] == ""
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bits = parse_bit_range(bit_def["bits"])
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assert parse_value(bit_def["value"]) <= mask_from_bits(bits), bit_def["value"]
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assert parse_value(bit_def["value"]) <= mask_from_bits(bits), (bit_def["value"], mask_from_bits(bits), bits)
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bit_ix = min(bits)
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yield f"constexpr uint32_t {bit_def['bit_name']} = {bit_def['value']} << {bit_ix};"
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yield f"constexpr uint32_t {escape(bit_def['bit_name'])} = {bit_def['value']} << {bit_ix};"
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def render_defs(bit_def):
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if bit_def["value"] != "":
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@ -212,9 +236,23 @@ def render_register(register):
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yield ""
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def render_registers(registers):
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last_block = None
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for register in registers:
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if register.block != last_block:
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assert register.block is not None
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if last_block is not None:
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yield '}' # end of previous namespace
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yield ""
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yield f'namespace {register.block.lower()} {{'
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if register.block is None:
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assert last_block is None
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last_block = register.block
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yield from render_register(register)
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if last_block is not None:
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yield '}' # end of block namespace
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def header():
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yield "#pragma once"
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yield ""
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@ -45,13 +45,12 @@ def new_writer():
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def terminate():
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nonlocal last_block
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nonlocal first_address
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nonlocal stack
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if last_block is not None:
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yield "};"
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for address, name in stack:
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yield f"static_assert((offsetof (struct {last_block.lower()}_reg, {name})) == {hex(address)});"
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yield f"static_assert((offsetof (struct {last_block.lower()}_reg, {name})) == {hex(address - first_address)});"
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yield ""
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stack = []
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@ -68,15 +67,16 @@ def new_writer():
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_address = int(row["address"], 16)
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assert _offset <= 0xff
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assert _address <= 0xffff
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address = (_offset << 16) | (_address << 0)
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offset_address = (_offset << 16)
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address = offset_address | (_address << 0)
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size = int(row["size"], 10)
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name = row["name"]
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description = row["description"]
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if block != last_block:
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yield from terminate()
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first_address = 0 # hmm...
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last_address = 0
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first_address = offset_address
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last_address = offset_address
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size_total = 0
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reserved_num = 0
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yield f"struct {block.lower()}_reg {{"
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293
regs/sh7091_bits.csv
Normal file
293
regs/sh7091_bits.csv
Normal file
@ -0,0 +1,293 @@
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"block","register_name","enum_name","bits","bit_name","value","mask","description"
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"CCN","PTEH",,"31-10","VPN",,,"Virtual Page Number"
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"CCN","PTEH",,"7-0","ASID",,,"Address space identifier"
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,,,,,,,
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"CCN","PTEL",,"28-10","PPN",,,"Physical page number"
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"CCN","PTEL","V","8","invalid","0",,"Validity"
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"CCN","PTEL","V","8","valid","1",,"Validity"
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"CCN","PTEL","SZ","7,4","1_kbyte_page","0b0000",,"Page size"
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"CCN","PTEL","SZ","7,4","4_kbyte_page","0b0001",,"Page size"
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"CCN","PTEL","SZ","7,4","64_kbyte_page","0b1000",,"Page size"
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"CCN","PTEL","SZ","7,4","1_mbyte_page","0b1001",,"Page size"
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"CCN","PTEL","PR","6-5","read_only_in_privileged_mode","0b00",,"Protection key data"
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"CCN","PTEL","PR","6-5","read_write_in_privileged_mode","0b01",,"Protection key data"
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"CCN","PTEL","PR","6-5","read_only_in_privileged_and_user_mode","0b10",,"Protection key data"
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"CCN","PTEL","PR","6-5","read_write_in_privileged_and_user_mode","0b11",,"Protection key data"
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"CCN","PTEL","C","3","not_cacheable","0",,"Cacheability bit"
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"CCN","PTEL","C","3","cacheable","1",,"Cacheability bit"
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"CCN","PTEL","D","2","write_has_not_been_performed","0",,"Dirty bit"
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"CCN","PTEL","D","2","write_has_been_performed","1",,"Dirty bit"
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"CCN","PTEL","SH","1","pages_are_shared_by_processes","0",,"Share status bit"
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"CCN","PTEL","SH","1","pages_are_not_shared_by_processes","1",,"Share status bit"
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"CCN","PTEL","WT","0","copy_back_mode","0",,"Write-through bit"
|
||||
"CCN","PTEL","WT","0","write_through_mode","1",,"Write-through bit"
|
||||
,,,,,,,
|
||||
"CCN","MMUCR",,"31-26","LRUI",,,"Least recently used ITLB"
|
||||
"CCN","MMUCR",,"23-18","URB",,,"UTLB replace boundary"
|
||||
"CCN","MMUCR",,"15-10","URC",,,"UTLB replace counter"
|
||||
"CCN","MMUCR","SQMD","9","user_privileged_access_possible","0",,"Store queue mode bit"
|
||||
"CCN","MMUCR","SQMD","9","privileged_access_possible","1",,"Store queue mode bit"
|
||||
"CCN","MMUCR","SV","8","multiple_virtual_memory_mode","0",,"Single virtual mode bit"
|
||||
"CCN","MMUCR","SV","8","single_virtual_memory_mode","1",,"Single virtual mode bit"
|
||||
"CCN","MMUCR","TI","2","invalidate_all_utlb_itlb_bits","1",,"TLB invalidate"
|
||||
"CCN","MMUCR","AT","0","mmu_disabled","0",,"Address translation bit"
|
||||
"CCN","MMUCR","AT","0","mmu_enabled","1",,"Address translation bit"
|
||||
,,,,,,,
|
||||
"CCN","BASRA",,"7-0","basa",,"0xff",
|
||||
,,,,,,,
|
||||
"CCN","BASRB",,"7-0","basa",,"0xff",
|
||||
,,,,,,,
|
||||
"CCN","CCR","IIX","15","address_bits_12_5_used_for_ic_entry_selection","0",,"IC index enable"
|
||||
"CCN","CCR","IIX","15","address_bits_25_and_11_5_used_for_ic_entry_selection","1",,"IC index enable"
|
||||
"CCN","CCR","ICI","11","clear_v_bits_of_all_ic_entries","1",,"IC invalidation"
|
||||
"CCN","CCR","ICE","8","ic_not_used","0",,"IC enable"
|
||||
"CCN","CCR","ICE","8","ic_used","1",,"IC enable"
|
||||
"CCN","CCR","OIX","7","address_bits_13_5_used_for_oc_entry_selection","0",,"OC index enable"
|
||||
"CCN","CCR","OIX","7","address_bits_25_and_12_5_used_for_oc_entry_selection","1",,"OC index enable"
|
||||
"CCN","CCR","ORA","5","16_kbytes_used_as_cache","0",,"OC RAM enable"
|
||||
"CCN","CCR","ORA","5","8_kbytes_used_as_cache_8_kbytes_used_as_ram","1",,"OC RAM enable"
|
||||
"CCN","CCR","OCI","3","clear_v_and_u_bits_of_all_oc_entries","1",,"OC invalidation"
|
||||
"CCN","CCR","CB","2","write_through_mode","0",,"Copy-back enable"
|
||||
"CCN","CCR","CB","2","copy_back_mode","1",,"Copy-back enable"
|
||||
"CCN","CCR","WT","1","copy_back_mode","0",,"Write-through enable"
|
||||
"CCN","CCR","WT","1","write_through_mode","1",,"Write-through enable"
|
||||
"CCN","CCR","OCE","0","oc_not_used","0",,"OC enable"
|
||||
"CCN","CCR","OCE","0","oc_used","1",,"OC enable"
|
||||
,,,,,,,
|
||||
"CCN","TRA",,"9-2","imm",,,
|
||||
,,,,,,,
|
||||
"CCN","EXPEVT",,"11-0","exception_code",,,
|
||||
,,,,,,,
|
||||
"CCN","INTEVT",,"11-0","exception_code",,,
|
||||
,,,,,,,
|
||||
"CCN","PTEA","TC","3","area_5_is_used","0",,"Timing control bit"
|
||||
"CCN","PTEA","TC","3","area_6_is_used","1",,"Timing control bit"
|
||||
"CCN","PTEA","SA","2-0","undefined","0b000",,"Space attribute bits"
|
||||
"CCN","PTEA","SA","2-0","variable_size_io_space","0b001",,"Space attribute bits"
|
||||
"CCN","PTEA","SA","2-0","8_bit_io_space","0b010",,"Space attribute bits"
|
||||
"CCN","PTEA","SA","2-0","16_bit_io_space","0b011",,"Space attribute bits"
|
||||
"CCN","PTEA","SA","2-0","8_bit_common_memory_space","0b100",,"Space attribute bits"
|
||||
"CCN","PTEA","SA","2-0","16_bit_common_memory_space","0b101",,"Space attribute bits"
|
||||
"CCN","PTEA","SA","2-0","8_bit_attribute_memory_space","0b110",,"Space attribute bits"
|
||||
"CCN","PTEA","SA","2-0","16_bit_attribute_memory_space","0b111",,"Space attribute bits"
|
||||
,,,,,,,
|
||||
"CCN","QACR0",,"4-2","area",,"0b111",
|
||||
,,,,,,,
|
||||
"CCN","QACR1",,"4-2","area",,"0b111",
|
||||
,,,,,,,
|
||||
"DMAC","DMATCR",,"23-0","transfer_count",,"0xffffff",
|
||||
,,,,,,,
|
||||
"DMAC","CHCR","SSA","31-29","reserved_in_pcmcia_access","0b000",,
|
||||
"DMAC","CHCR","SSA","31-29","dynamic_bus_sizing_io_space","0b001",,
|
||||
"DMAC","CHCR","SSA","31-29","8_bit_io_space","0b010",,
|
||||
"DMAC","CHCR","SSA","31-29","16_bit_io_space","0b011",,
|
||||
"DMAC","CHCR","SSA","31-29","8_bit_common_memory_space","0b100",,
|
||||
"DMAC","CHCR","SSA","31-29","16_bit_common_memory_space","0b101",,
|
||||
"DMAC","CHCR","SSA","31-29","8_bit_attribute_memory_space","0b110",,
|
||||
"DMAC","CHCR","SSA","31-29","16_bit_attribute_memory_space","0b111",,
|
||||
"DMAC","CHCR","STC","28","c5_space_wait_cycle_selection","0",,
|
||||
"DMAC","CHCR","STC","28","c6_space_wait_cycle_selection","1",,
|
||||
"DMAC","CHCR","DSA","27-25","reserved_in_pcmcia_access","0b000",,
|
||||
"DMAC","CHCR","DSA","27-25","dynamic_bus_sizing_io_space","0b001",,
|
||||
"DMAC","CHCR","DSA","27-25","8_bit_io_space","0b010",,
|
||||
"DMAC","CHCR","DSA","27-25","16_bit_io_space","0b011",,
|
||||
"DMAC","CHCR","DSA","27-25","8_bit_common_memory_space","0b100",,
|
||||
"DMAC","CHCR","DSA","27-25","16_bit_common_memory_space","0b101",,
|
||||
"DMAC","CHCR","DSA","27-25","8_bit_attribute_memory_space","0b110",,
|
||||
"DMAC","CHCR","DSA","27-25","16_bit_attribute_memory_space","0b111",,
|
||||
"DMAC","CHCR","DTC","24","c5_space_wait_cycle_selection","0",,
|
||||
"DMAC","CHCR","DTC","24","c6_space_wait_cycle_selection","1",,
|
||||
"DMAC","CHCR","DS","19","low_level_detection","0",,
|
||||
"DMAC","CHCR","DS","19","falling_edge_detection","1",,
|
||||
"DMAC","CHCR","RL","18","drak_is_an_active_high","0",,
|
||||
"DMAC","CHCR","RL","18","drak_is_an_active_low","1",,
|
||||
"DMAC","CHCR","AM","17","dack_is_output_in_read_cycle","0",,
|
||||
"DMAC","CHCR","AM","17","dack_is_output_in_write_cycle","1",,
|
||||
"DMAC","CHCR","AL","16","active_high_output","0",,
|
||||
"DMAC","CHCR","AL","16","active_low_output","1",,
|
||||
"DMAC","CHCR","DM","15-14","destination_address_fixed","0b00",,
|
||||
"DMAC","CHCR","DM","15-14","destination_address_incremented","0b01",,
|
||||
"DMAC","CHCR","DM","15-14","destination_address_decremented","0b10",,
|
||||
"DMAC","CHCR","SM","13-12","source_address_fixed","0b00",,
|
||||
"DMAC","CHCR","SM","13-12","source_address_incremented","0b01",,
|
||||
"DMAC","CHCR","SM","13-12","source_address_decremented","0b10",,
|
||||
"DMAC","CHCR","RS","11-8","resource_select",,"0b1111",
|
||||
"DMAC","CHCR","TM","7","cycle_steal_mode","0",,
|
||||
"DMAC","CHCR","TM","7","cycle_burst_mode","1",,
|
||||
"DMAC","CHCR","TS","6-4","64_bit","0b000",,
|
||||
"DMAC","CHCR","TS","6-4","8_bit","0b001",,
|
||||
"DMAC","CHCR","TS","6-4","16_bit","0b010",,
|
||||
"DMAC","CHCR","TS","6-4","32_bit","0b011",,
|
||||
"DMAC","CHCR","TS","6-4","32_byte","0b100",,
|
||||
"DMAC","CHCR","IE","2","interrupt_request_not_generated","0",,
|
||||
"DMAC","CHCR","IE","2","interrupt_request_generated","1",,
|
||||
"DMAC","CHCR","TE","1","transfers_not_completed","0",,
|
||||
"DMAC","CHCR","TE","1","transfers_completed","1",,
|
||||
"DMAC","CHCR","DE","0","channel_operation_disabled","0",,
|
||||
"DMAC","CHCR","DE","0","channel_operation_enabled","1",,
|
||||
,,,,,,,
|
||||
"DMAC","DMAOR","DDT","15","normal_dma_mode","0",,
|
||||
"DMAC","DMAOR","DDT","15","on_demand_data_transfer_mode","1",,
|
||||
"DMAC","DMAOR","PR","9-8","ch0_ch1_ch2_ch3","0b00",,
|
||||
"DMAC","DMAOR","PR","9-8","ch0_ch2_ch3_ch1","0b01",,
|
||||
"DMAC","DMAOR","PR","9-8","ch2_ch0_ch1_ch3","0b10",,
|
||||
"DMAC","DMAOR","PR","9-8","round_robin","0b11",,
|
||||
"DMAC","DMAOR","AE","2","no_address_error__dma_transfer_enabled","0",,
|
||||
"DMAC","DMAOR","AE","2","address_error__dma_transfer_disabled","1",,
|
||||
"DMAC","DMAOR","NMIF","1","no_nmi__dma_transfer_enabled","0",,
|
||||
"DMAC","DMAOR","NMIF","1","nmi__dma_transfer_disabled","1",,
|
||||
"DMAC","DMAOR","DME","0","operation_disabled_on_all_channels","0",,
|
||||
"DMAC","DMAOR","DME","0","operation_enabled_on_all_channels","1",,
|
||||
,,,,,,,
|
||||
"INTC","ICR","NMIL","15","pin_input_level_is_low","0",,
|
||||
"INTC","ICR","NMIL","15","pin_input_level_is_high","1",,
|
||||
"INTC","ICR","MAI","14","interrupts_enabled_while_nmi_pin_is_low","0",,
|
||||
"INTC","ICR","MAI","14","interrupts_disabled_while_nmi_pin_is_low","1",,
|
||||
"INTC","ICR","NMIB","9","interrupt_requests_witheld","0",,
|
||||
"INTC","ICR","NMIB","9","interrupt_requests_detected","1",,
|
||||
"INTC","ICR","NMIE","8","interrupt_on_falling_edge_of_nmi","0",,
|
||||
"INTC","ICR","NMIE","8","interrupt_on_rising_edge_of_nmi","1",,
|
||||
"INTC","ICR","IRLM","7","level_encoded_interrupt_requests","0",,
|
||||
"INTC","ICR","IRLM","7","independent_interrupt_request","1",,
|
||||
,,,,,,,
|
||||
"INTC","IPRA",,"15-12","TMU0",,"0b1111",
|
||||
"INTC","IPRA",,"11-8","TMU1",,"0b1111",
|
||||
"INTC","IPRA",,"7-4","TMU2",,"0b1111",
|
||||
"INTC","IPRA",,"3-0","RTC",,"0b1111",
|
||||
,,,,,,,
|
||||
"INTC","IPRB",,"15-12","WDT",,"0b1111",
|
||||
"INTC","IPRB",,"11-8","REF",,"0b1111",
|
||||
"INTC","IPRB",,"7-4","SCI1",,"0b1111",
|
||||
,,,,,,,
|
||||
"INTC","IPRC",,"15-12","GPIO",,"0b1111",
|
||||
"INTC","IPRC",,"11-8","DMAC",,"0b1111",
|
||||
"INTC","IPRC",,"7-4","SCIF",,"0b1111",
|
||||
"INTC","IPRC",,"3-0","UDI",,"0b1111",
|
||||
,,,,,,,
|
||||
"TMU","TOCR","TCOE","0","tclk_is_external_clock_or_input_capture","0",,"Timer Clock Pin Control"
|
||||
"TMU","TOCR","TCOE","0","tclk_is_on_chip_rtc","1",,"Timer Clock Pin Control"
|
||||
,,,,,,,
|
||||
"TMU","TSTR","STR2","2","counter_start","1",,"Counter Start 2"
|
||||
"TMU","TSTR","STR1","1","counter_start","1",,"Counter Start 1"
|
||||
"TMU","TSTR","STR0","0","counter_start","1",,"Counter Start 0"
|
||||
,,,,,,,
|
||||
"TMU","TCR0",,"8","UNF","1",,"Underflow Flag"
|
||||
"TMU","TCR0",,"5","UNIE","1",,"Underflow Interrupt Control"
|
||||
"TMU","TCR0","CKEG","4-3","rising","0b00",,"Clock Edge"
|
||||
"TMU","TCR0","CKEG","4-3","falling","0b01",,"Clock Edge"
|
||||
"TMU","TCR0","CKEG","4-3","rising_falling","0b10",,"Clock Edge"
|
||||
"TMU","TCR0","TPSC","2-0","p_phi_4","0b000",,"Timer Prescaler"
|
||||
"TMU","TCR0","TPSC","2-0","p_phi_16","0b001",,"Timer Prescaler"
|
||||
"TMU","TCR0","TPSC","2-0","p_phi_64","0b010",,"Timer Prescaler"
|
||||
"TMU","TCR0","TPSC","2-0","p_phi_256","0b011",,"Timer Prescaler"
|
||||
"TMU","TCR0","TPSC","2-0","p_phi_1024","0b100",,"Timer Prescaler"
|
||||
"TMU","TCR0","TPSC","2-0","rtc_output","0b110",,"Timer Prescaler"
|
||||
"TMU","TCR0","TPSC","2-0","external","0b111",,"Timer Prescaler"
|
||||
,,,,,,,
|
||||
"TMU","TCR1",,"8","UNF","1",,"Underflow Flag"
|
||||
"TMU","TCR1",,"5","UNIE","1",,"Underflow Interrupt Control"
|
||||
"TMU","TCR1","CKEG","4-3","rising","0b00",,"Clock Edge"
|
||||
"TMU","TCR1","CKEG","4-3","falling","0b01",,"Clock Edge"
|
||||
"TMU","TCR1","CKEG","4-3","rising_falling","0b10",,"Clock Edge"
|
||||
"TMU","TCR1","TPSC","2-0","p_phi_4","0b000",,"Timer Prescaler"
|
||||
"TMU","TCR1","TPSC","2-0","p_phi_16","0b001",,"Timer Prescaler"
|
||||
"TMU","TCR1","TPSC","2-0","p_phi_64","0b010",,"Timer Prescaler"
|
||||
"TMU","TCR1","TPSC","2-0","p_phi_256","0b011",,"Timer Prescaler"
|
||||
"TMU","TCR1","TPSC","2-0","p_phi_1024","0b100",,"Timer Prescaler"
|
||||
"TMU","TCR1","TPSC","2-0","rtc_output","0b110",,"Timer Prescaler"
|
||||
"TMU","TCR1","TPSC","2-0","external","0b111",,"Timer Prescaler"
|
||||
,,,,,,,
|
||||
"TMU","TCR2",,"9","ICPF","1",,"Input Capture Interrupt Flag"
|
||||
"TMU","TCR2",,"8","UNF","1",,"Underflow Flag"
|
||||
"TMU","TCR2","ICPE","7-6","disabled","0b00",,"Input Capture Control"
|
||||
"TMU","TCR2","ICPE","7-6","enabled","0b10",,"Input Capture Control"
|
||||
"TMU","TCR2","ICPE","7-6","enabled_with_interrupts","0b11",,"Input Capture Control"
|
||||
"TMU","TCR2",,"5","UNIE","1",,"Underflow Interrupt Control"
|
||||
"TMU","TCR2","CKEG","4-3","rising","0b00",,"Clock Edge"
|
||||
"TMU","TCR2","CKEG","4-3","falling","0b01",,"Clock Edge"
|
||||
"TMU","TCR2","CKEG","4-3","rising_falling","0b10",,"Clock Edge"
|
||||
"TMU","TCR2","TPSC","2-0","p_phi_4","0b000",,"Timer Prescaler"
|
||||
"TMU","TCR2","TPSC","2-0","p_phi_16","0b001",,"Timer Prescaler"
|
||||
"TMU","TCR2","TPSC","2-0","p_phi_64","0b010",,"Timer Prescaler"
|
||||
"TMU","TCR2","TPSC","2-0","p_phi_256","0b011",,"Timer Prescaler"
|
||||
"TMU","TCR2","TPSC","2-0","p_phi_1024","0b100",,"Timer Prescaler"
|
||||
"TMU","TCR2","TPSC","2-0","rtc_output","0b110",,"Timer Prescaler"
|
||||
"TMU","TCR2","TPSC","2-0","external","0b111",,"Timer Prescaler"
|
||||
,,,,,,,
|
||||
"SCIF","SCSMR2","CHR","6","8_bit_data","0",,
|
||||
"SCIF","SCSMR2","CHR","6","7_bit_data","1",,
|
||||
"SCIF","SCSMR2","PE","5","parity_disabled","0",,
|
||||
"SCIF","SCSMR2","PE","5","parity_enabled","1",,
|
||||
"SCIF","SCSMR2","OE","4","even_parity","0",,
|
||||
"SCIF","SCSMR2","OE","4","odd_parity","1",,
|
||||
"SCIF","SCSMR2","STOP","3","1_stop_bit","0",,
|
||||
"SCIF","SCSMR2","STOP","3","2_stop_bits","1",,
|
||||
"SCIF","SCSMR2","CKS","1-0","p_phi_clock","0b00",,
|
||||
"SCIF","SCSMR2","CKS","1-0","p_phi_4_clock","0b01",,
|
||||
"SCIF","SCSMR2","CKS","1-0","p_phi_16_clock","0b10",,
|
||||
"SCIF","SCSMR2","CKS","1-0","p_phi_64_clock","0b11",,
|
||||
,,,,,,,
|
||||
"SCIF","SCSCR2","TIE","7","transmit_fifo_data_empty_interrupt_disabled","0",,
|
||||
"SCIF","SCSCR2","TIE","7","transmit_fifo_data_empty_interrupt_enabled","1",,
|
||||
"SCIF","SCSCR2","RIE","6","request_disabled","0",,
|
||||
"SCIF","SCSCR2","RIE","6","request_enabled","1",,
|
||||
"SCIF","SCSCR2","TE","5","transmission_disabled","0",,
|
||||
"SCIF","SCSCR2","TE","5","transmission_enabled","1",,
|
||||
"SCIF","SCSCR2","RE","4","reception_disabled","0",,
|
||||
"SCIF","SCSCR2","RE","4","reception_enabled","1",,
|
||||
"SCIF","SCSCR2","REIE","3","requests_disabled","0",,
|
||||
"SCIF","SCSCR2","REIE","3","requests_enabled","1",,
|
||||
"SCIF","SCSCR2","CKE1","1","sck2_pin_functions_as_input_pin","0",,
|
||||
"SCIF","SCSCR2","CKE1","1","sck2_pin_functions_as_clock_input","1",,
|
||||
,,,,,,,
|
||||
"SCIF","SCFSR2","PER3_0","15-12","number_of_parity_errors",,,
|
||||
"SCIF","SCFSR2","FER3_0","11-8","number_of_framing_errors",,,
|
||||
"SCIF","SCFSR2","ER","7","no_framing_error_or_parity_error","0",,
|
||||
"SCIF","SCFSR2","ER","7","framing_error_or_parity_error","1",,
|
||||
"SCIF","SCFSR2","TEND","6","transmission_in_progress","0",,
|
||||
"SCIF","SCFSR2","TEND","6","transmission_has_ended","1",,
|
||||
"SCIF","SCFSR2","TDFE","5","transmit_data_bytes_does_exceed_trigger","0",,
|
||||
"SCIF","SCFSR2","TDFE","5","transmit_data_bytes_does_not_exceed_trigger","1",,
|
||||
"SCIF","SCFSR2","BRK","4","break_not_received","0",,
|
||||
"SCIF","SCFSR2","BRK","4","break_received","1",,
|
||||
"SCIF","SCFSR2","FER","3","no_framing_error","0",,
|
||||
"SCIF","SCFSR2","FER","3","framing_error","1",,
|
||||
"SCIF","SCFSR2","PER","2","parity_error","0",,
|
||||
"SCIF","SCFSR2","PER","2","no_parity_error","1",,
|
||||
"SCIF","SCFSR2","RDF","1","receive_data_bytes_less_than_receive_trigger","0",,
|
||||
"SCIF","SCFSR2","RDF","1","receive_data_bytes_greater_than_or_equal_receive_trigger","1",,
|
||||
"SCIF","SCFSR2","DR","0","reception_is_in_progress","0",,
|
||||
"SCIF","SCFSR2","DR","0","no_further_data_has_arrived","1",,
|
||||
,,,,,,,
|
||||
"SCIF","SCFCR2","RTRG","7-6","trigger_on_1_byte","0b00",,
|
||||
"SCIF","SCFCR2","RTRG","7-6","trigger_on_4_bytes","0b01",,
|
||||
"SCIF","SCFCR2","RTRG","7-6","trigger_on_8_bytes","0b10",,
|
||||
"SCIF","SCFCR2","RTRG","7-6","trigger_on_14_byte","0b11",,
|
||||
"SCIF","SCFCR2","TTRG","5-4","trigger_on_8_bytes","0b00",,
|
||||
"SCIF","SCFCR2","TTRG","5-4","trigger_on_4_bytes","0b01",,
|
||||
"SCIF","SCFCR2","TTRG","5-4","trigger_on_2_bytes","0b10",,
|
||||
"SCIF","SCFCR2","TTRG","5-4","trigger_on_1_bytes","0b11",,
|
||||
"SCIF","SCFCR2","MCE","3","modem_signals_disabled","0",,
|
||||
"SCIF","SCFCR2","MCE","3","modem_signals_enabled","1",,
|
||||
"SCIF","SCFCR2","TFRST","2","reset_operation_disabled","0",,
|
||||
"SCIF","SCFCR2","TFRST","2","reset_operation_enabled","1",,
|
||||
"SCIF","SCFCR2","RFRST","1","reset_operation_disabled","0",,
|
||||
"SCIF","SCFCR2","RFRST","1","reset_operation_enabled","1",,
|
||||
"SCIF","SCFCR2","LOOP","0","loopback_test_disabled","0",,
|
||||
"SCIF","SCFCR2","LOOP","0","loopback_test_enabled","1",,
|
||||
,,,,,,,
|
||||
"SCIF","SCFDR2",,"12-8","transmit_data_bytes",,,
|
||||
"SCIF","SCFDR2",,"4-0","receive_data_bytes",,,
|
||||
,,,,,,,
|
||||
"SCIF","SCSPTR2","RTSIO","7","rtsdt_not_output_to_rts2","0",,
|
||||
"SCIF","SCSPTR2","RTSIO","7","rtsdt_output_to_rts2","1",,
|
||||
"SCIF","SCSPTR2","RTSDT","6","input_output_data_is_low_level","0",,
|
||||
"SCIF","SCSPTR2","RTSDT","6","input_output_data_is_high_level","1",,
|
||||
"SCIF","SCSPTR2","CTSIO","5","ctsdt_is_not_output_to_cts2","0",,
|
||||
"SCIF","SCSPTR2","CTSIO","5","ctsdt_is_output_to_cts2","1",,
|
||||
"SCIF","SCSPTR2","CTSDT","4","input_output_data_is_low_level","0",,
|
||||
"SCIF","SCSPTR2","CTSDT","4","input_output_data_is_high_level","1",,
|
||||
"SCIF","SCSPTR2","SPB2IO","1","spb2dt_is_not_output_to_txd2","0",,
|
||||
"SCIF","SCSPTR2","SPB2IO","1","spb2dt_is_output_to_txd2","1",,
|
||||
"SCIF","SCSPTR2","SPB2DT","0","input_output_data_is_low_level","0",,
|
||||
"SCIF","SCSPTR2","SPB2DT","0","input_output_data_is_high_level","1",,
|
||||
|
BIN
regs/sh7091_bits.ods
Normal file
BIN
regs/sh7091_bits.ods
Normal file
Binary file not shown.
@ -1,6 +1,6 @@
|
||||
#include <cstdint>
|
||||
|
||||
#include "cache.hpp"
|
||||
#include "sh7091/cache.hpp"
|
||||
|
||||
extern uint32_t __bss_link_start __asm("__bss_link_start");
|
||||
extern uint32_t __bss_link_end __asm("__bss_link_end");
|
||||
|
||||
@ -1,8 +1,8 @@
|
||||
#include <cstdint>
|
||||
|
||||
#include "sh7091.hpp"
|
||||
#include "sh7091_bits.hpp"
|
||||
#include "holly.hpp"
|
||||
#include "sh7091/sh7091.hpp"
|
||||
#include "sh7091/sh7091_bits.hpp"
|
||||
#include "holly/holly.hpp"
|
||||
|
||||
enum load_command {
|
||||
CMD_NONE,
|
||||
@ -48,7 +48,8 @@ void debug(const char * s)
|
||||
{
|
||||
char c;
|
||||
while ((c = *s++)) {
|
||||
while ((sh7091.SCIF.SCFSR2 & SCFSR2__TDFE) == 0);
|
||||
using namespace scif;
|
||||
while ((sh7091.SCIF.SCFSR2 & scfsr2::tdfe::bit_mask) == 0);
|
||||
sh7091.SCIF.SCFTDR2 = (uint8_t)c;
|
||||
}
|
||||
}
|
||||
|
||||
36
sh7091/cache.cpp
Normal file
36
sh7091/cache.cpp
Normal file
@ -0,0 +1,36 @@
|
||||
#include "type.hpp"
|
||||
#include "sh7091.hpp"
|
||||
#include "sh7091_bits.hpp"
|
||||
|
||||
#include "cache.hpp"
|
||||
|
||||
extern volatile reg32 sh7091_ic_a[256][(1 << 5) / 4] __asm("sh7091_ic_a");
|
||||
extern volatile reg32 sh7091_oc_a[512][(1 << 5) / 4] __asm("sh7091_oc_a");
|
||||
|
||||
namespace cache {
|
||||
|
||||
void init()
|
||||
{
|
||||
for (int i = 0; i < 256; i++) {
|
||||
sh7091_ic_a[i][0] = 0;
|
||||
}
|
||||
|
||||
for (int i = 0; i < 512; i++) {
|
||||
sh7091_oc_a[i][0] = 0;
|
||||
}
|
||||
|
||||
using namespace ccn::ccr;
|
||||
|
||||
sh7091.CCN.CCR = ici::clear_v_bits_of_all_ic_entries // instruction cache invalidate
|
||||
| ice::ic_used // instruction cache enable
|
||||
| oci::clear_v_and_u_bits_of_all_oc_entries // operand cache invalidate
|
||||
| oce::oc_used // operand cache enable
|
||||
// | cb::copy_back_mode // enable copy-back mode for the P1 area
|
||||
;
|
||||
|
||||
sh7091.CCN.MMUCR = ccn::mmucr::at::mmu_disabled;
|
||||
|
||||
asm volatile ("nop;nop;nop;nop;nop;nop;nop;nop;");
|
||||
}
|
||||
|
||||
}
|
||||
@ -90,9 +90,9 @@ struct bsc_reg {
|
||||
reg8 _pad7[2];
|
||||
reg16 GPIOIC; /* GPIO interrupt control register */
|
||||
reg8 _pad8[1048502];
|
||||
reg8 SDMR2[65536]; /* Synchronous DRAM mode registers */
|
||||
reg32 SDMR2[16384]; /* Synchronous DRAM mode registers */
|
||||
reg8 _pad9[196608];
|
||||
reg8 SDMR3[65536]; /* Synchronous DRAM mode registers */
|
||||
reg32 SDMR3[16384]; /* Synchronous DRAM mode registers */
|
||||
};
|
||||
|
||||
static_assert((offsetof (struct bsc_reg, BCR1)) == 0x0);
|
||||
822
sh7091/sh7091_bits.hpp
Normal file
822
sh7091/sh7091_bits.hpp
Normal file
@ -0,0 +1,822 @@
|
||||
#pragma once
|
||||
|
||||
#include <cstdint>
|
||||
|
||||
#include "../float_uint32.hpp"
|
||||
|
||||
namespace ccn {
|
||||
namespace pteh {
|
||||
constexpr uint32_t VPN(uint32_t reg) { return (reg >> 10) & 0x3fffff; }
|
||||
constexpr uint32_t ASID(uint32_t reg) { return (reg >> 0) & 0xff; }
|
||||
}
|
||||
|
||||
namespace ptel {
|
||||
constexpr uint32_t PPN(uint32_t reg) { return (reg >> 10) & 0x7ffff; }
|
||||
|
||||
namespace v {
|
||||
constexpr uint32_t invalid = 0 << 8;
|
||||
constexpr uint32_t valid = 1 << 8;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 8;
|
||||
}
|
||||
|
||||
namespace sz {
|
||||
constexpr uint32_t _1_kbyte_page = 0b0000 << 4;
|
||||
constexpr uint32_t _4_kbyte_page = 0b0001 << 4;
|
||||
constexpr uint32_t _64_kbyte_page = 0b1000 << 4;
|
||||
constexpr uint32_t _1_mbyte_page = 0b1001 << 4;
|
||||
|
||||
constexpr uint32_t bit_mask = 0xf << 4;
|
||||
}
|
||||
|
||||
namespace pr {
|
||||
constexpr uint32_t read_only_in_privileged_mode = 0b00 << 5;
|
||||
constexpr uint32_t read_write_in_privileged_mode = 0b01 << 5;
|
||||
constexpr uint32_t read_only_in_privileged_and_user_mode = 0b10 << 5;
|
||||
constexpr uint32_t read_write_in_privileged_and_user_mode = 0b11 << 5;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x3 << 5;
|
||||
}
|
||||
|
||||
namespace c {
|
||||
constexpr uint32_t not_cacheable = 0 << 3;
|
||||
constexpr uint32_t cacheable = 1 << 3;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 3;
|
||||
}
|
||||
|
||||
namespace d {
|
||||
constexpr uint32_t write_has_not_been_performed = 0 << 2;
|
||||
constexpr uint32_t write_has_been_performed = 1 << 2;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 2;
|
||||
}
|
||||
|
||||
namespace sh {
|
||||
constexpr uint32_t pages_are_shared_by_processes = 0 << 1;
|
||||
constexpr uint32_t pages_are_not_shared_by_processes = 1 << 1;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 1;
|
||||
}
|
||||
|
||||
namespace wt {
|
||||
constexpr uint32_t copy_back_mode = 0 << 0;
|
||||
constexpr uint32_t write_through_mode = 1 << 0;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 0;
|
||||
}
|
||||
}
|
||||
|
||||
namespace mmucr {
|
||||
constexpr uint32_t LRUI(uint32_t reg) { return (reg >> 26) & 0x3f; }
|
||||
constexpr uint32_t URB(uint32_t reg) { return (reg >> 18) & 0x3f; }
|
||||
constexpr uint32_t URC(uint32_t reg) { return (reg >> 10) & 0x3f; }
|
||||
|
||||
namespace sqmd {
|
||||
constexpr uint32_t user_privileged_access_possible = 0 << 9;
|
||||
constexpr uint32_t privileged_access_possible = 1 << 9;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 9;
|
||||
}
|
||||
|
||||
namespace sv {
|
||||
constexpr uint32_t multiple_virtual_memory_mode = 0 << 8;
|
||||
constexpr uint32_t single_virtual_memory_mode = 1 << 8;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 8;
|
||||
}
|
||||
|
||||
namespace ti {
|
||||
constexpr uint32_t invalidate_all_utlb_itlb_bits = 1 << 2;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 2;
|
||||
}
|
||||
|
||||
namespace at {
|
||||
constexpr uint32_t mmu_disabled = 0 << 0;
|
||||
constexpr uint32_t mmu_enabled = 1 << 0;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 0;
|
||||
}
|
||||
}
|
||||
|
||||
namespace basra {
|
||||
constexpr uint32_t basa(uint32_t num) { return (num & 0xff) << 0; }
|
||||
}
|
||||
|
||||
namespace basrb {
|
||||
constexpr uint32_t basa(uint32_t num) { return (num & 0xff) << 0; }
|
||||
}
|
||||
|
||||
namespace ccr {
|
||||
namespace iix {
|
||||
constexpr uint32_t address_bits_12_5_used_for_ic_entry_selection = 0 << 15;
|
||||
constexpr uint32_t address_bits_25_and_11_5_used_for_ic_entry_selection = 1 << 15;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 15;
|
||||
}
|
||||
|
||||
namespace ici {
|
||||
constexpr uint32_t clear_v_bits_of_all_ic_entries = 1 << 11;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 11;
|
||||
}
|
||||
|
||||
namespace ice {
|
||||
constexpr uint32_t ic_not_used = 0 << 8;
|
||||
constexpr uint32_t ic_used = 1 << 8;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 8;
|
||||
}
|
||||
|
||||
namespace oix {
|
||||
constexpr uint32_t address_bits_13_5_used_for_oc_entry_selection = 0 << 7;
|
||||
constexpr uint32_t address_bits_25_and_12_5_used_for_oc_entry_selection = 1 << 7;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 7;
|
||||
}
|
||||
|
||||
namespace ora {
|
||||
constexpr uint32_t _16_kbytes_used_as_cache = 0 << 5;
|
||||
constexpr uint32_t _8_kbytes_used_as_cache_8_kbytes_used_as_ram = 1 << 5;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 5;
|
||||
}
|
||||
|
||||
namespace oci {
|
||||
constexpr uint32_t clear_v_and_u_bits_of_all_oc_entries = 1 << 3;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 3;
|
||||
}
|
||||
|
||||
namespace cb {
|
||||
constexpr uint32_t write_through_mode = 0 << 2;
|
||||
constexpr uint32_t copy_back_mode = 1 << 2;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 2;
|
||||
}
|
||||
|
||||
namespace wt {
|
||||
constexpr uint32_t copy_back_mode = 0 << 1;
|
||||
constexpr uint32_t write_through_mode = 1 << 1;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 1;
|
||||
}
|
||||
|
||||
namespace oce {
|
||||
constexpr uint32_t oc_not_used = 0 << 0;
|
||||
constexpr uint32_t oc_used = 1 << 0;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 0;
|
||||
}
|
||||
}
|
||||
|
||||
namespace tra {
|
||||
constexpr uint32_t imm(uint32_t reg) { return (reg >> 2) & 0xff; }
|
||||
}
|
||||
|
||||
namespace expevt {
|
||||
constexpr uint32_t exception_code(uint32_t reg) { return (reg >> 0) & 0xfff; }
|
||||
}
|
||||
|
||||
namespace intevt {
|
||||
constexpr uint32_t exception_code(uint32_t reg) { return (reg >> 0) & 0xfff; }
|
||||
}
|
||||
|
||||
namespace ptea {
|
||||
namespace tc {
|
||||
constexpr uint32_t area_5_is_used = 0 << 3;
|
||||
constexpr uint32_t area_6_is_used = 1 << 3;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 3;
|
||||
}
|
||||
|
||||
namespace sa {
|
||||
constexpr uint32_t undefined = 0b000 << 0;
|
||||
constexpr uint32_t variable_size_io_space = 0b001 << 0;
|
||||
constexpr uint32_t _8_bit_io_space = 0b010 << 0;
|
||||
constexpr uint32_t _16_bit_io_space = 0b011 << 0;
|
||||
constexpr uint32_t _8_bit_common_memory_space = 0b100 << 0;
|
||||
constexpr uint32_t _16_bit_common_memory_space = 0b101 << 0;
|
||||
constexpr uint32_t _8_bit_attribute_memory_space = 0b110 << 0;
|
||||
constexpr uint32_t _16_bit_attribute_memory_space = 0b111 << 0;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x7 << 0;
|
||||
}
|
||||
}
|
||||
|
||||
namespace qacr0 {
|
||||
constexpr uint32_t area(uint32_t num) { return (num & 0x7) << 2; }
|
||||
}
|
||||
|
||||
namespace qacr1 {
|
||||
constexpr uint32_t area(uint32_t num) { return (num & 0x7) << 2; }
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
namespace dmac {
|
||||
namespace dmatcr {
|
||||
constexpr uint32_t transfer_count(uint32_t num) { return (num & 0xffffff) << 0; }
|
||||
}
|
||||
|
||||
namespace chcr {
|
||||
namespace ssa {
|
||||
constexpr uint32_t reserved_in_pcmcia_access = 0b000 << 29;
|
||||
constexpr uint32_t dynamic_bus_sizing_io_space = 0b001 << 29;
|
||||
constexpr uint32_t _8_bit_io_space = 0b010 << 29;
|
||||
constexpr uint32_t _16_bit_io_space = 0b011 << 29;
|
||||
constexpr uint32_t _8_bit_common_memory_space = 0b100 << 29;
|
||||
constexpr uint32_t _16_bit_common_memory_space = 0b101 << 29;
|
||||
constexpr uint32_t _8_bit_attribute_memory_space = 0b110 << 29;
|
||||
constexpr uint32_t _16_bit_attribute_memory_space = 0b111 << 29;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x7 << 29;
|
||||
}
|
||||
|
||||
namespace stc {
|
||||
constexpr uint32_t c5_space_wait_cycle_selection = 0 << 28;
|
||||
constexpr uint32_t c6_space_wait_cycle_selection = 1 << 28;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 28;
|
||||
}
|
||||
|
||||
namespace dsa {
|
||||
constexpr uint32_t reserved_in_pcmcia_access = 0b000 << 25;
|
||||
constexpr uint32_t dynamic_bus_sizing_io_space = 0b001 << 25;
|
||||
constexpr uint32_t _8_bit_io_space = 0b010 << 25;
|
||||
constexpr uint32_t _16_bit_io_space = 0b011 << 25;
|
||||
constexpr uint32_t _8_bit_common_memory_space = 0b100 << 25;
|
||||
constexpr uint32_t _16_bit_common_memory_space = 0b101 << 25;
|
||||
constexpr uint32_t _8_bit_attribute_memory_space = 0b110 << 25;
|
||||
constexpr uint32_t _16_bit_attribute_memory_space = 0b111 << 25;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x7 << 25;
|
||||
}
|
||||
|
||||
namespace dtc {
|
||||
constexpr uint32_t c5_space_wait_cycle_selection = 0 << 24;
|
||||
constexpr uint32_t c6_space_wait_cycle_selection = 1 << 24;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 24;
|
||||
}
|
||||
|
||||
namespace ds {
|
||||
constexpr uint32_t low_level_detection = 0 << 19;
|
||||
constexpr uint32_t falling_edge_detection = 1 << 19;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 19;
|
||||
}
|
||||
|
||||
namespace rl {
|
||||
constexpr uint32_t drak_is_an_active_high = 0 << 18;
|
||||
constexpr uint32_t drak_is_an_active_low = 1 << 18;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 18;
|
||||
}
|
||||
|
||||
namespace am {
|
||||
constexpr uint32_t dack_is_output_in_read_cycle = 0 << 17;
|
||||
constexpr uint32_t dack_is_output_in_write_cycle = 1 << 17;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 17;
|
||||
}
|
||||
|
||||
namespace al {
|
||||
constexpr uint32_t active_high_output = 0 << 16;
|
||||
constexpr uint32_t active_low_output = 1 << 16;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 16;
|
||||
}
|
||||
|
||||
namespace dm {
|
||||
constexpr uint32_t destination_address_fixed = 0b00 << 14;
|
||||
constexpr uint32_t destination_address_incremented = 0b01 << 14;
|
||||
constexpr uint32_t destination_address_decremented = 0b10 << 14;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x3 << 14;
|
||||
}
|
||||
|
||||
namespace sm {
|
||||
constexpr uint32_t source_address_fixed = 0b00 << 12;
|
||||
constexpr uint32_t source_address_incremented = 0b01 << 12;
|
||||
constexpr uint32_t source_address_decremented = 0b10 << 12;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x3 << 12;
|
||||
}
|
||||
|
||||
namespace rs {
|
||||
constexpr uint32_t resource_select(uint32_t num) { return (num & 0xf) << 8; }
|
||||
|
||||
constexpr uint32_t bit_mask = 0xf << 8;
|
||||
}
|
||||
|
||||
namespace tm {
|
||||
constexpr uint32_t cycle_steal_mode = 0 << 7;
|
||||
constexpr uint32_t cycle_burst_mode = 1 << 7;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 7;
|
||||
}
|
||||
|
||||
namespace ts {
|
||||
constexpr uint32_t _64_bit = 0b000 << 4;
|
||||
constexpr uint32_t _8_bit = 0b001 << 4;
|
||||
constexpr uint32_t _16_bit = 0b010 << 4;
|
||||
constexpr uint32_t _32_bit = 0b011 << 4;
|
||||
constexpr uint32_t _32_byte = 0b100 << 4;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x7 << 4;
|
||||
}
|
||||
|
||||
namespace ie {
|
||||
constexpr uint32_t interrupt_request_not_generated = 0 << 2;
|
||||
constexpr uint32_t interrupt_request_generated = 1 << 2;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 2;
|
||||
}
|
||||
|
||||
namespace te {
|
||||
constexpr uint32_t transfers_not_completed = 0 << 1;
|
||||
constexpr uint32_t transfers_completed = 1 << 1;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 1;
|
||||
}
|
||||
|
||||
namespace de {
|
||||
constexpr uint32_t channel_operation_disabled = 0 << 0;
|
||||
constexpr uint32_t channel_operation_enabled = 1 << 0;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 0;
|
||||
}
|
||||
}
|
||||
|
||||
namespace dmaor {
|
||||
namespace ddt {
|
||||
constexpr uint32_t normal_dma_mode = 0 << 15;
|
||||
constexpr uint32_t on_demand_data_transfer_mode = 1 << 15;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 15;
|
||||
}
|
||||
|
||||
namespace pr {
|
||||
constexpr uint32_t ch0_ch1_ch2_ch3 = 0b00 << 8;
|
||||
constexpr uint32_t ch0_ch2_ch3_ch1 = 0b01 << 8;
|
||||
constexpr uint32_t ch2_ch0_ch1_ch3 = 0b10 << 8;
|
||||
constexpr uint32_t round_robin = 0b11 << 8;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x3 << 8;
|
||||
}
|
||||
|
||||
namespace ae {
|
||||
constexpr uint32_t no_address_error__dma_transfer_enabled = 0 << 2;
|
||||
constexpr uint32_t address_error__dma_transfer_disabled = 1 << 2;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 2;
|
||||
}
|
||||
|
||||
namespace nmif {
|
||||
constexpr uint32_t no_nmi__dma_transfer_enabled = 0 << 1;
|
||||
constexpr uint32_t nmi__dma_transfer_disabled = 1 << 1;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 1;
|
||||
}
|
||||
|
||||
namespace dme {
|
||||
constexpr uint32_t operation_disabled_on_all_channels = 0 << 0;
|
||||
constexpr uint32_t operation_enabled_on_all_channels = 1 << 0;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 0;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
namespace intc {
|
||||
namespace icr {
|
||||
namespace nmil {
|
||||
constexpr uint32_t pin_input_level_is_low = 0 << 15;
|
||||
constexpr uint32_t pin_input_level_is_high = 1 << 15;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 15;
|
||||
}
|
||||
|
||||
namespace mai {
|
||||
constexpr uint32_t interrupts_enabled_while_nmi_pin_is_low = 0 << 14;
|
||||
constexpr uint32_t interrupts_disabled_while_nmi_pin_is_low = 1 << 14;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 14;
|
||||
}
|
||||
|
||||
namespace nmib {
|
||||
constexpr uint32_t interrupt_requests_witheld = 0 << 9;
|
||||
constexpr uint32_t interrupt_requests_detected = 1 << 9;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 9;
|
||||
}
|
||||
|
||||
namespace nmie {
|
||||
constexpr uint32_t interrupt_on_falling_edge_of_nmi = 0 << 8;
|
||||
constexpr uint32_t interrupt_on_rising_edge_of_nmi = 1 << 8;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 8;
|
||||
}
|
||||
|
||||
namespace irlm {
|
||||
constexpr uint32_t level_encoded_interrupt_requests = 0 << 7;
|
||||
constexpr uint32_t independent_interrupt_request = 1 << 7;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 7;
|
||||
}
|
||||
}
|
||||
|
||||
namespace ipra {
|
||||
constexpr uint32_t TMU0(uint32_t num) { return (num & 0xf) << 12; }
|
||||
constexpr uint32_t TMU1(uint32_t num) { return (num & 0xf) << 8; }
|
||||
constexpr uint32_t TMU2(uint32_t num) { return (num & 0xf) << 4; }
|
||||
constexpr uint32_t RTC(uint32_t num) { return (num & 0xf) << 0; }
|
||||
}
|
||||
|
||||
namespace iprb {
|
||||
constexpr uint32_t WDT(uint32_t num) { return (num & 0xf) << 12; }
|
||||
constexpr uint32_t REF(uint32_t num) { return (num & 0xf) << 8; }
|
||||
constexpr uint32_t SCI1(uint32_t num) { return (num & 0xf) << 4; }
|
||||
}
|
||||
|
||||
namespace iprc {
|
||||
constexpr uint32_t GPIO(uint32_t num) { return (num & 0xf) << 12; }
|
||||
constexpr uint32_t DMAC(uint32_t num) { return (num & 0xf) << 8; }
|
||||
constexpr uint32_t SCIF(uint32_t num) { return (num & 0xf) << 4; }
|
||||
constexpr uint32_t UDI(uint32_t num) { return (num & 0xf) << 0; }
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
namespace tmu {
|
||||
namespace tocr {
|
||||
namespace tcoe {
|
||||
constexpr uint32_t tclk_is_external_clock_or_input_capture = 0 << 0;
|
||||
constexpr uint32_t tclk_is_on_chip_rtc = 1 << 0;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 0;
|
||||
}
|
||||
}
|
||||
|
||||
namespace tstr {
|
||||
namespace str2 {
|
||||
constexpr uint32_t counter_start = 1 << 2;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 2;
|
||||
}
|
||||
|
||||
namespace str1 {
|
||||
constexpr uint32_t counter_start = 1 << 1;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 1;
|
||||
}
|
||||
|
||||
namespace str0 {
|
||||
constexpr uint32_t counter_start = 1 << 0;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 0;
|
||||
}
|
||||
}
|
||||
|
||||
namespace tcr0 {
|
||||
constexpr uint32_t UNF = 1 << 8;
|
||||
constexpr uint32_t UNIE = 1 << 5;
|
||||
|
||||
namespace ckeg {
|
||||
constexpr uint32_t rising = 0b00 << 3;
|
||||
constexpr uint32_t falling = 0b01 << 3;
|
||||
constexpr uint32_t rising_falling = 0b10 << 3;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x3 << 3;
|
||||
}
|
||||
|
||||
namespace tpsc {
|
||||
constexpr uint32_t p_phi_4 = 0b000 << 0;
|
||||
constexpr uint32_t p_phi_16 = 0b001 << 0;
|
||||
constexpr uint32_t p_phi_64 = 0b010 << 0;
|
||||
constexpr uint32_t p_phi_256 = 0b011 << 0;
|
||||
constexpr uint32_t p_phi_1024 = 0b100 << 0;
|
||||
constexpr uint32_t rtc_output = 0b110 << 0;
|
||||
constexpr uint32_t external = 0b111 << 0;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x7 << 0;
|
||||
}
|
||||
}
|
||||
|
||||
namespace tcr1 {
|
||||
constexpr uint32_t UNF = 1 << 8;
|
||||
constexpr uint32_t UNIE = 1 << 5;
|
||||
|
||||
namespace ckeg {
|
||||
constexpr uint32_t rising = 0b00 << 3;
|
||||
constexpr uint32_t falling = 0b01 << 3;
|
||||
constexpr uint32_t rising_falling = 0b10 << 3;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x3 << 3;
|
||||
}
|
||||
|
||||
namespace tpsc {
|
||||
constexpr uint32_t p_phi_4 = 0b000 << 0;
|
||||
constexpr uint32_t p_phi_16 = 0b001 << 0;
|
||||
constexpr uint32_t p_phi_64 = 0b010 << 0;
|
||||
constexpr uint32_t p_phi_256 = 0b011 << 0;
|
||||
constexpr uint32_t p_phi_1024 = 0b100 << 0;
|
||||
constexpr uint32_t rtc_output = 0b110 << 0;
|
||||
constexpr uint32_t external = 0b111 << 0;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x7 << 0;
|
||||
}
|
||||
}
|
||||
|
||||
namespace tcr2 {
|
||||
constexpr uint32_t ICPF = 1 << 9;
|
||||
constexpr uint32_t UNF = 1 << 8;
|
||||
|
||||
namespace icpe {
|
||||
constexpr uint32_t disabled = 0b00 << 6;
|
||||
constexpr uint32_t enabled = 0b10 << 6;
|
||||
constexpr uint32_t enabled_with_interrupts = 0b11 << 6;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x3 << 6;
|
||||
}
|
||||
|
||||
constexpr uint32_t UNIE = 1 << 5;
|
||||
|
||||
namespace ckeg {
|
||||
constexpr uint32_t rising = 0b00 << 3;
|
||||
constexpr uint32_t falling = 0b01 << 3;
|
||||
constexpr uint32_t rising_falling = 0b10 << 3;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x3 << 3;
|
||||
}
|
||||
|
||||
namespace tpsc {
|
||||
constexpr uint32_t p_phi_4 = 0b000 << 0;
|
||||
constexpr uint32_t p_phi_16 = 0b001 << 0;
|
||||
constexpr uint32_t p_phi_64 = 0b010 << 0;
|
||||
constexpr uint32_t p_phi_256 = 0b011 << 0;
|
||||
constexpr uint32_t p_phi_1024 = 0b100 << 0;
|
||||
constexpr uint32_t rtc_output = 0b110 << 0;
|
||||
constexpr uint32_t external = 0b111 << 0;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x7 << 0;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
namespace scif {
|
||||
namespace scsmr2 {
|
||||
namespace chr {
|
||||
constexpr uint32_t _8_bit_data = 0 << 6;
|
||||
constexpr uint32_t _7_bit_data = 1 << 6;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 6;
|
||||
}
|
||||
|
||||
namespace pe {
|
||||
constexpr uint32_t parity_disabled = 0 << 5;
|
||||
constexpr uint32_t parity_enabled = 1 << 5;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 5;
|
||||
}
|
||||
|
||||
namespace oe {
|
||||
constexpr uint32_t even_parity = 0 << 4;
|
||||
constexpr uint32_t odd_parity = 1 << 4;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 4;
|
||||
}
|
||||
|
||||
namespace stop {
|
||||
constexpr uint32_t _1_stop_bit = 0 << 3;
|
||||
constexpr uint32_t _2_stop_bits = 1 << 3;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 3;
|
||||
}
|
||||
|
||||
namespace cks {
|
||||
constexpr uint32_t p_phi_clock = 0b00 << 0;
|
||||
constexpr uint32_t p_phi_4_clock = 0b01 << 0;
|
||||
constexpr uint32_t p_phi_16_clock = 0b10 << 0;
|
||||
constexpr uint32_t p_phi_64_clock = 0b11 << 0;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x3 << 0;
|
||||
}
|
||||
}
|
||||
|
||||
namespace scscr2 {
|
||||
namespace tie {
|
||||
constexpr uint32_t transmit_fifo_data_empty_interrupt_disabled = 0 << 7;
|
||||
constexpr uint32_t transmit_fifo_data_empty_interrupt_enabled = 1 << 7;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 7;
|
||||
}
|
||||
|
||||
namespace rie {
|
||||
constexpr uint32_t request_disabled = 0 << 6;
|
||||
constexpr uint32_t request_enabled = 1 << 6;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 6;
|
||||
}
|
||||
|
||||
namespace te {
|
||||
constexpr uint32_t transmission_disabled = 0 << 5;
|
||||
constexpr uint32_t transmission_enabled = 1 << 5;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 5;
|
||||
}
|
||||
|
||||
namespace re {
|
||||
constexpr uint32_t reception_disabled = 0 << 4;
|
||||
constexpr uint32_t reception_enabled = 1 << 4;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 4;
|
||||
}
|
||||
|
||||
namespace reie {
|
||||
constexpr uint32_t requests_disabled = 0 << 3;
|
||||
constexpr uint32_t requests_enabled = 1 << 3;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 3;
|
||||
}
|
||||
|
||||
namespace cke1 {
|
||||
constexpr uint32_t sck2_pin_functions_as_input_pin = 0 << 1;
|
||||
constexpr uint32_t sck2_pin_functions_as_clock_input = 1 << 1;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 1;
|
||||
}
|
||||
}
|
||||
|
||||
namespace scfsr2 {
|
||||
namespace per3_0 {
|
||||
constexpr uint32_t number_of_parity_errors(uint32_t reg) { return (reg >> 12) & 0xf; }
|
||||
|
||||
constexpr uint32_t bit_mask = 0xf << 12;
|
||||
}
|
||||
|
||||
namespace fer3_0 {
|
||||
constexpr uint32_t number_of_framing_errors(uint32_t reg) { return (reg >> 8) & 0xf; }
|
||||
|
||||
constexpr uint32_t bit_mask = 0xf << 8;
|
||||
}
|
||||
|
||||
namespace er {
|
||||
constexpr uint32_t no_framing_error_or_parity_error = 0 << 7;
|
||||
constexpr uint32_t framing_error_or_parity_error = 1 << 7;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 7;
|
||||
}
|
||||
|
||||
namespace tend {
|
||||
constexpr uint32_t transmission_in_progress = 0 << 6;
|
||||
constexpr uint32_t transmission_has_ended = 1 << 6;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 6;
|
||||
}
|
||||
|
||||
namespace tdfe {
|
||||
constexpr uint32_t transmit_data_bytes_does_exceed_trigger = 0 << 5;
|
||||
constexpr uint32_t transmit_data_bytes_does_not_exceed_trigger = 1 << 5;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 5;
|
||||
}
|
||||
|
||||
namespace brk {
|
||||
constexpr uint32_t break_not_received = 0 << 4;
|
||||
constexpr uint32_t break_received = 1 << 4;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 4;
|
||||
}
|
||||
|
||||
namespace fer {
|
||||
constexpr uint32_t no_framing_error = 0 << 3;
|
||||
constexpr uint32_t framing_error = 1 << 3;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 3;
|
||||
}
|
||||
|
||||
namespace per {
|
||||
constexpr uint32_t parity_error = 0 << 2;
|
||||
constexpr uint32_t no_parity_error = 1 << 2;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 2;
|
||||
}
|
||||
|
||||
namespace rdf {
|
||||
constexpr uint32_t receive_data_bytes_less_than_receive_trigger = 0 << 1;
|
||||
constexpr uint32_t receive_data_bytes_greater_than_or_equal_receive_trigger = 1 << 1;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 1;
|
||||
}
|
||||
|
||||
namespace dr {
|
||||
constexpr uint32_t reception_is_in_progress = 0 << 0;
|
||||
constexpr uint32_t no_further_data_has_arrived = 1 << 0;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 0;
|
||||
}
|
||||
}
|
||||
|
||||
namespace scfcr2 {
|
||||
namespace rtrg {
|
||||
constexpr uint32_t trigger_on_1_byte = 0b00 << 6;
|
||||
constexpr uint32_t trigger_on_4_bytes = 0b01 << 6;
|
||||
constexpr uint32_t trigger_on_8_bytes = 0b10 << 6;
|
||||
constexpr uint32_t trigger_on_14_byte = 0b11 << 6;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x3 << 6;
|
||||
}
|
||||
|
||||
namespace ttrg {
|
||||
constexpr uint32_t trigger_on_8_bytes = 0b00 << 4;
|
||||
constexpr uint32_t trigger_on_4_bytes = 0b01 << 4;
|
||||
constexpr uint32_t trigger_on_2_bytes = 0b10 << 4;
|
||||
constexpr uint32_t trigger_on_1_bytes = 0b11 << 4;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x3 << 4;
|
||||
}
|
||||
|
||||
namespace mce {
|
||||
constexpr uint32_t modem_signals_disabled = 0 << 3;
|
||||
constexpr uint32_t modem_signals_enabled = 1 << 3;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 3;
|
||||
}
|
||||
|
||||
namespace tfrst {
|
||||
constexpr uint32_t reset_operation_disabled = 0 << 2;
|
||||
constexpr uint32_t reset_operation_enabled = 1 << 2;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 2;
|
||||
}
|
||||
|
||||
namespace rfrst {
|
||||
constexpr uint32_t reset_operation_disabled = 0 << 1;
|
||||
constexpr uint32_t reset_operation_enabled = 1 << 1;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 1;
|
||||
}
|
||||
|
||||
namespace loop {
|
||||
constexpr uint32_t loopback_test_disabled = 0 << 0;
|
||||
constexpr uint32_t loopback_test_enabled = 1 << 0;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 0;
|
||||
}
|
||||
}
|
||||
|
||||
namespace scfdr2 {
|
||||
constexpr uint32_t transmit_data_bytes(uint32_t reg) { return (reg >> 8) & 0x1f; }
|
||||
constexpr uint32_t receive_data_bytes(uint32_t reg) { return (reg >> 0) & 0x1f; }
|
||||
}
|
||||
|
||||
namespace scsptr2 {
|
||||
namespace rtsio {
|
||||
constexpr uint32_t rtsdt_not_output_to_rts2 = 0 << 7;
|
||||
constexpr uint32_t rtsdt_output_to_rts2 = 1 << 7;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 7;
|
||||
}
|
||||
|
||||
namespace rtsdt {
|
||||
constexpr uint32_t input_output_data_is_low_level = 0 << 6;
|
||||
constexpr uint32_t input_output_data_is_high_level = 1 << 6;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 6;
|
||||
}
|
||||
|
||||
namespace ctsio {
|
||||
constexpr uint32_t ctsdt_is_not_output_to_cts2 = 0 << 5;
|
||||
constexpr uint32_t ctsdt_is_output_to_cts2 = 1 << 5;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 5;
|
||||
}
|
||||
|
||||
namespace ctsdt {
|
||||
constexpr uint32_t input_output_data_is_low_level = 0 << 4;
|
||||
constexpr uint32_t input_output_data_is_high_level = 1 << 4;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 4;
|
||||
}
|
||||
|
||||
namespace spb2io {
|
||||
constexpr uint32_t spb2dt_is_not_output_to_txd2 = 0 << 1;
|
||||
constexpr uint32_t spb2dt_is_output_to_txd2 = 1 << 1;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 1;
|
||||
}
|
||||
|
||||
namespace spb2dt {
|
||||
constexpr uint32_t input_output_data_is_low_level = 0 << 0;
|
||||
constexpr uint32_t input_output_data_is_high_level = 1 << 0;
|
||||
|
||||
constexpr uint32_t bit_mask = 0x1 << 0;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
101
sh7091_bits.hpp
101
sh7091_bits.hpp
@ -1,101 +0,0 @@
|
||||
#define CCR__IIX (1 << 15)
|
||||
#define CCR__ICI (1 << 11)
|
||||
#define CCR__ICE (1 << 8)
|
||||
#define CCR__OIX (1 << 7)
|
||||
#define CCR__ORA (1 << 5)
|
||||
#define CCR__OCI (1 << 4)
|
||||
#define CCR__CB (1 << 2)
|
||||
#define CCR__WT (1 << 1)
|
||||
#define CCR__OCE (1 << 0)
|
||||
|
||||
#define PDTRA__MASK (0b11 << 8)
|
||||
#define PDTRA__VGA (0b00 << 8)
|
||||
#define PDTRA__RESERVED (0b01 << 8)
|
||||
#define PDTRA__RGB (0b10 << 8)
|
||||
#define PDTRA__AV (0b11 << 8)
|
||||
|
||||
#define SCFCR2__TFRST (1 << 2)
|
||||
#define SCFCR2__RFRST (1 << 1)
|
||||
|
||||
#define SCSCR2__TE (1 << 5)
|
||||
#define SCSCR2__RE (1 << 4)
|
||||
|
||||
#define SCFSR2__ER (1 << 7) /* read error */
|
||||
#define SCFSR2__TEND (1 << 6) /* transmit end */
|
||||
#define SCFSR2__TDFE (1 << 5) /* transmit fifo data empty */
|
||||
#define SCFSR2__BRK (1 << 4) /* break detect */
|
||||
#define SCFSR2__FER (1 << 3) /* framing error */
|
||||
#define SCFSR2__PER (1 << 2) /* parity error */
|
||||
#define SCFSR2__RDF (1 << 1) /* receive FIFO data full */
|
||||
#define SCFSR2__DR (1 << 0) /* receive data ready */
|
||||
|
||||
#define DMAOR__DDT (1 << 15) /* on-demand data transfer mode */
|
||||
/* priority mode */
|
||||
#define DMAOR__PR__CH0_CH1_CH2_CH3 (0b11 << 8)
|
||||
#define DMAOR__PR__CH0_CH2_CH3_CH1 (0b01 << 8)
|
||||
#define DMAOR__PR__CH2_CH0_CH1_CH3 (0b10 << 8)
|
||||
#define DMAOR__PR__ROUND_ROBIN (0b11 << 8)
|
||||
#define DMAOR__AE (1 << 2) /* address error flag; clear-only */
|
||||
#define DMAOR__NMIF (1 << 1) /* non-maskable interrupt flag; clear-only */
|
||||
#define DMAOR__DME (1 << 0) /* DMAC master enable */
|
||||
|
||||
/* source address space attribute specification */
|
||||
#define CHCR2__SSA__RESERVED_IN_PCMCIA_ACCESS (0b000 << 29)
|
||||
#define CHCR2__SSA__DYNAMIC_BUS_SIZING_IO_SPACE (0b001 << 29)
|
||||
#define CHCR2__SSA__8BIT_IO_SPACE (0b010 << 29)
|
||||
#define CHCR2__SSA__16BIT_IO_SPACE (0b011 << 29)
|
||||
#define CHCR2__SSA__8BIT_COMMON_MEMORY_SPACE (0b100 << 29)
|
||||
#define CHCR2__SSA__16BIT_COMMON_MEMORY_SPACE (0b101 << 29)
|
||||
#define CHCR2__SSA__8BIT_ATTRIBUTE_MEMORY_SPACE (0b110 << 29)
|
||||
#define CHCR2__SSA__16BIT_ATTRIBUTE_MEMORY_SPACE (0b111 << 29)
|
||||
/* source address wait control select */
|
||||
#define CHCR2__STC__C5_SPACE_WAIT_CYCLE_SELECTION (0 << 28)
|
||||
#define CHCR2__STC__C6_SPACE_WAIT_CYCLE_SELECTION (1 << 28)
|
||||
/* destination address space attribute specification */
|
||||
#define CHCR2__DSA__RESERVED_IN_PCMCIA_ACCESS (0b000 << 25)
|
||||
#define CHCR2__DSA__DYNAMIC_BUS_SIZING_IO_SPACE (0b001 << 25)
|
||||
#define CHCR2__DSA__8BIT_IO_SPACE (0b010 << 25)
|
||||
#define CHCR2__DSA__16BIT_IO_SPACE (0b011 << 25)
|
||||
#define CHCR2__DSA__8BIT_COMMON_MEMORY_SPACE (0b100 << 25)
|
||||
#define CHCR2__DSA__16BIT_COMMON_MEMORY_SPACE (0b101 << 25)
|
||||
#define CHCR2__DSA__8BIT_ATTRIBUTE_MEMORY_SPACE (0b110 << 25)
|
||||
#define CHCR2__DSA__16BIT_ATTRIBUTE_MEMORY_SPACE (0b111 << 25)
|
||||
/* destination address wait control select */
|
||||
#define CHCR2__DTC__C5_SPACE_WAIT_CYCLE_SELECTION (0 << 24)
|
||||
#define CHCR2__DTC__C6_SPACE_WAIT_CYCLE_SELECTION (1 << 24)
|
||||
/* DREQ select */
|
||||
#define CHCR2__DS__LOW_LEVEL_DETECTION (0 << 19)
|
||||
#define CHCR2__DS__FALLING_EDGE_DETECTION (1 << 19)
|
||||
/* request check level */
|
||||
#define CHCR2__RL__DRAK_IS_AN_ACTIVE_HIGH_OUTPUT (0 << 18)
|
||||
#define CHCR2__RL__DRAK_IS_AN_ACTIVE_LOW_OUTPUT (1 << 18)
|
||||
/* acknowledge mode */
|
||||
#define CHCR2__AM__DACK_IS_OUTPUT_IN_READ_CYCLE (0 << 17)
|
||||
#define CHCR2__AM__DACK_IS_OUTPUT_IN_WRITE_CYCLE (1 << 17)
|
||||
/* acknowledge level */
|
||||
#define CHCR2__AL__ACTIVE_HIGH_OUTPUT (0 << 16)
|
||||
#define CHCR2__AL__ACTIVE_LOW_OUTPUT (1 << 16)
|
||||
/* destination address mode */
|
||||
#define CHCR2__DM__DESTINATION_ADDRESS_FIXED (0b00 << 14)
|
||||
#define CHCR2__DM__DESTINATION_ADDRESS_INCREMENTED (0b01 << 14)
|
||||
#define CHCR2__DM__DESTINATION_ADDRESS_DECREMENTED (0b10 << 14)
|
||||
/* source address mode */
|
||||
#define CHCR2__SM__SOURCE_ADDRESS_FIXED (0b00 << 12)
|
||||
#define CHCR2__SM__SOURCE_ADDRESS_INCREMENTED (0b01 << 12)
|
||||
#define CHCR2__SM__SOURCE_ADDRESS_DECREMENTED (0b10 << 12)
|
||||
/* resource select */
|
||||
#define CHCR2__RS(n) (((n) & 0b1111) << 8)
|
||||
/* transmit mode */
|
||||
#define CHCR2__TM__CYCLE_STEAL_MODE (0 << 7)
|
||||
#define CHCR2__TM__BURST_MODE (1 << 7)
|
||||
/* transmit size */
|
||||
#define CHCR2__TS__64_BIT (0b000 << 4)
|
||||
#define CHCR2__TS__8_BIT (0b001 << 4)
|
||||
#define CHCR2__TS__16_BIT (0b010 << 4)
|
||||
#define CHCR2__TS__32_BIT (0b011 << 4)
|
||||
#define CHCR2__TS__32_BYTE (0b100 << 4)
|
||||
#define CHCR2__IE (1 << 2) /* interrupt enable */
|
||||
#define CHCR2__TE (1 << 1) /* transfer end; clear only */
|
||||
#define CHCR2__DE (1 << 0) /* DMAC (channel) enable */
|
||||
|
||||
#define DMATCR2__TRANSFER_COUNT(n) (((n) & 0xffffff) << 0)
|
||||
14
vga.cpp
14
vga.cpp
@ -1,8 +1,8 @@
|
||||
#include <cstdint>
|
||||
|
||||
#include "sh7091.hpp"
|
||||
#include "sh7091_bits.hpp"
|
||||
#include "holly.hpp"
|
||||
#include "sh7091/sh7091.hpp"
|
||||
#include "sh7091/sh7091_bits.hpp"
|
||||
#include "holly/holly.hpp"
|
||||
#include "holly/core_bits.hpp"
|
||||
#include "aica.hpp"
|
||||
#include "memorymap.hpp"
|
||||
@ -10,14 +10,16 @@
|
||||
#include "vga.hpp"
|
||||
#include "rgb.hpp"
|
||||
|
||||
/*
|
||||
uint32_t get_cable_type()
|
||||
{
|
||||
/* set all pins to input */
|
||||
// set all pins to input
|
||||
sh7091.BSC.PCTRA = 0;
|
||||
|
||||
/* get cable type from pins 9 + 8 */
|
||||
// get cable type from pins 9 + 8
|
||||
return sh7091.BSC.PDTRA & PDTRA__MASK;
|
||||
}
|
||||
*/
|
||||
|
||||
void vga1()
|
||||
{
|
||||
@ -117,8 +119,6 @@ void v_sync_out()
|
||||
|
||||
void vga()
|
||||
{
|
||||
get_cable_type();
|
||||
|
||||
holly.SOFTRESET = softreset::sdram_if_soft_reset
|
||||
| softreset::pipeline_soft_reset
|
||||
| softreset::ta_soft_reset;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user