diff --git a/cache.cpp b/cache.cpp
deleted file mode 100644
index 8dea9e6..0000000
--- a/cache.cpp
+++ /dev/null
@@ -1,34 +0,0 @@
-#include "type.hpp"
-#include "sh7091.hpp"
-#include "sh7091_bits.hpp"
-
-#include "cache.hpp"
-
-extern volatile reg32 sh7091_ic_a[256][(1 << 5) / 4] __asm("sh7091_ic_a");
-extern volatile reg32 sh7091_oc_a[512][(1 << 5) / 4] __asm("sh7091_oc_a");
-
-namespace cache {
-
-void init()
-{
-  for (int i = 0; i < 256; i++) {
-    sh7091_ic_a[i][0] = 0;
-  }
-
-  for (int i = 0; i < 512; i++) {
-    sh7091_oc_a[i][0] = 0;
-  }
-
-  sh7091.CCN.CCR = CCR__ICI // instruction cache invalidate
-                 | CCR__ICE // instruction cache enable
-                 | CCR__OCI // operand cache invalidate
-                 | CCR__OCE // operand cache enable
-              // | CCR__CB  // enable copy-back mode for the P1 area
-                 ;
-
-  sh7091.CCN.MMUCR = 0;
-
-  asm volatile ("nop;nop;nop;nop;nop;nop;nop;nop;");
-}
-
-}
diff --git a/common.mk b/common.mk
index 5a0d1f9..8b853bc 100644
--- a/common.mk
+++ b/common.mk
@@ -55,7 +55,7 @@ IP_OBJ = \
 START_OBJ = \
 	start.o \
 	runtime.o \
-	cache.o
+	sh7091/cache.o
 
 %.bin.o: %.bin
 	$(BUILD_BINARY_O)
@@ -139,12 +139,24 @@ maple/maple_bus_commands.hpp: regs/maple_bus_commands.csv regs/gen/maple_bus_com
 maple/maple_bus_bits.hpp: regs/maple_bus_bits.csv regs/gen/core_bits.py
 	python regs/gen/core_bits.py $< > $@
 
+holly/core_bits.hpp: regs/core_bits.csv regs/gen/core_bits.py
+	python regs/gen/core_bits.py $< > $@
+
+holly/holly.hpp: regs/holly.csv regs/gen/holly.py
+	python regs/gen/holly.py $< > $@
+
 holly/ta_global_parameter.hpp: regs/global_parameter_format.csv regs/gen/ta_parameter_format.py
 	python regs/gen/ta_parameter_format.py $< ta_global_parameter > $@
 
 holly/ta_vertex_parameter.hpp: regs/vertex_parameter_format.csv regs/gen/ta_parameter_format.py
 	python regs/gen/ta_parameter_format.py $< ta_vertex_parameter > $@
 
+sh7091/sh7091.hpp: regs/sh7091.csv regs/gen/sh7091.py
+	python regs/gen/sh7091.py $< > $@
+
+sh7091/sh7091_bits.hpp: regs/sh7091_bits.csv regs/gen/core_bits.py
+	python regs/gen/core_bits.py $< > $@
+
 clean:
 	find -P \
 		-regextype posix-egrep \
diff --git a/example/heart.cpp b/example/heart.cpp
index 22c33e5..97a55af 100644
--- a/example/heart.cpp
+++ b/example/heart.cpp
@@ -4,7 +4,7 @@
 #include "vga.hpp"
 
 #include "holly/texture_memory_alloc.hpp"
-#include "holly.hpp"
+#include "holly/holly.hpp"
 #include "holly/core.hpp"
 #include "holly/core_bits.hpp"
 #include "holly/ta_fifo_polygon_converter.hpp"
diff --git a/example/serial_transfer.cpp b/example/serial_transfer.cpp
index 760d74d..1c9b375 100644
--- a/example/serial_transfer.cpp
+++ b/example/serial_transfer.cpp
@@ -1,9 +1,9 @@
 #include <cstdint>
 
-#include "sh7091.hpp"
-#include "sh7091_bits.hpp"
+#include "sh7091/sh7091.hpp"
+#include "sh7091/sh7091_bits.hpp"
+#include "sh7091/cache.hpp"
 
-#include "cache.hpp"
 #include "serial_load.hpp"
 
 extern uint32_t __bss_link_start __asm("__bss_link_start");
@@ -22,13 +22,15 @@ void main()
   load_init();
 
   while (1) {
-    while ((sh7091.SCIF.SCFSR2 & SCFSR2__TDFE) == 0) {
+    using namespace scif;
+
+    while ((sh7091.SCIF.SCFSR2 & scfsr2::tdfe::bit_mask) == 0) {
       // wait
     }
-    while ((sh7091.SCIF.SCFDR2 & 0b11111) > 0) {
+    while ((scfdr2::receive_data_bytes(sh7091.SCIF.SCFDR2)) > 0) {
       uint8_t c = sh7091.SCIF.SCFRDR2;
       load_recv(c);
     }
-    sh7091.SCIF.SCFSR2 = sh7091.SCIF.SCFSR2 & (~SCFSR2__RDF);
+    sh7091.SCIF.SCFSR2 = sh7091.SCIF.SCFSR2 & (~scfsr2::rdf::bit_mask);
   }
 }
diff --git a/holly/core.cpp b/holly/core.cpp
index 061f914..0ea30c0 100644
--- a/holly/core.cpp
+++ b/holly/core.cpp
@@ -1,13 +1,12 @@
-#include "../float_uint32.hpp"
-#include "core_bits.hpp"
-#include "../holly.hpp"
-#include "../memorymap.hpp"
-#include "../systembus.hpp"
-#include "../systembus_bits.hpp"
+#include "float_uint32.hpp"
+#include "memorymap.hpp"
+#include "systembus.hpp"
+#include "systembus_bits.hpp"
 
 #include "texture_memory_alloc.hpp"
-
+#include "holly.hpp"
 #include "core.hpp"
+#include "core_bits.hpp"
 #include "background.hpp"
 #include "region_array.hpp"
 
diff --git a/holly/core_bits.hpp b/holly/core_bits.hpp
index 81bf1a6..fd22958 100644
--- a/holly/core_bits.hpp
+++ b/holly/core_bits.hpp
@@ -53,24 +53,24 @@ namespace fb_r_ctrl {
   namespace vclk_div {
     constexpr uint32_t pclk_vclk_2 = 0 << 23;
     constexpr uint32_t pclk_vclk_1 = 1 << 23;
-    
+
     constexpr uint32_t bit_mask = 0x1 << 23;
   }
-  
+
   constexpr uint32_t fb_strip_buf_en = 1 << 22;
   constexpr uint32_t fb_stripsize(uint32_t num) { return (num & 0x3e) << 16; }
   constexpr uint32_t fb_chroma_threshold(uint32_t num) { return (num & 0xff) << 8; }
   constexpr uint32_t fb_concat(uint32_t num) { return (num & 0x3) << 4; }
-  
+
   namespace fb_depth {
     constexpr uint32_t _0555_rgb_16bit = 0 << 2;
     constexpr uint32_t _0565_rgb_16bit = 1 << 2;
     constexpr uint32_t _888_rgb_24bit_packed = 2 << 2;
     constexpr uint32_t _0888_rgb_32bit = 3 << 2;
-    
+
     constexpr uint32_t bit_mask = 0x3 << 2;
   }
-  
+
   constexpr uint32_t fb_line_double = 1 << 1;
   constexpr uint32_t fb_enable = 1 << 0;
 }
@@ -79,7 +79,7 @@ namespace fb_w_ctrl {
   constexpr uint32_t fb_alpha_threshold(uint32_t num) { return (num & 0xff) << 16; }
   constexpr uint32_t fb_kval(uint32_t num) { return (num & 0xff) << 8; }
   constexpr uint32_t fb_dither = 1 << 3;
-  
+
   namespace fb_packmode {
     constexpr uint32_t _0555_krgb_16bit = 0 << 0;
     constexpr uint32_t _565_rgb_16bit = 1 << 0;
@@ -88,7 +88,7 @@ namespace fb_w_ctrl {
     constexpr uint32_t _888_rgb_24bit_packed = 4 << 0;
     constexpr uint32_t _0888_krgb_32bit = 5 << 0;
     constexpr uint32_t _8888_argb_32bit = 6 << 0;
-    
+
     constexpr uint32_t bit_mask = 0x7 << 0;
   }
 }
@@ -133,10 +133,10 @@ namespace fpu_shad_scale {
   namespace simple_shadow_enable {
     constexpr uint32_t parameter_selection_volume_mode = 0 << 8;
     constexpr uint32_t intensity_volume_mode = 1 << 8;
-    
+
     constexpr uint32_t bit_mask = 0x1 << 8;
   }
-  
+
   constexpr uint32_t scale_factor_for_shadows(uint32_t num) { return (num & 0xff) << 0; }
 }
 
@@ -148,10 +148,10 @@ namespace fpu_param_cfg {
   namespace region_header_type {
     constexpr uint32_t type_1 = 0 << 21;
     constexpr uint32_t type_2 = 1 << 21;
-    
+
     constexpr uint32_t bit_mask = 0x1 << 21;
   }
-  
+
   constexpr uint32_t tsp_parameter_burst_threshold(uint32_t num) { return (num & 0x3f) << 14; }
   constexpr uint32_t isp_parameter_burst_threshold(uint32_t num) { return (num & 0x3f) << 8; }
   constexpr uint32_t pointer_burst_size(uint32_t num) { return (num & 0xf) << 4; }
@@ -162,21 +162,21 @@ namespace half_offset {
   namespace tsp_texel_sampling_position {
     constexpr uint32_t top_left = 1 << 2;
     constexpr uint32_t center = 1 << 2;
-    
+
     constexpr uint32_t bit_mask = 0x1 << 2;
   }
-  
+
   namespace tsp_pixel_sampling_position {
     constexpr uint32_t top_left = 1 << 1;
     constexpr uint32_t center = 1 << 1;
-    
+
     constexpr uint32_t bit_mask = 0x1 << 1;
   }
-  
+
   namespace fpu_pixel_sampling_position {
     constexpr uint32_t top_left = 1 << 0;
     constexpr uint32_t center = 1 << 0;
-    
+
     constexpr uint32_t bit_mask = 0x1 << 0;
   }
 }
@@ -222,18 +222,18 @@ namespace sdram_arb_cfg {
     constexpr uint32_t isp_pointer_data = 0x9 << 18;
     constexpr uint32_t isp_parameters = 0xa << 18;
     constexpr uint32_t crt_controller = 0xb << 18;
-    
+
     constexpr uint32_t bit_mask = 0xf << 18;
   }
-  
+
   namespace arbiter_priority_control {
     constexpr uint32_t priority_arbitration_only = 0x0 << 16;
     constexpr uint32_t override_value_field = 0x1 << 16;
     constexpr uint32_t round_robin_counter = 0x2 << 16;
-    
+
     constexpr uint32_t bit_mask = 0x3 << 16;
   }
-  
+
   constexpr uint32_t arbiter_crt_page_break_latency_count_value(uint32_t num) { return (num & 0xff) << 8; }
   constexpr uint32_t arbiter_page_break_latency_count_value(uint32_t num) { return (num & 0xff) << 0; }
 }
@@ -289,15 +289,15 @@ namespace spg_trigger_pos {
 
 namespace spg_hblank_int {
   constexpr uint32_t hblank_in_interrupt(uint32_t reg) { return (reg >> 16) & 0x3ff; }
-  
+
   namespace hblank_int_mode {
     constexpr uint32_t output_equal_line_comp_val = 0x0 << 12;
     constexpr uint32_t output_every_line_comp_val = 0x1 << 12;
     constexpr uint32_t output_every_line = 0x2 << 12;
-    
+
     constexpr uint32_t bit_mask = 0x3 << 12;
   }
-  
+
   constexpr uint32_t line_comp_val(uint32_t num) { return (num & 0x3ff) << 0; }
 }
 
@@ -310,41 +310,41 @@ namespace spg_control {
   namespace csync_on_h {
     constexpr uint32_t hsync = 0 << 9;
     constexpr uint32_t csync = 1 << 9;
-    
+
     constexpr uint32_t bit_mask = 0x1 << 9;
   }
-  
+
   namespace sync_direction {
     constexpr uint32_t input = 0 << 8;
     constexpr uint32_t output = 1 << 8;
-    
+
     constexpr uint32_t bit_mask = 0x1 << 8;
   }
-  
+
   constexpr uint32_t pal = 1 << 7;
   constexpr uint32_t ntsc = 1 << 6;
   constexpr uint32_t force_field2 = 1 << 5;
   constexpr uint32_t interlace = 1 << 4;
   constexpr uint32_t spg_lock = 1 << 3;
-  
+
   namespace mcsync_pol {
     constexpr uint32_t active_low = 0 << 2;
     constexpr uint32_t active_high = 1 << 2;
-    
+
     constexpr uint32_t bit_mask = 0x1 << 2;
   }
-  
+
   namespace mvsync_pol {
     constexpr uint32_t active_low = 0 << 1;
     constexpr uint32_t active_high = 1 << 1;
-    
+
     constexpr uint32_t bit_mask = 0x1 << 1;
   }
-  
+
   namespace mhsync_pol {
     constexpr uint32_t active_low = 0 << 0;
     constexpr uint32_t active_high = 1 << 0;
-    
+
     constexpr uint32_t bit_mask = 0x1 << 0;
   }
 }
@@ -375,17 +375,17 @@ namespace text_control {
   namespace code_book_endian {
     constexpr uint32_t little_endian = 0 << 17;
     constexpr uint32_t big_endian = 1 << 17;
-    
+
     constexpr uint32_t bit_mask = 0x1 << 17;
   }
-  
+
   namespace index_endian {
     constexpr uint32_t little_endian = 0 << 16;
     constexpr uint32_t big_endian = 1 << 16;
-    
+
     constexpr uint32_t bit_mask = 0x1 << 16;
   }
-  
+
   constexpr uint32_t bank_bit(uint32_t num) { return (num & 0x1f) << 8; }
   constexpr uint32_t stride(uint32_t num) { return (num & 0x1f) << 0; }
 }
@@ -394,7 +394,7 @@ namespace vo_control {
   constexpr uint32_t pclk_delay_reset = 1 << 21;
   constexpr uint32_t pclk_delay(uint32_t num) { return (num & 0xf) << 16; }
   constexpr uint32_t pixel_double = 1 << 8;
-  
+
   namespace field_mode {
     constexpr uint32_t use_field_flag_from_spg = 0x0 << 4;
     constexpr uint32_t use_inverse_of_field_flag_from_spg = 0x1 << 4;
@@ -405,30 +405,30 @@ namespace vo_control {
     constexpr uint32_t field_1_when_hsync_becomes_active_in_the_middle_of_the_vsync_active_edge = 0x6 << 4;
     constexpr uint32_t field_2_when_hsync_becomes_active_in_the_middle_of_the_vsync_active_edge = 0x7 << 4;
     constexpr uint32_t inverted_at_the_active_edge_of_vsync = 0x8 << 4;
-    
+
     constexpr uint32_t bit_mask = 0xf << 4;
   }
-  
+
   constexpr uint32_t blank_video = 1 << 3;
-  
+
   namespace blank_pol {
     constexpr uint32_t active_low = 0 << 2;
     constexpr uint32_t active_high = 1 << 2;
-    
+
     constexpr uint32_t bit_mask = 0x1 << 2;
   }
-  
+
   namespace vsync_pol {
     constexpr uint32_t active_low = 0 << 1;
     constexpr uint32_t active_high = 1 << 1;
-    
+
     constexpr uint32_t bit_mask = 0x1 << 1;
   }
-  
+
   namespace hsync_pol {
     constexpr uint32_t active_low = 0 << 0;
     constexpr uint32_t active_high = 1 << 0;
-    
+
     constexpr uint32_t bit_mask = 0x1 << 0;
   }
 }
@@ -446,10 +446,10 @@ namespace scaler_ctl {
   namespace field_select {
     constexpr uint32_t field_1 = 0 << 18;
     constexpr uint32_t field_2 = 1 << 18;
-    
+
     constexpr uint32_t bit_mask = 0x1 << 18;
   }
-  
+
   constexpr uint32_t interlace = 1 << 17;
   constexpr uint32_t horizontal_scaling_enable = 1 << 16;
   constexpr uint32_t vertical_scale_factor(uint32_t num) { return (num & 0xffff) << 0; }
@@ -461,7 +461,7 @@ namespace pal_ram_ctrl {
     constexpr uint32_t rgb565 = 1 << 0;
     constexpr uint32_t argb4444 = 2 << 0;
     constexpr uint32_t argb8888 = 3 << 0;
-    
+
     constexpr uint32_t bit_mask = 0x3 << 0;
   }
 }
diff --git a/holly.hpp b/holly/holly.hpp
similarity index 100%
rename from holly.hpp
rename to holly/holly.hpp
diff --git a/holly/ta_fifo_polygon_converter.cpp b/holly/ta_fifo_polygon_converter.cpp
index feab290..eb68ca0 100644
--- a/holly/ta_fifo_polygon_converter.cpp
+++ b/holly/ta_fifo_polygon_converter.cpp
@@ -1,13 +1,13 @@
 #include <cstdint>
 
+#include "systembus.hpp"
+#include "systembus_bits.hpp"
+#include "sh7091/sh7091.hpp"
+#include "sh7091/sh7091_bits.hpp"
+
 #include "core_bits.hpp"
 #include "ta_bits.hpp"
-#include "../holly.hpp"
-#include "../systembus.hpp"
-#include "../systembus_bits.hpp"
-#include "../sh7091.hpp"
-#include "../sh7091_bits.hpp"
-
+#include "holly.hpp"
 #include "texture_memory_alloc.hpp"
 
 #include "ta_fifo_polygon_converter.hpp"
@@ -79,23 +79,25 @@ void ta_polygon_converter_transfer(volatile uint32_t * buf, uint32_t size)
   volatile uint32_t _dummy = sh7091.DMAC.CHCR2;
   (void)_dummy;
 
+  using namespace dmac;
+
   /* start a new CH2-DMA transfer from "system memory" to "TA FIFO polygon converter" */
   sh7091.DMAC.CHCR2 = 0; /* disable DMA channel */
-  sh7091.DMAC.SAR2 = reinterpret_cast<uint32_t>(&buf[0]); /* start address, must be aligned to a CHCHR__TS-sized (32-byte) boundary */
-  sh7091.DMAC.DMATCR2 = DMATCR2__TRANSFER_COUNT(size / 32); /* transfer count, in CHCHR__TS-sized (32-byte) units */
-  sh7091.DMAC.CHCR2 = CHCR2__DM__DESTINATION_ADDRESS_FIXED
-                    | CHCR2__SM__SOURCE_ADDRESS_INCREMENTED
-		    | CHCR2__RS(0b0010) /* external request, single address mode;
-					   external address space → external device */
-                    | CHCR2__TM__BURST_MODE /* transmit mode */
-                    | CHCR2__TS__32_BYTE    /* transfer size */
-                    | CHCR2__DE;            /* DMAC (channel) enable */
+  sh7091.DMAC.SAR2 = reinterpret_cast<uint32_t>(&buf[0]);  /* start address, must be aligned to a CHCHR__TS-sized (32-byte) boundary */
+  sh7091.DMAC.DMATCR2 = dmatcr::transfer_count(size / 32); /* transfer count, in CHCHR__TS-sized (32-byte) units */
+  sh7091.DMAC.CHCR2 = chcr::dm::destination_address_fixed
+                    | chcr::sm::source_address_incremented
+                    | chcr::rs::resource_select(0b0010) /* external request, single address mode;
+					                   external address space → external device */
+                    | chcr::tm::cycle_burst_mode /* transmit mode */
+                    | chcr::ts::_32_byte         /* transfer size */
+                    | chcr::de::channel_operation_enabled;
 
-  sh7091.DMAC.DMAOR = DMAOR__DDT                 /* on-demand data transfer mode */
-                    | DMAOR__PR__CH2_CH0_CH1_CH3 /* priority mode; CH2 > CH0 > CH1 > CH3 */
-                    | DMAOR__DME;                /* DMAC master enable */
+  sh7091.DMAC.DMAOR = dmaor::ddt::on_demand_data_transfer_mode       /* on-demand data transfer mode */
+                    | dmaor::pr::ch2_ch0_ch1_ch3                     /* priority mode; CH2 > CH0 > CH1 > CH3 */
+                    | dmaor::dme::operation_enabled_on_all_channels; /* DMAC master enable */
   system.C2DSTAT = C2DSTAT__ADDRESS(0x10000000); /* CH2-DMA destination address */
-  system.C2DLEN  = CD2LEN__LENGTH(size) ; /* CH2-DMA length (must be a multiple of 32) */
+  system.C2DLEN  = CD2LEN__LENGTH(size);         /* CH2-DMA length (must be a multiple of 32) */
   system.C2DST   = 1;          /* CH2-DMA start (an 'external' request from SH7091's perspective) */
 
   // wait for CH2-DMA completion
diff --git a/regs/gen/core_bits.py b/regs/gen/core_bits.py
index f47db48..f48e345 100644
--- a/regs/gen/core_bits.py
+++ b/regs/gen/core_bits.py
@@ -18,11 +18,19 @@ def parse_bit_number(s):
     assert '-' not in s
     return int(s, 10)
 
+def parse_bit_set(s, split_char):
+    assert len(list(c for c in s if c == split_char)) == 1
+    left, right = map(parse_bit_number, s.split(split_char, maxsplit=1))
+    assert left > right, (left, right)
+    return left, right
+
 def parse_bit_range(s):
     if '-' in s:
-        left, right = map(parse_bit_number, s.split('-', maxsplit=1))
-        assert left > right, (left, right)
+        left, right = parse_bit_set(s, '-')
         return set(range(right, left+1))
+    elif ',' in s:
+        left, right = parse_bit_set(s, ',')
+        return set([right, left])
     else:
         num = parse_bit_number(s)
         return set([num])
@@ -41,7 +49,7 @@ def aggregate_enums(aggregated_rows):
 
     for row in aggregated_rows:
         bits = parse_bit_range(row["bits"])
-        assert row["bit_name"] != ""
+        assert row["bit_name"] != "", row
         if row["enum_name"] == "":
             assert_unique_ordered(bits)
             non_enum.append(row)
@@ -50,7 +58,7 @@ def aggregate_enums(aggregated_rows):
                 assert_unique_ordered(bits)
                 non_enum.append(row["enum_name"])
             else:
-                assert enum_bits[row["enum_name"]] == bits
+                assert enum_bits[row["enum_name"]] == bits, row
 
             enum_bits[row["enum_name"]] = bits
             enum_aggregated[row["enum_name"]].append(row)
@@ -64,6 +72,7 @@ class enum:
 
 @dataclass
 class register:
+    block: Union[None, str]
     name: str
     defs: list[Union[dict, enum]]
 
@@ -79,9 +88,17 @@ def aggregate_all_enums(aggregated):
                 return row_or_string
             else:
                 assert False, (row_or_string, type(row_or_string))
-        out.append(
-            register(register_name,
-                     [resolve(aggregate) for aggregate in non_enum]))
+
+        defs = [resolve(aggregate) for aggregate in non_enum]
+        if 'block' in rows[0]:
+            blocks = set(row['block'] for row in rows)
+            assert len(blocks) == 1, blocks
+            block_name = next(iter(blocks))
+            out.append(
+                register(block_name, register_name, defs))
+        else:
+            out.append(
+                register(None, register_name, defs))
     return out
 
 '''
@@ -107,19 +124,26 @@ def aggregate_all_enums(aggregated):
 '''
 
 def mask_from_bits(bits):
-    mask = 2 ** len(bits) - 1
+    h, l = max(bits), min(bits)
+    mask = 2 ** ((h - l) + 1) - 1
     return mask
 
 def parse_value(value):
     return eval(value)
 
+def escape(bit_name):
+    if bit_name[0] in {'0', '1', '2', '3', '4', '5', '6', '7', '8', '9'}:
+        return '_' + bit_name
+    else:
+        return bit_name
+
 def render_read_only(bit_def):
     assert bit_def["value"] == ""
     assert bit_def["mask"] == ""
     bits = parse_bit_range(bit_def["bits"])
     mask_value = mask_from_bits(bits)
     yield (
-        f"constexpr uint32_t {bit_def['bit_name']}(uint32_t reg) {{ "
+        f"constexpr uint32_t {escape(bit_def['bit_name'])}(uint32_t reg) {{ "
         f"return (reg >> {min(bits)}) & {hex(mask_value)};"
         " }"
     )
@@ -145,7 +169,7 @@ def render_mask(bit_def):
     bits = parse_bit_range(bit_def["bits"])
     if mask.startswith("float_"):
         yield (
-            f"constexpr uint32_t {bit_def['bit_name']}(float num) {{ "
+            f"inline uint32_t {escape(bit_def['bit_name'])}(float num) {{ "
             f"return {render_float_mask(mask)};"
             " }"
         )
@@ -155,7 +179,7 @@ def render_mask(bit_def):
         assert mask_value & mask_from_bits(bits) == mask_value, (mask_value, mask_from_bits(bits))
 
         yield (
-            f"constexpr uint32_t {bit_def['bit_name']}(uint32_t num) {{ "
+            f"constexpr uint32_t {escape(bit_def['bit_name'])}(uint32_t num) {{ "
             f"return (num & {hex(mask_value)}) << {min(bits)};"
             " }"
         )
@@ -163,9 +187,9 @@ def render_mask(bit_def):
 def render_value(bit_def):
     assert bit_def["mask"] == ""
     bits = parse_bit_range(bit_def["bits"])
-    assert parse_value(bit_def["value"]) <= mask_from_bits(bits), bit_def["value"]
+    assert parse_value(bit_def["value"]) <= mask_from_bits(bits), (bit_def["value"], mask_from_bits(bits), bits)
     bit_ix = min(bits)
-    yield f"constexpr uint32_t {bit_def['bit_name']} = {bit_def['value']} << {bit_ix};"
+    yield f"constexpr uint32_t {escape(bit_def['bit_name'])} = {bit_def['value']} << {bit_ix};"
 
 def render_defs(bit_def):
     if bit_def["value"] != "":
@@ -212,9 +236,23 @@ def render_register(register):
     yield ""
 
 def render_registers(registers):
+    last_block = None
     for register in registers:
+        if register.block != last_block:
+            assert register.block is not None
+            if last_block is not None:
+                yield '}' # end of previous namespace
+                yield ""
+            yield f'namespace {register.block.lower()} {{'
+        if register.block is None:
+            assert last_block is None
+        last_block = register.block
+
         yield from render_register(register)
 
+    if last_block is not None:
+        yield '}' # end of block namespace
+
 def header():
     yield "#pragma once"
     yield ""
diff --git a/regs/gen/sh7091.py b/regs/gen/sh7091.py
index a3cf7c0..6949b39 100644
--- a/regs/gen/sh7091.py
+++ b/regs/gen/sh7091.py
@@ -45,13 +45,12 @@ def new_writer():
 
     def terminate():
         nonlocal last_block
-        nonlocal first_address
         nonlocal stack
 
         if last_block is not None:
             yield "};"
             for address, name in stack:
-                yield f"static_assert((offsetof (struct {last_block.lower()}_reg, {name})) == {hex(address)});"
+                yield f"static_assert((offsetof (struct {last_block.lower()}_reg, {name})) == {hex(address - first_address)});"
             yield ""
         stack = []
 
@@ -68,15 +67,16 @@ def new_writer():
         _address = int(row["address"], 16)
         assert _offset  <= 0xff
         assert _address <= 0xffff
-        address = (_offset << 16) | (_address << 0)
+        offset_address = (_offset << 16)
+        address = offset_address | (_address << 0)
         size = int(row["size"], 10)
         name = row["name"]
         description = row["description"]
 
         if block != last_block:
             yield from terminate()
-            first_address = 0 # hmm...
-            last_address = 0
+            first_address = offset_address
+            last_address = offset_address
             size_total = 0
             reserved_num = 0
             yield f"struct {block.lower()}_reg {{"
diff --git a/regs/sh7091_bits.csv b/regs/sh7091_bits.csv
new file mode 100644
index 0000000..f165e1c
--- /dev/null
+++ b/regs/sh7091_bits.csv
@@ -0,0 +1,293 @@
+"block","register_name","enum_name","bits","bit_name","value","mask","description"
+"CCN","PTEH",,"31-10","VPN",,,"Virtual Page Number"
+"CCN","PTEH",,"7-0","ASID",,,"Address space identifier"
+,,,,,,,
+"CCN","PTEL",,"28-10","PPN",,,"Physical page number"
+"CCN","PTEL","V","8","invalid","0",,"Validity"
+"CCN","PTEL","V","8","valid","1",,"Validity"
+"CCN","PTEL","SZ","7,4","1_kbyte_page","0b0000",,"Page size"
+"CCN","PTEL","SZ","7,4","4_kbyte_page","0b0001",,"Page size"
+"CCN","PTEL","SZ","7,4","64_kbyte_page","0b1000",,"Page size"
+"CCN","PTEL","SZ","7,4","1_mbyte_page","0b1001",,"Page size"
+"CCN","PTEL","PR","6-5","read_only_in_privileged_mode","0b00",,"Protection key data"
+"CCN","PTEL","PR","6-5","read_write_in_privileged_mode","0b01",,"Protection key data"
+"CCN","PTEL","PR","6-5","read_only_in_privileged_and_user_mode","0b10",,"Protection key data"
+"CCN","PTEL","PR","6-5","read_write_in_privileged_and_user_mode","0b11",,"Protection key data"
+"CCN","PTEL","C","3","not_cacheable","0",,"Cacheability bit"
+"CCN","PTEL","C","3","cacheable","1",,"Cacheability bit"
+"CCN","PTEL","D","2","write_has_not_been_performed","0",,"Dirty bit"
+"CCN","PTEL","D","2","write_has_been_performed","1",,"Dirty bit"
+"CCN","PTEL","SH","1","pages_are_shared_by_processes","0",,"Share status bit"
+"CCN","PTEL","SH","1","pages_are_not_shared_by_processes","1",,"Share status bit"
+"CCN","PTEL","WT","0","copy_back_mode","0",,"Write-through bit"
+"CCN","PTEL","WT","0","write_through_mode","1",,"Write-through bit"
+,,,,,,,
+"CCN","MMUCR",,"31-26","LRUI",,,"Least recently used ITLB"
+"CCN","MMUCR",,"23-18","URB",,,"UTLB replace boundary"
+"CCN","MMUCR",,"15-10","URC",,,"UTLB replace counter"
+"CCN","MMUCR","SQMD","9","user_privileged_access_possible","0",,"Store queue mode bit"
+"CCN","MMUCR","SQMD","9","privileged_access_possible","1",,"Store queue mode bit"
+"CCN","MMUCR","SV","8","multiple_virtual_memory_mode","0",,"Single virtual mode bit"
+"CCN","MMUCR","SV","8","single_virtual_memory_mode","1",,"Single virtual mode bit"
+"CCN","MMUCR","TI","2","invalidate_all_utlb_itlb_bits","1",,"TLB invalidate"
+"CCN","MMUCR","AT","0","mmu_disabled","0",,"Address translation bit"
+"CCN","MMUCR","AT","0","mmu_enabled","1",,"Address translation bit"
+,,,,,,,
+"CCN","BASRA",,"7-0","basa",,"0xff",
+,,,,,,,
+"CCN","BASRB",,"7-0","basa",,"0xff",
+,,,,,,,
+"CCN","CCR","IIX","15","address_bits_12_5_used_for_ic_entry_selection","0",,"IC index enable"
+"CCN","CCR","IIX","15","address_bits_25_and_11_5_used_for_ic_entry_selection","1",,"IC index enable"
+"CCN","CCR","ICI","11","clear_v_bits_of_all_ic_entries","1",,"IC invalidation"
+"CCN","CCR","ICE","8","ic_not_used","0",,"IC enable"
+"CCN","CCR","ICE","8","ic_used","1",,"IC enable"
+"CCN","CCR","OIX","7","address_bits_13_5_used_for_oc_entry_selection","0",,"OC index enable"
+"CCN","CCR","OIX","7","address_bits_25_and_12_5_used_for_oc_entry_selection","1",,"OC index enable"
+"CCN","CCR","ORA","5","16_kbytes_used_as_cache","0",,"OC RAM enable"
+"CCN","CCR","ORA","5","8_kbytes_used_as_cache_8_kbytes_used_as_ram","1",,"OC RAM enable"
+"CCN","CCR","OCI","3","clear_v_and_u_bits_of_all_oc_entries","1",,"OC invalidation"
+"CCN","CCR","CB","2","write_through_mode","0",,"Copy-back enable"
+"CCN","CCR","CB","2","copy_back_mode","1",,"Copy-back enable"
+"CCN","CCR","WT","1","copy_back_mode","0",,"Write-through enable"
+"CCN","CCR","WT","1","write_through_mode","1",,"Write-through enable"
+"CCN","CCR","OCE","0","oc_not_used","0",,"OC enable"
+"CCN","CCR","OCE","0","oc_used","1",,"OC enable"
+,,,,,,,
+"CCN","TRA",,"9-2","imm",,,
+,,,,,,,
+"CCN","EXPEVT",,"11-0","exception_code",,,
+,,,,,,,
+"CCN","INTEVT",,"11-0","exception_code",,,
+,,,,,,,
+"CCN","PTEA","TC","3","area_5_is_used","0",,"Timing control bit"
+"CCN","PTEA","TC","3","area_6_is_used","1",,"Timing control bit"
+"CCN","PTEA","SA","2-0","undefined","0b000",,"Space attribute bits"
+"CCN","PTEA","SA","2-0","variable_size_io_space","0b001",,"Space attribute bits"
+"CCN","PTEA","SA","2-0","8_bit_io_space","0b010",,"Space attribute bits"
+"CCN","PTEA","SA","2-0","16_bit_io_space","0b011",,"Space attribute bits"
+"CCN","PTEA","SA","2-0","8_bit_common_memory_space","0b100",,"Space attribute bits"
+"CCN","PTEA","SA","2-0","16_bit_common_memory_space","0b101",,"Space attribute bits"
+"CCN","PTEA","SA","2-0","8_bit_attribute_memory_space","0b110",,"Space attribute bits"
+"CCN","PTEA","SA","2-0","16_bit_attribute_memory_space","0b111",,"Space attribute bits"
+,,,,,,,
+"CCN","QACR0",,"4-2","area",,"0b111",
+,,,,,,,
+"CCN","QACR1",,"4-2","area",,"0b111",
+,,,,,,,
+"DMAC","DMATCR",,"23-0","transfer_count",,"0xffffff",
+,,,,,,,
+"DMAC","CHCR","SSA","31-29","reserved_in_pcmcia_access","0b000",,
+"DMAC","CHCR","SSA","31-29","dynamic_bus_sizing_io_space","0b001",,
+"DMAC","CHCR","SSA","31-29","8_bit_io_space","0b010",,
+"DMAC","CHCR","SSA","31-29","16_bit_io_space","0b011",,
+"DMAC","CHCR","SSA","31-29","8_bit_common_memory_space","0b100",,
+"DMAC","CHCR","SSA","31-29","16_bit_common_memory_space","0b101",,
+"DMAC","CHCR","SSA","31-29","8_bit_attribute_memory_space","0b110",,
+"DMAC","CHCR","SSA","31-29","16_bit_attribute_memory_space","0b111",,
+"DMAC","CHCR","STC","28","c5_space_wait_cycle_selection","0",,
+"DMAC","CHCR","STC","28","c6_space_wait_cycle_selection","1",,
+"DMAC","CHCR","DSA","27-25","reserved_in_pcmcia_access","0b000",,
+"DMAC","CHCR","DSA","27-25","dynamic_bus_sizing_io_space","0b001",,
+"DMAC","CHCR","DSA","27-25","8_bit_io_space","0b010",,
+"DMAC","CHCR","DSA","27-25","16_bit_io_space","0b011",,
+"DMAC","CHCR","DSA","27-25","8_bit_common_memory_space","0b100",,
+"DMAC","CHCR","DSA","27-25","16_bit_common_memory_space","0b101",,
+"DMAC","CHCR","DSA","27-25","8_bit_attribute_memory_space","0b110",,
+"DMAC","CHCR","DSA","27-25","16_bit_attribute_memory_space","0b111",,
+"DMAC","CHCR","DTC","24","c5_space_wait_cycle_selection","0",,
+"DMAC","CHCR","DTC","24","c6_space_wait_cycle_selection","1",,
+"DMAC","CHCR","DS","19","low_level_detection","0",,
+"DMAC","CHCR","DS","19","falling_edge_detection","1",,
+"DMAC","CHCR","RL","18","drak_is_an_active_high","0",,
+"DMAC","CHCR","RL","18","drak_is_an_active_low","1",,
+"DMAC","CHCR","AM","17","dack_is_output_in_read_cycle","0",,
+"DMAC","CHCR","AM","17","dack_is_output_in_write_cycle","1",,
+"DMAC","CHCR","AL","16","active_high_output","0",,
+"DMAC","CHCR","AL","16","active_low_output","1",,
+"DMAC","CHCR","DM","15-14","destination_address_fixed","0b00",,
+"DMAC","CHCR","DM","15-14","destination_address_incremented","0b01",,
+"DMAC","CHCR","DM","15-14","destination_address_decremented","0b10",,
+"DMAC","CHCR","SM","13-12","source_address_fixed","0b00",,
+"DMAC","CHCR","SM","13-12","source_address_incremented","0b01",,
+"DMAC","CHCR","SM","13-12","source_address_decremented","0b10",,
+"DMAC","CHCR","RS","11-8","resource_select",,"0b1111",
+"DMAC","CHCR","TM","7","cycle_steal_mode","0",,
+"DMAC","CHCR","TM","7","cycle_burst_mode","1",,
+"DMAC","CHCR","TS","6-4","64_bit","0b000",,
+"DMAC","CHCR","TS","6-4","8_bit","0b001",,
+"DMAC","CHCR","TS","6-4","16_bit","0b010",,
+"DMAC","CHCR","TS","6-4","32_bit","0b011",,
+"DMAC","CHCR","TS","6-4","32_byte","0b100",,
+"DMAC","CHCR","IE","2","interrupt_request_not_generated","0",,
+"DMAC","CHCR","IE","2","interrupt_request_generated","1",,
+"DMAC","CHCR","TE","1","transfers_not_completed","0",,
+"DMAC","CHCR","TE","1","transfers_completed","1",,
+"DMAC","CHCR","DE","0","channel_operation_disabled","0",,
+"DMAC","CHCR","DE","0","channel_operation_enabled","1",,
+,,,,,,,
+"DMAC","DMAOR","DDT","15","normal_dma_mode","0",,
+"DMAC","DMAOR","DDT","15","on_demand_data_transfer_mode","1",,
+"DMAC","DMAOR","PR","9-8","ch0_ch1_ch2_ch3","0b00",,
+"DMAC","DMAOR","PR","9-8","ch0_ch2_ch3_ch1","0b01",,
+"DMAC","DMAOR","PR","9-8","ch2_ch0_ch1_ch3","0b10",,
+"DMAC","DMAOR","PR","9-8","round_robin","0b11",,
+"DMAC","DMAOR","AE","2","no_address_error__dma_transfer_enabled","0",,
+"DMAC","DMAOR","AE","2","address_error__dma_transfer_disabled","1",,
+"DMAC","DMAOR","NMIF","1","no_nmi__dma_transfer_enabled","0",,
+"DMAC","DMAOR","NMIF","1","nmi__dma_transfer_disabled","1",,
+"DMAC","DMAOR","DME","0","operation_disabled_on_all_channels","0",,
+"DMAC","DMAOR","DME","0","operation_enabled_on_all_channels","1",,
+,,,,,,,
+"INTC","ICR","NMIL","15","pin_input_level_is_low","0",,
+"INTC","ICR","NMIL","15","pin_input_level_is_high","1",,
+"INTC","ICR","MAI","14","interrupts_enabled_while_nmi_pin_is_low","0",,
+"INTC","ICR","MAI","14","interrupts_disabled_while_nmi_pin_is_low","1",,
+"INTC","ICR","NMIB","9","interrupt_requests_witheld","0",,
+"INTC","ICR","NMIB","9","interrupt_requests_detected","1",,
+"INTC","ICR","NMIE","8","interrupt_on_falling_edge_of_nmi","0",,
+"INTC","ICR","NMIE","8","interrupt_on_rising_edge_of_nmi","1",,
+"INTC","ICR","IRLM","7","level_encoded_interrupt_requests","0",,
+"INTC","ICR","IRLM","7","independent_interrupt_request","1",,
+,,,,,,,
+"INTC","IPRA",,"15-12","TMU0",,"0b1111",
+"INTC","IPRA",,"11-8","TMU1",,"0b1111",
+"INTC","IPRA",,"7-4","TMU2",,"0b1111",
+"INTC","IPRA",,"3-0","RTC",,"0b1111",
+,,,,,,,
+"INTC","IPRB",,"15-12","WDT",,"0b1111",
+"INTC","IPRB",,"11-8","REF",,"0b1111",
+"INTC","IPRB",,"7-4","SCI1",,"0b1111",
+,,,,,,,
+"INTC","IPRC",,"15-12","GPIO",,"0b1111",
+"INTC","IPRC",,"11-8","DMAC",,"0b1111",
+"INTC","IPRC",,"7-4","SCIF",,"0b1111",
+"INTC","IPRC",,"3-0","UDI",,"0b1111",
+,,,,,,,
+"TMU","TOCR","TCOE","0","tclk_is_external_clock_or_input_capture","0",,"Timer Clock Pin Control"
+"TMU","TOCR","TCOE","0","tclk_is_on_chip_rtc","1",,"Timer Clock Pin Control"
+,,,,,,,
+"TMU","TSTR","STR2","2","counter_start","1",,"Counter Start 2"
+"TMU","TSTR","STR1","1","counter_start","1",,"Counter Start 1"
+"TMU","TSTR","STR0","0","counter_start","1",,"Counter Start 0"
+,,,,,,,
+"TMU","TCR0",,"8","UNF","1",,"Underflow Flag"
+"TMU","TCR0",,"5","UNIE","1",,"Underflow Interrupt Control"
+"TMU","TCR0","CKEG","4-3","rising","0b00",,"Clock Edge"
+"TMU","TCR0","CKEG","4-3","falling","0b01",,"Clock Edge"
+"TMU","TCR0","CKEG","4-3","rising_falling","0b10",,"Clock Edge"
+"TMU","TCR0","TPSC","2-0","p_phi_4","0b000",,"Timer Prescaler"
+"TMU","TCR0","TPSC","2-0","p_phi_16","0b001",,"Timer Prescaler"
+"TMU","TCR0","TPSC","2-0","p_phi_64","0b010",,"Timer Prescaler"
+"TMU","TCR0","TPSC","2-0","p_phi_256","0b011",,"Timer Prescaler"
+"TMU","TCR0","TPSC","2-0","p_phi_1024","0b100",,"Timer Prescaler"
+"TMU","TCR0","TPSC","2-0","rtc_output","0b110",,"Timer Prescaler"
+"TMU","TCR0","TPSC","2-0","external","0b111",,"Timer Prescaler"
+,,,,,,,
+"TMU","TCR1",,"8","UNF","1",,"Underflow Flag"
+"TMU","TCR1",,"5","UNIE","1",,"Underflow Interrupt Control"
+"TMU","TCR1","CKEG","4-3","rising","0b00",,"Clock Edge"
+"TMU","TCR1","CKEG","4-3","falling","0b01",,"Clock Edge"
+"TMU","TCR1","CKEG","4-3","rising_falling","0b10",,"Clock Edge"
+"TMU","TCR1","TPSC","2-0","p_phi_4","0b000",,"Timer Prescaler"
+"TMU","TCR1","TPSC","2-0","p_phi_16","0b001",,"Timer Prescaler"
+"TMU","TCR1","TPSC","2-0","p_phi_64","0b010",,"Timer Prescaler"
+"TMU","TCR1","TPSC","2-0","p_phi_256","0b011",,"Timer Prescaler"
+"TMU","TCR1","TPSC","2-0","p_phi_1024","0b100",,"Timer Prescaler"
+"TMU","TCR1","TPSC","2-0","rtc_output","0b110",,"Timer Prescaler"
+"TMU","TCR1","TPSC","2-0","external","0b111",,"Timer Prescaler"
+,,,,,,,
+"TMU","TCR2",,"9","ICPF","1",,"Input Capture Interrupt Flag"
+"TMU","TCR2",,"8","UNF","1",,"Underflow Flag"
+"TMU","TCR2","ICPE","7-6","disabled","0b00",,"Input Capture Control"
+"TMU","TCR2","ICPE","7-6","enabled","0b10",,"Input Capture Control"
+"TMU","TCR2","ICPE","7-6","enabled_with_interrupts","0b11",,"Input Capture Control"
+"TMU","TCR2",,"5","UNIE","1",,"Underflow Interrupt Control"
+"TMU","TCR2","CKEG","4-3","rising","0b00",,"Clock Edge"
+"TMU","TCR2","CKEG","4-3","falling","0b01",,"Clock Edge"
+"TMU","TCR2","CKEG","4-3","rising_falling","0b10",,"Clock Edge"
+"TMU","TCR2","TPSC","2-0","p_phi_4","0b000",,"Timer Prescaler"
+"TMU","TCR2","TPSC","2-0","p_phi_16","0b001",,"Timer Prescaler"
+"TMU","TCR2","TPSC","2-0","p_phi_64","0b010",,"Timer Prescaler"
+"TMU","TCR2","TPSC","2-0","p_phi_256","0b011",,"Timer Prescaler"
+"TMU","TCR2","TPSC","2-0","p_phi_1024","0b100",,"Timer Prescaler"
+"TMU","TCR2","TPSC","2-0","rtc_output","0b110",,"Timer Prescaler"
+"TMU","TCR2","TPSC","2-0","external","0b111",,"Timer Prescaler"
+,,,,,,,
+"SCIF","SCSMR2","CHR","6","8_bit_data","0",,
+"SCIF","SCSMR2","CHR","6","7_bit_data","1",,
+"SCIF","SCSMR2","PE","5","parity_disabled","0",,
+"SCIF","SCSMR2","PE","5","parity_enabled","1",,
+"SCIF","SCSMR2","OE","4","even_parity","0",,
+"SCIF","SCSMR2","OE","4","odd_parity","1",,
+"SCIF","SCSMR2","STOP","3","1_stop_bit","0",,
+"SCIF","SCSMR2","STOP","3","2_stop_bits","1",,
+"SCIF","SCSMR2","CKS","1-0","p_phi_clock","0b00",,
+"SCIF","SCSMR2","CKS","1-0","p_phi_4_clock","0b01",,
+"SCIF","SCSMR2","CKS","1-0","p_phi_16_clock","0b10",,
+"SCIF","SCSMR2","CKS","1-0","p_phi_64_clock","0b11",,
+,,,,,,,
+"SCIF","SCSCR2","TIE","7","transmit_fifo_data_empty_interrupt_disabled","0",,
+"SCIF","SCSCR2","TIE","7","transmit_fifo_data_empty_interrupt_enabled","1",,
+"SCIF","SCSCR2","RIE","6","request_disabled","0",,
+"SCIF","SCSCR2","RIE","6","request_enabled","1",,
+"SCIF","SCSCR2","TE","5","transmission_disabled","0",,
+"SCIF","SCSCR2","TE","5","transmission_enabled","1",,
+"SCIF","SCSCR2","RE","4","reception_disabled","0",,
+"SCIF","SCSCR2","RE","4","reception_enabled","1",,
+"SCIF","SCSCR2","REIE","3","requests_disabled","0",,
+"SCIF","SCSCR2","REIE","3","requests_enabled","1",,
+"SCIF","SCSCR2","CKE1","1","sck2_pin_functions_as_input_pin","0",,
+"SCIF","SCSCR2","CKE1","1","sck2_pin_functions_as_clock_input","1",,
+,,,,,,,
+"SCIF","SCFSR2","PER3_0","15-12","number_of_parity_errors",,,
+"SCIF","SCFSR2","FER3_0","11-8","number_of_framing_errors",,,
+"SCIF","SCFSR2","ER","7","no_framing_error_or_parity_error","0",,
+"SCIF","SCFSR2","ER","7","framing_error_or_parity_error","1",,
+"SCIF","SCFSR2","TEND","6","transmission_in_progress","0",,
+"SCIF","SCFSR2","TEND","6","transmission_has_ended","1",,
+"SCIF","SCFSR2","TDFE","5","transmit_data_bytes_does_exceed_trigger","0",,
+"SCIF","SCFSR2","TDFE","5","transmit_data_bytes_does_not_exceed_trigger","1",,
+"SCIF","SCFSR2","BRK","4","break_not_received","0",,
+"SCIF","SCFSR2","BRK","4","break_received","1",,
+"SCIF","SCFSR2","FER","3","no_framing_error","0",,
+"SCIF","SCFSR2","FER","3","framing_error","1",,
+"SCIF","SCFSR2","PER","2","parity_error","0",,
+"SCIF","SCFSR2","PER","2","no_parity_error","1",,
+"SCIF","SCFSR2","RDF","1","receive_data_bytes_less_than_receive_trigger","0",,
+"SCIF","SCFSR2","RDF","1","receive_data_bytes_greater_than_or_equal_receive_trigger","1",,
+"SCIF","SCFSR2","DR","0","reception_is_in_progress","0",,
+"SCIF","SCFSR2","DR","0","no_further_data_has_arrived","1",,
+,,,,,,,
+"SCIF","SCFCR2","RTRG","7-6","trigger_on_1_byte","0b00",,
+"SCIF","SCFCR2","RTRG","7-6","trigger_on_4_bytes","0b01",,
+"SCIF","SCFCR2","RTRG","7-6","trigger_on_8_bytes","0b10",,
+"SCIF","SCFCR2","RTRG","7-6","trigger_on_14_byte","0b11",,
+"SCIF","SCFCR2","TTRG","5-4","trigger_on_8_bytes","0b00",,
+"SCIF","SCFCR2","TTRG","5-4","trigger_on_4_bytes","0b01",,
+"SCIF","SCFCR2","TTRG","5-4","trigger_on_2_bytes","0b10",,
+"SCIF","SCFCR2","TTRG","5-4","trigger_on_1_bytes","0b11",,
+"SCIF","SCFCR2","MCE","3","modem_signals_disabled","0",,
+"SCIF","SCFCR2","MCE","3","modem_signals_enabled","1",,
+"SCIF","SCFCR2","TFRST","2","reset_operation_disabled","0",,
+"SCIF","SCFCR2","TFRST","2","reset_operation_enabled","1",,
+"SCIF","SCFCR2","RFRST","1","reset_operation_disabled","0",,
+"SCIF","SCFCR2","RFRST","1","reset_operation_enabled","1",,
+"SCIF","SCFCR2","LOOP","0","loopback_test_disabled","0",,
+"SCIF","SCFCR2","LOOP","0","loopback_test_enabled","1",,
+,,,,,,,
+"SCIF","SCFDR2",,"12-8","transmit_data_bytes",,,
+"SCIF","SCFDR2",,"4-0","receive_data_bytes",,,
+,,,,,,,
+"SCIF","SCSPTR2","RTSIO","7","rtsdt_not_output_to_rts2","0",,
+"SCIF","SCSPTR2","RTSIO","7","rtsdt_output_to_rts2","1",,
+"SCIF","SCSPTR2","RTSDT","6","input_output_data_is_low_level","0",,
+"SCIF","SCSPTR2","RTSDT","6","input_output_data_is_high_level","1",,
+"SCIF","SCSPTR2","CTSIO","5","ctsdt_is_not_output_to_cts2","0",,
+"SCIF","SCSPTR2","CTSIO","5","ctsdt_is_output_to_cts2","1",,
+"SCIF","SCSPTR2","CTSDT","4","input_output_data_is_low_level","0",,
+"SCIF","SCSPTR2","CTSDT","4","input_output_data_is_high_level","1",,
+"SCIF","SCSPTR2","SPB2IO","1","spb2dt_is_not_output_to_txd2","0",,
+"SCIF","SCSPTR2","SPB2IO","1","spb2dt_is_output_to_txd2","1",,
+"SCIF","SCSPTR2","SPB2DT","0","input_output_data_is_low_level","0",,
+"SCIF","SCSPTR2","SPB2DT","0","input_output_data_is_high_level","1",,
diff --git a/regs/sh7091_bits.ods b/regs/sh7091_bits.ods
new file mode 100644
index 0000000..747ad83
Binary files /dev/null and b/regs/sh7091_bits.ods differ
diff --git a/runtime.cpp b/runtime.cpp
index bdd69a5..6460fe8 100644
--- a/runtime.cpp
+++ b/runtime.cpp
@@ -1,6 +1,6 @@
 #include <cstdint>
 
-#include "cache.hpp"
+#include "sh7091/cache.hpp"
 
 extern uint32_t __bss_link_start __asm("__bss_link_start");
 extern uint32_t __bss_link_end __asm("__bss_link_end");
diff --git a/serial_load.cpp b/serial_load.cpp
index 9e12807..31bda3c 100644
--- a/serial_load.cpp
+++ b/serial_load.cpp
@@ -1,8 +1,8 @@
 #include <cstdint>
 
-#include "sh7091.hpp"
-#include "sh7091_bits.hpp"
-#include "holly.hpp"
+#include "sh7091/sh7091.hpp"
+#include "sh7091/sh7091_bits.hpp"
+#include "holly/holly.hpp"
 
 enum load_command {
   CMD_NONE,
@@ -48,7 +48,8 @@ void debug(const char * s)
 {
   char c;
   while ((c = *s++)) {
-    while ((sh7091.SCIF.SCFSR2 & SCFSR2__TDFE) == 0);
+    using namespace scif;
+    while ((sh7091.SCIF.SCFSR2 & scfsr2::tdfe::bit_mask) == 0);
     sh7091.SCIF.SCFTDR2 = (uint8_t)c;
   }
 }
diff --git a/sh7091/cache.cpp b/sh7091/cache.cpp
new file mode 100644
index 0000000..f223b83
--- /dev/null
+++ b/sh7091/cache.cpp
@@ -0,0 +1,36 @@
+#include "type.hpp"
+#include "sh7091.hpp"
+#include "sh7091_bits.hpp"
+
+#include "cache.hpp"
+
+extern volatile reg32 sh7091_ic_a[256][(1 << 5) / 4] __asm("sh7091_ic_a");
+extern volatile reg32 sh7091_oc_a[512][(1 << 5) / 4] __asm("sh7091_oc_a");
+
+namespace cache {
+
+void init()
+{
+  for (int i = 0; i < 256; i++) {
+    sh7091_ic_a[i][0] = 0;
+  }
+
+  for (int i = 0; i < 512; i++) {
+    sh7091_oc_a[i][0] = 0;
+  }
+
+  using namespace ccn::ccr;
+
+  sh7091.CCN.CCR = ici::clear_v_bits_of_all_ic_entries       // instruction cache invalidate
+                 | ice::ic_used                              // instruction cache enable
+                 | oci::clear_v_and_u_bits_of_all_oc_entries // operand cache invalidate
+                 | oce::oc_used                              // operand cache enable
+              // | cb::copy_back_mode                        // enable copy-back mode for the P1 area
+                 ;
+
+  sh7091.CCN.MMUCR = ccn::mmucr::at::mmu_disabled;
+
+  asm volatile ("nop;nop;nop;nop;nop;nop;nop;nop;");
+}
+
+}
diff --git a/cache.hpp b/sh7091/cache.hpp
similarity index 100%
rename from cache.hpp
rename to sh7091/cache.hpp
diff --git a/imask.hpp b/sh7091/imask.hpp
similarity index 100%
rename from imask.hpp
rename to sh7091/imask.hpp
diff --git a/serial.cpp b/sh7091/serial.cpp
similarity index 100%
rename from serial.cpp
rename to sh7091/serial.cpp
diff --git a/serial.hpp b/sh7091/serial.hpp
similarity index 100%
rename from serial.hpp
rename to sh7091/serial.hpp
diff --git a/sh7091.hpp b/sh7091/sh7091.hpp
similarity index 99%
rename from sh7091.hpp
rename to sh7091/sh7091.hpp
index 0eb68ba..6119f15 100644
--- a/sh7091.hpp
+++ b/sh7091/sh7091.hpp
@@ -90,9 +90,9 @@ struct bsc_reg {
   reg8  _pad7[2];
   reg16 GPIOIC;            /* GPIO interrupt control register */
   reg8  _pad8[1048502];
-  reg8  SDMR2[65536];      /* Synchronous DRAM mode registers */
+  reg32 SDMR2[16384];      /* Synchronous DRAM mode registers */
   reg8  _pad9[196608];
-  reg8  SDMR3[65536];      /* Synchronous DRAM mode registers */
+  reg32 SDMR3[16384];      /* Synchronous DRAM mode registers */
 };
 
 static_assert((offsetof (struct bsc_reg, BCR1)) == 0x0);
diff --git a/sh7091/sh7091_bits.hpp b/sh7091/sh7091_bits.hpp
new file mode 100644
index 0000000..13ff73e
--- /dev/null
+++ b/sh7091/sh7091_bits.hpp
@@ -0,0 +1,822 @@
+#pragma once
+
+#include <cstdint>
+
+#include "../float_uint32.hpp"
+
+namespace ccn {
+  namespace pteh {
+    constexpr uint32_t VPN(uint32_t reg) { return (reg >> 10) & 0x3fffff; }
+    constexpr uint32_t ASID(uint32_t reg) { return (reg >> 0) & 0xff; }
+  }
+
+  namespace ptel {
+    constexpr uint32_t PPN(uint32_t reg) { return (reg >> 10) & 0x7ffff; }
+
+    namespace v {
+      constexpr uint32_t invalid = 0 << 8;
+      constexpr uint32_t valid = 1 << 8;
+
+      constexpr uint32_t bit_mask = 0x1 << 8;
+    }
+
+    namespace sz {
+      constexpr uint32_t _1_kbyte_page = 0b0000 << 4;
+      constexpr uint32_t _4_kbyte_page = 0b0001 << 4;
+      constexpr uint32_t _64_kbyte_page = 0b1000 << 4;
+      constexpr uint32_t _1_mbyte_page = 0b1001 << 4;
+
+      constexpr uint32_t bit_mask = 0xf << 4;
+    }
+
+    namespace pr {
+      constexpr uint32_t read_only_in_privileged_mode = 0b00 << 5;
+      constexpr uint32_t read_write_in_privileged_mode = 0b01 << 5;
+      constexpr uint32_t read_only_in_privileged_and_user_mode = 0b10 << 5;
+      constexpr uint32_t read_write_in_privileged_and_user_mode = 0b11 << 5;
+
+      constexpr uint32_t bit_mask = 0x3 << 5;
+    }
+
+    namespace c {
+      constexpr uint32_t not_cacheable = 0 << 3;
+      constexpr uint32_t cacheable = 1 << 3;
+
+      constexpr uint32_t bit_mask = 0x1 << 3;
+    }
+
+    namespace d {
+      constexpr uint32_t write_has_not_been_performed = 0 << 2;
+      constexpr uint32_t write_has_been_performed = 1 << 2;
+
+      constexpr uint32_t bit_mask = 0x1 << 2;
+    }
+
+    namespace sh {
+      constexpr uint32_t pages_are_shared_by_processes = 0 << 1;
+      constexpr uint32_t pages_are_not_shared_by_processes = 1 << 1;
+
+      constexpr uint32_t bit_mask = 0x1 << 1;
+    }
+
+    namespace wt {
+      constexpr uint32_t copy_back_mode = 0 << 0;
+      constexpr uint32_t write_through_mode = 1 << 0;
+
+      constexpr uint32_t bit_mask = 0x1 << 0;
+    }
+  }
+
+  namespace mmucr {
+    constexpr uint32_t LRUI(uint32_t reg) { return (reg >> 26) & 0x3f; }
+    constexpr uint32_t URB(uint32_t reg) { return (reg >> 18) & 0x3f; }
+    constexpr uint32_t URC(uint32_t reg) { return (reg >> 10) & 0x3f; }
+
+    namespace sqmd {
+      constexpr uint32_t user_privileged_access_possible = 0 << 9;
+      constexpr uint32_t privileged_access_possible = 1 << 9;
+
+      constexpr uint32_t bit_mask = 0x1 << 9;
+    }
+
+    namespace sv {
+      constexpr uint32_t multiple_virtual_memory_mode = 0 << 8;
+      constexpr uint32_t single_virtual_memory_mode = 1 << 8;
+
+      constexpr uint32_t bit_mask = 0x1 << 8;
+    }
+
+    namespace ti {
+      constexpr uint32_t invalidate_all_utlb_itlb_bits = 1 << 2;
+
+      constexpr uint32_t bit_mask = 0x1 << 2;
+    }
+
+    namespace at {
+      constexpr uint32_t mmu_disabled = 0 << 0;
+      constexpr uint32_t mmu_enabled = 1 << 0;
+
+      constexpr uint32_t bit_mask = 0x1 << 0;
+    }
+  }
+
+  namespace basra {
+    constexpr uint32_t basa(uint32_t num) { return (num & 0xff) << 0; }
+  }
+
+  namespace basrb {
+    constexpr uint32_t basa(uint32_t num) { return (num & 0xff) << 0; }
+  }
+
+  namespace ccr {
+    namespace iix {
+      constexpr uint32_t address_bits_12_5_used_for_ic_entry_selection = 0 << 15;
+      constexpr uint32_t address_bits_25_and_11_5_used_for_ic_entry_selection = 1 << 15;
+
+      constexpr uint32_t bit_mask = 0x1 << 15;
+    }
+
+    namespace ici {
+      constexpr uint32_t clear_v_bits_of_all_ic_entries = 1 << 11;
+
+      constexpr uint32_t bit_mask = 0x1 << 11;
+    }
+
+    namespace ice {
+      constexpr uint32_t ic_not_used = 0 << 8;
+      constexpr uint32_t ic_used = 1 << 8;
+
+      constexpr uint32_t bit_mask = 0x1 << 8;
+    }
+
+    namespace oix {
+      constexpr uint32_t address_bits_13_5_used_for_oc_entry_selection = 0 << 7;
+      constexpr uint32_t address_bits_25_and_12_5_used_for_oc_entry_selection = 1 << 7;
+
+      constexpr uint32_t bit_mask = 0x1 << 7;
+    }
+
+    namespace ora {
+      constexpr uint32_t _16_kbytes_used_as_cache = 0 << 5;
+      constexpr uint32_t _8_kbytes_used_as_cache_8_kbytes_used_as_ram = 1 << 5;
+
+      constexpr uint32_t bit_mask = 0x1 << 5;
+    }
+
+    namespace oci {
+      constexpr uint32_t clear_v_and_u_bits_of_all_oc_entries = 1 << 3;
+
+      constexpr uint32_t bit_mask = 0x1 << 3;
+    }
+
+    namespace cb {
+      constexpr uint32_t write_through_mode = 0 << 2;
+      constexpr uint32_t copy_back_mode = 1 << 2;
+
+      constexpr uint32_t bit_mask = 0x1 << 2;
+    }
+
+    namespace wt {
+      constexpr uint32_t copy_back_mode = 0 << 1;
+      constexpr uint32_t write_through_mode = 1 << 1;
+
+      constexpr uint32_t bit_mask = 0x1 << 1;
+    }
+
+    namespace oce {
+      constexpr uint32_t oc_not_used = 0 << 0;
+      constexpr uint32_t oc_used = 1 << 0;
+
+      constexpr uint32_t bit_mask = 0x1 << 0;
+    }
+  }
+
+  namespace tra {
+    constexpr uint32_t imm(uint32_t reg) { return (reg >> 2) & 0xff; }
+  }
+
+  namespace expevt {
+    constexpr uint32_t exception_code(uint32_t reg) { return (reg >> 0) & 0xfff; }
+  }
+
+  namespace intevt {
+    constexpr uint32_t exception_code(uint32_t reg) { return (reg >> 0) & 0xfff; }
+  }
+
+  namespace ptea {
+    namespace tc {
+      constexpr uint32_t area_5_is_used = 0 << 3;
+      constexpr uint32_t area_6_is_used = 1 << 3;
+
+      constexpr uint32_t bit_mask = 0x1 << 3;
+    }
+
+    namespace sa {
+      constexpr uint32_t undefined = 0b000 << 0;
+      constexpr uint32_t variable_size_io_space = 0b001 << 0;
+      constexpr uint32_t _8_bit_io_space = 0b010 << 0;
+      constexpr uint32_t _16_bit_io_space = 0b011 << 0;
+      constexpr uint32_t _8_bit_common_memory_space = 0b100 << 0;
+      constexpr uint32_t _16_bit_common_memory_space = 0b101 << 0;
+      constexpr uint32_t _8_bit_attribute_memory_space = 0b110 << 0;
+      constexpr uint32_t _16_bit_attribute_memory_space = 0b111 << 0;
+
+      constexpr uint32_t bit_mask = 0x7 << 0;
+    }
+  }
+
+  namespace qacr0 {
+    constexpr uint32_t area(uint32_t num) { return (num & 0x7) << 2; }
+  }
+
+  namespace qacr1 {
+    constexpr uint32_t area(uint32_t num) { return (num & 0x7) << 2; }
+  }
+
+}
+
+namespace dmac {
+  namespace dmatcr {
+    constexpr uint32_t transfer_count(uint32_t num) { return (num & 0xffffff) << 0; }
+  }
+
+  namespace chcr {
+    namespace ssa {
+      constexpr uint32_t reserved_in_pcmcia_access = 0b000 << 29;
+      constexpr uint32_t dynamic_bus_sizing_io_space = 0b001 << 29;
+      constexpr uint32_t _8_bit_io_space = 0b010 << 29;
+      constexpr uint32_t _16_bit_io_space = 0b011 << 29;
+      constexpr uint32_t _8_bit_common_memory_space = 0b100 << 29;
+      constexpr uint32_t _16_bit_common_memory_space = 0b101 << 29;
+      constexpr uint32_t _8_bit_attribute_memory_space = 0b110 << 29;
+      constexpr uint32_t _16_bit_attribute_memory_space = 0b111 << 29;
+
+      constexpr uint32_t bit_mask = 0x7 << 29;
+    }
+
+    namespace stc {
+      constexpr uint32_t c5_space_wait_cycle_selection = 0 << 28;
+      constexpr uint32_t c6_space_wait_cycle_selection = 1 << 28;
+
+      constexpr uint32_t bit_mask = 0x1 << 28;
+    }
+
+    namespace dsa {
+      constexpr uint32_t reserved_in_pcmcia_access = 0b000 << 25;
+      constexpr uint32_t dynamic_bus_sizing_io_space = 0b001 << 25;
+      constexpr uint32_t _8_bit_io_space = 0b010 << 25;
+      constexpr uint32_t _16_bit_io_space = 0b011 << 25;
+      constexpr uint32_t _8_bit_common_memory_space = 0b100 << 25;
+      constexpr uint32_t _16_bit_common_memory_space = 0b101 << 25;
+      constexpr uint32_t _8_bit_attribute_memory_space = 0b110 << 25;
+      constexpr uint32_t _16_bit_attribute_memory_space = 0b111 << 25;
+
+      constexpr uint32_t bit_mask = 0x7 << 25;
+    }
+
+    namespace dtc {
+      constexpr uint32_t c5_space_wait_cycle_selection = 0 << 24;
+      constexpr uint32_t c6_space_wait_cycle_selection = 1 << 24;
+
+      constexpr uint32_t bit_mask = 0x1 << 24;
+    }
+
+    namespace ds {
+      constexpr uint32_t low_level_detection = 0 << 19;
+      constexpr uint32_t falling_edge_detection = 1 << 19;
+
+      constexpr uint32_t bit_mask = 0x1 << 19;
+    }
+
+    namespace rl {
+      constexpr uint32_t drak_is_an_active_high = 0 << 18;
+      constexpr uint32_t drak_is_an_active_low = 1 << 18;
+
+      constexpr uint32_t bit_mask = 0x1 << 18;
+    }
+
+    namespace am {
+      constexpr uint32_t dack_is_output_in_read_cycle = 0 << 17;
+      constexpr uint32_t dack_is_output_in_write_cycle = 1 << 17;
+
+      constexpr uint32_t bit_mask = 0x1 << 17;
+    }
+
+    namespace al {
+      constexpr uint32_t active_high_output = 0 << 16;
+      constexpr uint32_t active_low_output = 1 << 16;
+
+      constexpr uint32_t bit_mask = 0x1 << 16;
+    }
+
+    namespace dm {
+      constexpr uint32_t destination_address_fixed = 0b00 << 14;
+      constexpr uint32_t destination_address_incremented = 0b01 << 14;
+      constexpr uint32_t destination_address_decremented = 0b10 << 14;
+
+      constexpr uint32_t bit_mask = 0x3 << 14;
+    }
+
+    namespace sm {
+      constexpr uint32_t source_address_fixed = 0b00 << 12;
+      constexpr uint32_t source_address_incremented = 0b01 << 12;
+      constexpr uint32_t source_address_decremented = 0b10 << 12;
+
+      constexpr uint32_t bit_mask = 0x3 << 12;
+    }
+
+    namespace rs {
+      constexpr uint32_t resource_select(uint32_t num) { return (num & 0xf) << 8; }
+
+      constexpr uint32_t bit_mask = 0xf << 8;
+    }
+
+    namespace tm {
+      constexpr uint32_t cycle_steal_mode = 0 << 7;
+      constexpr uint32_t cycle_burst_mode = 1 << 7;
+
+      constexpr uint32_t bit_mask = 0x1 << 7;
+    }
+
+    namespace ts {
+      constexpr uint32_t _64_bit = 0b000 << 4;
+      constexpr uint32_t _8_bit = 0b001 << 4;
+      constexpr uint32_t _16_bit = 0b010 << 4;
+      constexpr uint32_t _32_bit = 0b011 << 4;
+      constexpr uint32_t _32_byte = 0b100 << 4;
+
+      constexpr uint32_t bit_mask = 0x7 << 4;
+    }
+
+    namespace ie {
+      constexpr uint32_t interrupt_request_not_generated = 0 << 2;
+      constexpr uint32_t interrupt_request_generated = 1 << 2;
+
+      constexpr uint32_t bit_mask = 0x1 << 2;
+    }
+
+    namespace te {
+      constexpr uint32_t transfers_not_completed = 0 << 1;
+      constexpr uint32_t transfers_completed = 1 << 1;
+
+      constexpr uint32_t bit_mask = 0x1 << 1;
+    }
+
+    namespace de {
+      constexpr uint32_t channel_operation_disabled = 0 << 0;
+      constexpr uint32_t channel_operation_enabled = 1 << 0;
+
+      constexpr uint32_t bit_mask = 0x1 << 0;
+    }
+  }
+
+  namespace dmaor {
+    namespace ddt {
+      constexpr uint32_t normal_dma_mode = 0 << 15;
+      constexpr uint32_t on_demand_data_transfer_mode = 1 << 15;
+
+      constexpr uint32_t bit_mask = 0x1 << 15;
+    }
+
+    namespace pr {
+      constexpr uint32_t ch0_ch1_ch2_ch3 = 0b00 << 8;
+      constexpr uint32_t ch0_ch2_ch3_ch1 = 0b01 << 8;
+      constexpr uint32_t ch2_ch0_ch1_ch3 = 0b10 << 8;
+      constexpr uint32_t round_robin = 0b11 << 8;
+
+      constexpr uint32_t bit_mask = 0x3 << 8;
+    }
+
+    namespace ae {
+      constexpr uint32_t no_address_error__dma_transfer_enabled = 0 << 2;
+      constexpr uint32_t address_error__dma_transfer_disabled = 1 << 2;
+
+      constexpr uint32_t bit_mask = 0x1 << 2;
+    }
+
+    namespace nmif {
+      constexpr uint32_t no_nmi__dma_transfer_enabled = 0 << 1;
+      constexpr uint32_t nmi__dma_transfer_disabled = 1 << 1;
+
+      constexpr uint32_t bit_mask = 0x1 << 1;
+    }
+
+    namespace dme {
+      constexpr uint32_t operation_disabled_on_all_channels = 0 << 0;
+      constexpr uint32_t operation_enabled_on_all_channels = 1 << 0;
+
+      constexpr uint32_t bit_mask = 0x1 << 0;
+    }
+  }
+
+}
+
+namespace intc {
+  namespace icr {
+    namespace nmil {
+      constexpr uint32_t pin_input_level_is_low = 0 << 15;
+      constexpr uint32_t pin_input_level_is_high = 1 << 15;
+
+      constexpr uint32_t bit_mask = 0x1 << 15;
+    }
+
+    namespace mai {
+      constexpr uint32_t interrupts_enabled_while_nmi_pin_is_low = 0 << 14;
+      constexpr uint32_t interrupts_disabled_while_nmi_pin_is_low = 1 << 14;
+
+      constexpr uint32_t bit_mask = 0x1 << 14;
+    }
+
+    namespace nmib {
+      constexpr uint32_t interrupt_requests_witheld = 0 << 9;
+      constexpr uint32_t interrupt_requests_detected = 1 << 9;
+
+      constexpr uint32_t bit_mask = 0x1 << 9;
+    }
+
+    namespace nmie {
+      constexpr uint32_t interrupt_on_falling_edge_of_nmi = 0 << 8;
+      constexpr uint32_t interrupt_on_rising_edge_of_nmi = 1 << 8;
+
+      constexpr uint32_t bit_mask = 0x1 << 8;
+    }
+
+    namespace irlm {
+      constexpr uint32_t level_encoded_interrupt_requests = 0 << 7;
+      constexpr uint32_t independent_interrupt_request = 1 << 7;
+
+      constexpr uint32_t bit_mask = 0x1 << 7;
+    }
+  }
+
+  namespace ipra {
+    constexpr uint32_t TMU0(uint32_t num) { return (num & 0xf) << 12; }
+    constexpr uint32_t TMU1(uint32_t num) { return (num & 0xf) << 8; }
+    constexpr uint32_t TMU2(uint32_t num) { return (num & 0xf) << 4; }
+    constexpr uint32_t RTC(uint32_t num) { return (num & 0xf) << 0; }
+  }
+
+  namespace iprb {
+    constexpr uint32_t WDT(uint32_t num) { return (num & 0xf) << 12; }
+    constexpr uint32_t REF(uint32_t num) { return (num & 0xf) << 8; }
+    constexpr uint32_t SCI1(uint32_t num) { return (num & 0xf) << 4; }
+  }
+
+  namespace iprc {
+    constexpr uint32_t GPIO(uint32_t num) { return (num & 0xf) << 12; }
+    constexpr uint32_t DMAC(uint32_t num) { return (num & 0xf) << 8; }
+    constexpr uint32_t SCIF(uint32_t num) { return (num & 0xf) << 4; }
+    constexpr uint32_t UDI(uint32_t num) { return (num & 0xf) << 0; }
+  }
+
+}
+
+namespace tmu {
+  namespace tocr {
+    namespace tcoe {
+      constexpr uint32_t tclk_is_external_clock_or_input_capture = 0 << 0;
+      constexpr uint32_t tclk_is_on_chip_rtc = 1 << 0;
+
+      constexpr uint32_t bit_mask = 0x1 << 0;
+    }
+  }
+
+  namespace tstr {
+    namespace str2 {
+      constexpr uint32_t counter_start = 1 << 2;
+
+      constexpr uint32_t bit_mask = 0x1 << 2;
+    }
+
+    namespace str1 {
+      constexpr uint32_t counter_start = 1 << 1;
+
+      constexpr uint32_t bit_mask = 0x1 << 1;
+    }
+
+    namespace str0 {
+      constexpr uint32_t counter_start = 1 << 0;
+
+      constexpr uint32_t bit_mask = 0x1 << 0;
+    }
+  }
+
+  namespace tcr0 {
+    constexpr uint32_t UNF = 1 << 8;
+    constexpr uint32_t UNIE = 1 << 5;
+
+    namespace ckeg {
+      constexpr uint32_t rising = 0b00 << 3;
+      constexpr uint32_t falling = 0b01 << 3;
+      constexpr uint32_t rising_falling = 0b10 << 3;
+
+      constexpr uint32_t bit_mask = 0x3 << 3;
+    }
+
+    namespace tpsc {
+      constexpr uint32_t p_phi_4 = 0b000 << 0;
+      constexpr uint32_t p_phi_16 = 0b001 << 0;
+      constexpr uint32_t p_phi_64 = 0b010 << 0;
+      constexpr uint32_t p_phi_256 = 0b011 << 0;
+      constexpr uint32_t p_phi_1024 = 0b100 << 0;
+      constexpr uint32_t rtc_output = 0b110 << 0;
+      constexpr uint32_t external = 0b111 << 0;
+
+      constexpr uint32_t bit_mask = 0x7 << 0;
+    }
+  }
+
+  namespace tcr1 {
+    constexpr uint32_t UNF = 1 << 8;
+    constexpr uint32_t UNIE = 1 << 5;
+
+    namespace ckeg {
+      constexpr uint32_t rising = 0b00 << 3;
+      constexpr uint32_t falling = 0b01 << 3;
+      constexpr uint32_t rising_falling = 0b10 << 3;
+
+      constexpr uint32_t bit_mask = 0x3 << 3;
+    }
+
+    namespace tpsc {
+      constexpr uint32_t p_phi_4 = 0b000 << 0;
+      constexpr uint32_t p_phi_16 = 0b001 << 0;
+      constexpr uint32_t p_phi_64 = 0b010 << 0;
+      constexpr uint32_t p_phi_256 = 0b011 << 0;
+      constexpr uint32_t p_phi_1024 = 0b100 << 0;
+      constexpr uint32_t rtc_output = 0b110 << 0;
+      constexpr uint32_t external = 0b111 << 0;
+
+      constexpr uint32_t bit_mask = 0x7 << 0;
+    }
+  }
+
+  namespace tcr2 {
+    constexpr uint32_t ICPF = 1 << 9;
+    constexpr uint32_t UNF = 1 << 8;
+
+    namespace icpe {
+      constexpr uint32_t disabled = 0b00 << 6;
+      constexpr uint32_t enabled = 0b10 << 6;
+      constexpr uint32_t enabled_with_interrupts = 0b11 << 6;
+
+      constexpr uint32_t bit_mask = 0x3 << 6;
+    }
+
+    constexpr uint32_t UNIE = 1 << 5;
+
+    namespace ckeg {
+      constexpr uint32_t rising = 0b00 << 3;
+      constexpr uint32_t falling = 0b01 << 3;
+      constexpr uint32_t rising_falling = 0b10 << 3;
+
+      constexpr uint32_t bit_mask = 0x3 << 3;
+    }
+
+    namespace tpsc {
+      constexpr uint32_t p_phi_4 = 0b000 << 0;
+      constexpr uint32_t p_phi_16 = 0b001 << 0;
+      constexpr uint32_t p_phi_64 = 0b010 << 0;
+      constexpr uint32_t p_phi_256 = 0b011 << 0;
+      constexpr uint32_t p_phi_1024 = 0b100 << 0;
+      constexpr uint32_t rtc_output = 0b110 << 0;
+      constexpr uint32_t external = 0b111 << 0;
+
+      constexpr uint32_t bit_mask = 0x7 << 0;
+    }
+  }
+
+}
+
+namespace scif {
+  namespace scsmr2 {
+    namespace chr {
+      constexpr uint32_t _8_bit_data = 0 << 6;
+      constexpr uint32_t _7_bit_data = 1 << 6;
+
+      constexpr uint32_t bit_mask = 0x1 << 6;
+    }
+
+    namespace pe {
+      constexpr uint32_t parity_disabled = 0 << 5;
+      constexpr uint32_t parity_enabled = 1 << 5;
+
+      constexpr uint32_t bit_mask = 0x1 << 5;
+    }
+
+    namespace oe {
+      constexpr uint32_t even_parity = 0 << 4;
+      constexpr uint32_t odd_parity = 1 << 4;
+
+      constexpr uint32_t bit_mask = 0x1 << 4;
+    }
+
+    namespace stop {
+      constexpr uint32_t _1_stop_bit = 0 << 3;
+      constexpr uint32_t _2_stop_bits = 1 << 3;
+
+      constexpr uint32_t bit_mask = 0x1 << 3;
+    }
+
+    namespace cks {
+      constexpr uint32_t p_phi_clock = 0b00 << 0;
+      constexpr uint32_t p_phi_4_clock = 0b01 << 0;
+      constexpr uint32_t p_phi_16_clock = 0b10 << 0;
+      constexpr uint32_t p_phi_64_clock = 0b11 << 0;
+
+      constexpr uint32_t bit_mask = 0x3 << 0;
+    }
+  }
+
+  namespace scscr2 {
+    namespace tie {
+      constexpr uint32_t transmit_fifo_data_empty_interrupt_disabled = 0 << 7;
+      constexpr uint32_t transmit_fifo_data_empty_interrupt_enabled = 1 << 7;
+
+      constexpr uint32_t bit_mask = 0x1 << 7;
+    }
+
+    namespace rie {
+      constexpr uint32_t request_disabled = 0 << 6;
+      constexpr uint32_t request_enabled = 1 << 6;
+
+      constexpr uint32_t bit_mask = 0x1 << 6;
+    }
+
+    namespace te {
+      constexpr uint32_t transmission_disabled = 0 << 5;
+      constexpr uint32_t transmission_enabled = 1 << 5;
+
+      constexpr uint32_t bit_mask = 0x1 << 5;
+    }
+
+    namespace re {
+      constexpr uint32_t reception_disabled = 0 << 4;
+      constexpr uint32_t reception_enabled = 1 << 4;
+
+      constexpr uint32_t bit_mask = 0x1 << 4;
+    }
+
+    namespace reie {
+      constexpr uint32_t requests_disabled = 0 << 3;
+      constexpr uint32_t requests_enabled = 1 << 3;
+
+      constexpr uint32_t bit_mask = 0x1 << 3;
+    }
+
+    namespace cke1 {
+      constexpr uint32_t sck2_pin_functions_as_input_pin = 0 << 1;
+      constexpr uint32_t sck2_pin_functions_as_clock_input = 1 << 1;
+
+      constexpr uint32_t bit_mask = 0x1 << 1;
+    }
+  }
+
+  namespace scfsr2 {
+    namespace per3_0 {
+      constexpr uint32_t number_of_parity_errors(uint32_t reg) { return (reg >> 12) & 0xf; }
+
+      constexpr uint32_t bit_mask = 0xf << 12;
+    }
+
+    namespace fer3_0 {
+      constexpr uint32_t number_of_framing_errors(uint32_t reg) { return (reg >> 8) & 0xf; }
+
+      constexpr uint32_t bit_mask = 0xf << 8;
+    }
+
+    namespace er {
+      constexpr uint32_t no_framing_error_or_parity_error = 0 << 7;
+      constexpr uint32_t framing_error_or_parity_error = 1 << 7;
+
+      constexpr uint32_t bit_mask = 0x1 << 7;
+    }
+
+    namespace tend {
+      constexpr uint32_t transmission_in_progress = 0 << 6;
+      constexpr uint32_t transmission_has_ended = 1 << 6;
+
+      constexpr uint32_t bit_mask = 0x1 << 6;
+    }
+
+    namespace tdfe {
+      constexpr uint32_t transmit_data_bytes_does_exceed_trigger = 0 << 5;
+      constexpr uint32_t transmit_data_bytes_does_not_exceed_trigger = 1 << 5;
+
+      constexpr uint32_t bit_mask = 0x1 << 5;
+    }
+
+    namespace brk {
+      constexpr uint32_t break_not_received = 0 << 4;
+      constexpr uint32_t break_received = 1 << 4;
+
+      constexpr uint32_t bit_mask = 0x1 << 4;
+    }
+
+    namespace fer {
+      constexpr uint32_t no_framing_error = 0 << 3;
+      constexpr uint32_t framing_error = 1 << 3;
+
+      constexpr uint32_t bit_mask = 0x1 << 3;
+    }
+
+    namespace per {
+      constexpr uint32_t parity_error = 0 << 2;
+      constexpr uint32_t no_parity_error = 1 << 2;
+
+      constexpr uint32_t bit_mask = 0x1 << 2;
+    }
+
+    namespace rdf {
+      constexpr uint32_t receive_data_bytes_less_than_receive_trigger = 0 << 1;
+      constexpr uint32_t receive_data_bytes_greater_than_or_equal_receive_trigger = 1 << 1;
+
+      constexpr uint32_t bit_mask = 0x1 << 1;
+    }
+
+    namespace dr {
+      constexpr uint32_t reception_is_in_progress = 0 << 0;
+      constexpr uint32_t no_further_data_has_arrived = 1 << 0;
+
+      constexpr uint32_t bit_mask = 0x1 << 0;
+    }
+  }
+
+  namespace scfcr2 {
+    namespace rtrg {
+      constexpr uint32_t trigger_on_1_byte = 0b00 << 6;
+      constexpr uint32_t trigger_on_4_bytes = 0b01 << 6;
+      constexpr uint32_t trigger_on_8_bytes = 0b10 << 6;
+      constexpr uint32_t trigger_on_14_byte = 0b11 << 6;
+
+      constexpr uint32_t bit_mask = 0x3 << 6;
+    }
+
+    namespace ttrg {
+      constexpr uint32_t trigger_on_8_bytes = 0b00 << 4;
+      constexpr uint32_t trigger_on_4_bytes = 0b01 << 4;
+      constexpr uint32_t trigger_on_2_bytes = 0b10 << 4;
+      constexpr uint32_t trigger_on_1_bytes = 0b11 << 4;
+
+      constexpr uint32_t bit_mask = 0x3 << 4;
+    }
+
+    namespace mce {
+      constexpr uint32_t modem_signals_disabled = 0 << 3;
+      constexpr uint32_t modem_signals_enabled = 1 << 3;
+
+      constexpr uint32_t bit_mask = 0x1 << 3;
+    }
+
+    namespace tfrst {
+      constexpr uint32_t reset_operation_disabled = 0 << 2;
+      constexpr uint32_t reset_operation_enabled = 1 << 2;
+
+      constexpr uint32_t bit_mask = 0x1 << 2;
+    }
+
+    namespace rfrst {
+      constexpr uint32_t reset_operation_disabled = 0 << 1;
+      constexpr uint32_t reset_operation_enabled = 1 << 1;
+
+      constexpr uint32_t bit_mask = 0x1 << 1;
+    }
+
+    namespace loop {
+      constexpr uint32_t loopback_test_disabled = 0 << 0;
+      constexpr uint32_t loopback_test_enabled = 1 << 0;
+
+      constexpr uint32_t bit_mask = 0x1 << 0;
+    }
+  }
+
+  namespace scfdr2 {
+    constexpr uint32_t transmit_data_bytes(uint32_t reg) { return (reg >> 8) & 0x1f; }
+    constexpr uint32_t receive_data_bytes(uint32_t reg) { return (reg >> 0) & 0x1f; }
+  }
+
+  namespace scsptr2 {
+    namespace rtsio {
+      constexpr uint32_t rtsdt_not_output_to_rts2 = 0 << 7;
+      constexpr uint32_t rtsdt_output_to_rts2 = 1 << 7;
+
+      constexpr uint32_t bit_mask = 0x1 << 7;
+    }
+
+    namespace rtsdt {
+      constexpr uint32_t input_output_data_is_low_level = 0 << 6;
+      constexpr uint32_t input_output_data_is_high_level = 1 << 6;
+
+      constexpr uint32_t bit_mask = 0x1 << 6;
+    }
+
+    namespace ctsio {
+      constexpr uint32_t ctsdt_is_not_output_to_cts2 = 0 << 5;
+      constexpr uint32_t ctsdt_is_output_to_cts2 = 1 << 5;
+
+      constexpr uint32_t bit_mask = 0x1 << 5;
+    }
+
+    namespace ctsdt {
+      constexpr uint32_t input_output_data_is_low_level = 0 << 4;
+      constexpr uint32_t input_output_data_is_high_level = 1 << 4;
+
+      constexpr uint32_t bit_mask = 0x1 << 4;
+    }
+
+    namespace spb2io {
+      constexpr uint32_t spb2dt_is_not_output_to_txd2 = 0 << 1;
+      constexpr uint32_t spb2dt_is_output_to_txd2 = 1 << 1;
+
+      constexpr uint32_t bit_mask = 0x1 << 1;
+    }
+
+    namespace spb2dt {
+      constexpr uint32_t input_output_data_is_low_level = 0 << 0;
+      constexpr uint32_t input_output_data_is_high_level = 1 << 0;
+
+      constexpr uint32_t bit_mask = 0x1 << 0;
+    }
+  }
+
+}
diff --git a/storequeue.cpp b/sh7091/storequeue.cpp
similarity index 100%
rename from storequeue.cpp
rename to sh7091/storequeue.cpp
diff --git a/storequeue.hpp b/sh7091/storequeue.hpp
similarity index 100%
rename from storequeue.hpp
rename to sh7091/storequeue.hpp
diff --git a/sh7091_bits.hpp b/sh7091_bits.hpp
deleted file mode 100644
index e5996c1..0000000
--- a/sh7091_bits.hpp
+++ /dev/null
@@ -1,101 +0,0 @@
-#define CCR__IIX (1 << 15)
-#define CCR__ICI (1 << 11)
-#define CCR__ICE (1 << 8)
-#define CCR__OIX (1 << 7)
-#define CCR__ORA (1 << 5)
-#define CCR__OCI (1 << 4)
-#define CCR__CB  (1 << 2)
-#define CCR__WT  (1 << 1)
-#define CCR__OCE (1 << 0)
-
-#define PDTRA__MASK     (0b11 << 8)
-#define PDTRA__VGA      (0b00 << 8)
-#define PDTRA__RESERVED (0b01 << 8)
-#define PDTRA__RGB      (0b10 << 8)
-#define PDTRA__AV       (0b11 << 8)
-
-#define SCFCR2__TFRST (1 << 2)
-#define SCFCR2__RFRST (1 << 1)
-
-#define SCSCR2__TE (1 << 5)
-#define SCSCR2__RE (1 << 4)
-
-#define SCFSR2__ER   (1 << 7) /* read error */
-#define SCFSR2__TEND (1 << 6) /* transmit end */
-#define SCFSR2__TDFE (1 << 5) /* transmit fifo data empty */
-#define SCFSR2__BRK  (1 << 4) /* break detect */
-#define SCFSR2__FER  (1 << 3) /* framing error */
-#define SCFSR2__PER  (1 << 2) /* parity error */
-#define SCFSR2__RDF  (1 << 1) /* receive FIFO data full */
-#define SCFSR2__DR   (1 << 0) /* receive data ready */
-
-#define DMAOR__DDT (1 << 15) /* on-demand data transfer mode */
-/* priority mode */
-#define DMAOR__PR__CH0_CH1_CH2_CH3 (0b11 << 8)
-#define DMAOR__PR__CH0_CH2_CH3_CH1 (0b01 << 8)
-#define DMAOR__PR__CH2_CH0_CH1_CH3 (0b10 << 8)
-#define DMAOR__PR__ROUND_ROBIN     (0b11 << 8)
-#define DMAOR__AE (1 << 2)  /* address error flag; clear-only */
-#define DMAOR__NMIF (1 << 1) /* non-maskable interrupt flag; clear-only */
-#define DMAOR__DME (1 << 0) /* DMAC master enable */
-
-/* source address space attribute specification */
-#define CHCR2__SSA__RESERVED_IN_PCMCIA_ACCESS    (0b000 << 29)
-#define CHCR2__SSA__DYNAMIC_BUS_SIZING_IO_SPACE  (0b001 << 29)
-#define CHCR2__SSA__8BIT_IO_SPACE                (0b010 << 29)
-#define CHCR2__SSA__16BIT_IO_SPACE               (0b011 << 29)
-#define CHCR2__SSA__8BIT_COMMON_MEMORY_SPACE     (0b100 << 29)
-#define CHCR2__SSA__16BIT_COMMON_MEMORY_SPACE    (0b101 << 29)
-#define CHCR2__SSA__8BIT_ATTRIBUTE_MEMORY_SPACE  (0b110 << 29)
-#define CHCR2__SSA__16BIT_ATTRIBUTE_MEMORY_SPACE (0b111 << 29)
-/* source address wait control select */
-#define CHCR2__STC__C5_SPACE_WAIT_CYCLE_SELECTION (0 << 28)
-#define CHCR2__STC__C6_SPACE_WAIT_CYCLE_SELECTION (1 << 28)
-/* destination address space attribute specification */
-#define CHCR2__DSA__RESERVED_IN_PCMCIA_ACCESS    (0b000 << 25)
-#define CHCR2__DSA__DYNAMIC_BUS_SIZING_IO_SPACE  (0b001 << 25)
-#define CHCR2__DSA__8BIT_IO_SPACE                (0b010 << 25)
-#define CHCR2__DSA__16BIT_IO_SPACE               (0b011 << 25)
-#define CHCR2__DSA__8BIT_COMMON_MEMORY_SPACE     (0b100 << 25)
-#define CHCR2__DSA__16BIT_COMMON_MEMORY_SPACE    (0b101 << 25)
-#define CHCR2__DSA__8BIT_ATTRIBUTE_MEMORY_SPACE  (0b110 << 25)
-#define CHCR2__DSA__16BIT_ATTRIBUTE_MEMORY_SPACE (0b111 << 25)
-/* destination address wait control select */
-#define CHCR2__DTC__C5_SPACE_WAIT_CYCLE_SELECTION (0 << 24)
-#define CHCR2__DTC__C6_SPACE_WAIT_CYCLE_SELECTION (1 << 24)
-/* DREQ select */
-#define CHCR2__DS__LOW_LEVEL_DETECTION    (0 << 19)
-#define CHCR2__DS__FALLING_EDGE_DETECTION (1 << 19)
-/* request check level */
-#define CHCR2__RL__DRAK_IS_AN_ACTIVE_HIGH_OUTPUT (0 << 18)
-#define CHCR2__RL__DRAK_IS_AN_ACTIVE_LOW_OUTPUT  (1 << 18)
-/* acknowledge mode */
-#define CHCR2__AM__DACK_IS_OUTPUT_IN_READ_CYCLE  (0 << 17)
-#define CHCR2__AM__DACK_IS_OUTPUT_IN_WRITE_CYCLE (1 << 17)
-/* acknowledge level */
-#define CHCR2__AL__ACTIVE_HIGH_OUTPUT (0 << 16)
-#define CHCR2__AL__ACTIVE_LOW_OUTPUT  (1 << 16)
-/* destination address mode */
-#define CHCR2__DM__DESTINATION_ADDRESS_FIXED       (0b00 << 14)
-#define CHCR2__DM__DESTINATION_ADDRESS_INCREMENTED (0b01 << 14)
-#define CHCR2__DM__DESTINATION_ADDRESS_DECREMENTED (0b10 << 14)
-/* source address mode */
-#define CHCR2__SM__SOURCE_ADDRESS_FIXED       (0b00 << 12)
-#define CHCR2__SM__SOURCE_ADDRESS_INCREMENTED (0b01 << 12)
-#define CHCR2__SM__SOURCE_ADDRESS_DECREMENTED (0b10 << 12)
-/* resource select */
-#define CHCR2__RS(n) (((n) & 0b1111) << 8)
-/* transmit mode */
-#define CHCR2__TM__CYCLE_STEAL_MODE (0 << 7)
-#define CHCR2__TM__BURST_MODE       (1 << 7)
-/* transmit size */
-#define CHCR2__TS__64_BIT  (0b000 << 4)
-#define CHCR2__TS__8_BIT   (0b001 << 4)
-#define CHCR2__TS__16_BIT  (0b010 << 4)
-#define CHCR2__TS__32_BIT  (0b011 << 4)
-#define CHCR2__TS__32_BYTE (0b100 << 4)
-#define CHCR2__IE  (1 << 2) /* interrupt enable */
-#define CHCR2__TE  (1 << 1) /* transfer end; clear only */
-#define CHCR2__DE  (1 << 0) /* DMAC (channel) enable */
-
-#define DMATCR2__TRANSFER_COUNT(n) (((n) & 0xffffff) << 0)
diff --git a/vga.cpp b/vga.cpp
index 82f4b81..7f4123c 100644
--- a/vga.cpp
+++ b/vga.cpp
@@ -1,8 +1,8 @@
 #include <cstdint>
 
-#include "sh7091.hpp"
-#include "sh7091_bits.hpp"
-#include "holly.hpp"
+#include "sh7091/sh7091.hpp"
+#include "sh7091/sh7091_bits.hpp"
+#include "holly/holly.hpp"
 #include "holly/core_bits.hpp"
 #include "aica.hpp"
 #include "memorymap.hpp"
@@ -10,14 +10,16 @@
 #include "vga.hpp"
 #include "rgb.hpp"
 
+/*
 uint32_t get_cable_type()
 {
-  /* set all pins to input */
+  // set all pins to input
   sh7091.BSC.PCTRA = 0;
 
-  /* get cable type from pins 9 + 8 */
+  // get cable type from pins 9 + 8
   return sh7091.BSC.PDTRA & PDTRA__MASK;
 }
+*/
 
 void vga1()
 {
@@ -117,8 +119,6 @@ void v_sync_out()
 
 void vga()
 {
-  get_cable_type();
-
   holly.SOFTRESET = softreset::sdram_if_soft_reset
 		  | softreset::pipeline_soft_reset
 		  | softreset::ta_soft_reset;