diff --git a/example/illslot.s b/example/illslot.s
index 76deb3c..039028b 100644
--- a/example/illslot.s
+++ b/example/illslot.s
@@ -1,6 +1,8 @@
 	.global _illslot
 _illslot:
+        trapa #12
 	rts
-	mova	test,r0
+	nop
+        mova	test,r0
 
 test:	.long 0x12345678
diff --git a/example/interrupt.cpp b/example/interrupt.cpp
index 3116687..ed8bc94 100644
--- a/example/interrupt.cpp
+++ b/example/interrupt.cpp
@@ -11,9 +11,11 @@ void vbr100()
 {
   serial::string("vbr100\n");
   serial::string("expevt ");
-  serial::integer(sh7091.CCN.EXPEVT);
+  serial::integer<uint16_t>(sh7091.CCN.EXPEVT);
   serial::string("intevt ");
-  serial::integer(sh7091.CCN.INTEVT);
+  serial::integer<uint16_t>(sh7091.CCN.INTEVT);
+  serial::string("tra ");
+  serial::integer<uint16_t>(sh7091.CCN.TRA);
   uint32_t spc;
   uint32_t ssr;
   asm volatile ("stc spc,%0"
@@ -42,9 +44,53 @@ void vbr600()
   while (1);
 }
 
+__attribute__ ((interrupt_handler))
+void dbr();
+
+void dbr()
+{
+  serial::string("dbr\n");
+  serial::string("expevt ");
+  serial::integer<uint16_t>(sh7091.CCN.EXPEVT);
+  serial::string("intevt ");
+  serial::integer<uint16_t>(sh7091.CCN.INTEVT);
+  serial::string("tra ");
+  serial::integer<uint16_t>(sh7091.CCN.TRA);
+
+  uint32_t spc;
+  uint32_t ssr;
+  asm volatile ("stc spc,%0" : "=r" (spc) );
+  asm volatile ("stc ssr,%0" : "=r" (ssr) );
+  serial::string("spc ");
+  serial::integer(spc);
+  serial::string("ssr ");
+  serial::integer(ssr);
+
+  uint32_t sr;
+  asm volatile ("stc sr,%0" : "=r" (sr) );
+  serial::string("sr ");
+  serial::integer(sr);
+
+  return;
+}
+
+int do_stuff(int a, int b)
+{
+  serial::string("do_stuff\n");
+  asm volatile ("nop;");
+  return a + b;
+}
+
 extern "C" uint32_t * illslot(void);
+
 void main()
 {
+  serial::string("main\n");
+  for (int i = 0; i < 10000000; i++) {
+    asm volatile ("nop;");
+  }
+  //serial::init(0);
+
   uint32_t vbr = reinterpret_cast<uint32_t>(&__vbr_link_start) - 0x100;
 
   system.IML2NRM = 0;
@@ -83,24 +129,64 @@ void main()
   serial::string("sr ");
   serial::integer<uint32_t>(sr);
 
-  sr = sr & (~(1 << 28)); // BL
+  sr &= ~sh::sr::bl; // BL
+  sr |= sh::sr::imask(15); // imask
 
-  asm volatile ("ldc %0, sr"
+  serial::string("sr ");
+  serial::integer<uint32_t>(sr);
+
+  asm volatile ("ldc %0,sr"
 		:
 		: "r" (sr));
 
-  /*
-  uint32_t vbr2;
-  asm volatile ("stc vbr,%0"
-		: "=r" (vbr2));
-  */
-
+  serial::string("vbr ");
   serial::integer<uint32_t>(vbr);
-  //serial::integer<uint32_t>(vbr2);
+  serial::string("vbr100 ");
   serial::integer<uint32_t>(reinterpret_cast<uint32_t>(&vbr100));
 
-  uint32_t * test = illslot();
-  serial::integer<uint32_t>(*test);
+  (void)dbr;
+  uint32_t dbr_address = reinterpret_cast<uint32_t>(&dbr);
+  asm volatile ("ldc %0,dbr"
+                :
+                : "r" (dbr_address));
+  serial::string("dbr ");
+  serial::integer<uint32_t>(dbr_address);
 
-  while (1);
+  sh7091.UBC.BARA = reinterpret_cast<uint32_t>(&do_stuff);
+  sh7091.CCN.BASRA = 0;
+  sh7091.UBC.BAMRA
+    = ubc::bamra::bama::all_bara_bits_are_included_in_break_conditions
+    | ubc::bamra::basma::no_basra_bits_are_included_in_break_conditions
+    ;
+  sh7091.UBC.BBRA
+    = ubc::bbra::sza::operand_size_is_not_included_in_break_conditions
+    | ubc::bbra::ida::instruction_access_cycle_is_used_as_break_condition
+    | ubc::bbra::rwa::read_cycle_or_write_cycle_is_used_as_break_condition
+    ;
+  sh7091.UBC.BRCR
+    = ubc::brcr::pcba::channel_a_pc_break_is_effected_before_instruction_execution
+    | ubc::brcr::ubde::user_break_debug_function_is_used
+    ;
+  serial::string("basra ");
+  serial::integer(sh7091.CCN.BASRA);
+  serial::string("bara ");
+  serial::integer(sh7091.UBC.BARA);
+  serial::string("bamra ");
+  serial::integer(sh7091.UBC.BAMRA);
+  serial::string("bbra ");
+  serial::integer(sh7091.UBC.BBRA);
+  serial::string("brcr ");
+  serial::integer(sh7091.UBC.BRCR);
+
+  int res = do_stuff(1, 2);
+  (void)res;
+
+  /*
+  uint32_t * test = illslot();
+  serial::string("illslot\n");
+  serial::integer<uint32_t>(*test);
+  */
+  serial::string("return\n");
+
+  //while (1);
 }
diff --git a/example/maple_device_request.cpp b/example/maple_device_request.cpp
index 0aed218..cb5beb8 100644
--- a/example/maple_device_request.cpp
+++ b/example/maple_device_request.cpp
@@ -7,15 +7,15 @@
 
 void main()
 {
-  serial::init(0);
+  //serial::init(0);
 
-  uint32_t send_buf[1024] __attribute__((aligned(32)));
-  uint32_t recv_buf[1024] __attribute__((aligned(32)));
+  uint8_t send_buf[1024] __attribute__((aligned(32)));
+  uint8_t recv_buf[1024] __attribute__((aligned(32)));
 
   using command_type = maple::device_request;
   using response_type = maple::device_status;
 
-  auto writer = maple::host_command_writer(send_buf, recv_buf);
+  auto writer = maple::host_command_writer<>(send_buf, recv_buf);
 
   auto [host_command, host_response]
     = writer.append_command_all_ports<command_type, response_type>();
@@ -47,5 +47,5 @@ void main()
     }
   }
 
-  while (1);
+  //while (1);
 }
diff --git a/ip.lds b/ip.lds
index ab523e2..82337f4 100644
--- a/ip.lds
+++ b/ip.lds
@@ -99,4 +99,4 @@ __vbr_load_end = 0;
 INCLUDE "addresses.lds"
 
 __send_buf = 0xac000020;
-__recv_buf = 0xac002020;
+__recv_buf = 0xac004020;
diff --git a/loader.lds b/loader.lds
index cbe0cc1..14a9444 100644
--- a/loader.lds
+++ b/loader.lds
@@ -75,4 +75,4 @@ INCLUDE "addresses.lds"
 __stack_end = 0x8c00f000;
 
 __send_buf = 0xac000020;
-__recv_buf = 0xac002020;
+__recv_buf = 0xac004000;
diff --git a/maple/maple.cpp b/maple/maple.cpp
index d77a3e4..c14c5a8 100644
--- a/maple/maple.cpp
+++ b/maple/maple.cpp
@@ -107,12 +107,10 @@ uint32_t init_block_write(uint32_t * command_buf, uint32_t * receive_buf,
 }
 */
 
-static inline void _dma_start(const uint32_t * command_buf)
+static inline void _dma_start(const uint8_t * command_buf)
 {
   using namespace dmac;
 
-  //command_buf = reinterpret_cast<uint32_t *>(reinterpret_cast<uint32_t>(command_buf) | 0xa000'0000);
-
   sh7091.DMAC.DMAOR = dmaor::ddt::on_demand_data_transfer_mode       /* on-demand data transfer mode */
                     | dmaor::pr::ch2_ch0_ch1_ch3                     /* priority mode; CH2 > CH0 > CH1 > CH3 */
                     | dmaor::dme::operation_enabled_on_all_channels; /* DMAC master enable */
@@ -161,9 +159,9 @@ bool dma_poll_complete()
   return complete;
 }
 
-void dma_start(const uint32_t * send_buf,
+void dma_start(uint8_t const * const send_buf,
                const uint32_t send_size,
-               const uint32_t * recv_buf,
+               uint8_t * const recv_buf,
                const uint32_t recv_size
                )
 {
@@ -171,7 +169,7 @@ void dma_start(const uint32_t * send_buf,
   for (uint32_t i = 0; i < align_32byte(send_size) / 32; i++) {
     asm volatile ("ocbwb @%0"
                   :                                                              // output
-                  : "r" (reinterpret_cast<uint32_t>(&send_buf[(32 * i) / 4])) // input
+                  : "r" (reinterpret_cast<uint32_t>(&send_buf[32 * i])) // input
                   );
   }
 
@@ -182,7 +180,7 @@ void dma_start(const uint32_t * send_buf,
   for (uint32_t i = 0; i < align_32byte(recv_size) / 32; i++) {
     asm volatile ("ocbp @%0"
                   :                                                              // output
-                  : "r" (reinterpret_cast<uint32_t>(&recv_buf[(32 * i) / 4])) // input
+                  : "r" (reinterpret_cast<uint32_t>(&recv_buf[32 * i])) // input
                   );
   }
 }
diff --git a/maple/maple.hpp b/maple/maple.hpp
index 7b92600..e0c04bf 100644
--- a/maple/maple.hpp
+++ b/maple/maple.hpp
@@ -38,9 +38,9 @@ void dma_wait_complete();
 
 bool dma_poll_complete();
 
-void dma_start(uint32_t const * const command_buf,
+void dma_start(uint8_t const * const command_buf,
                const uint32_t command_size,
-               uint32_t const * const receive_buf,
+               uint8_t * const receive_buf,
                const uint32_t receive_size
                );
 
diff --git a/maple/maple_host_command_writer.hpp b/maple/maple_host_command_writer.hpp
index d82b17c..a14cba3 100644
--- a/maple/maple_host_command_writer.hpp
+++ b/maple/maple_host_command_writer.hpp
@@ -12,14 +12,15 @@ namespace maple {
 
 template <uint32_t base_address = 0>
 struct host_command_writer {
-  uint32_t * const send_buf;
-  uint32_t * const recv_buf;
+  uint8_t * const send_buf;
+  uint8_t * const recv_buf;
   uint32_t send_offset;
   uint32_t recv_offset;
+  uint32_t last_send_offset;
 
-  constexpr host_command_writer(uint32_t * const send_buf,
-				uint32_t * const recv_buf)
-    : send_buf(send_buf), recv_buf(recv_buf), send_offset(0), recv_offset(0)
+  constexpr host_command_writer(uint8_t * const send_buf,
+				uint8_t * const recv_buf)
+    : send_buf(send_buf), recv_buf(recv_buf), send_offset(0), recv_offset(0), last_send_offset(0)
   { }
 
   template <typename C, typename R>
@@ -38,8 +39,8 @@ struct host_command_writer {
     static_assert((sizeof (command_type)) % 4 == 0);
     static_assert((sizeof (response_type)) % 4 == 0);
 
-    auto host_command = reinterpret_cast<command_type *>(&send_buf[send_offset / 4]);
-    auto host_response = reinterpret_cast<response_type *>(&recv_buf[recv_offset / 4]);
+    auto host_command = reinterpret_cast<command_type *>(&send_buf[send_offset]);
+    auto host_response = reinterpret_cast<response_type *>(&recv_buf[recv_offset]);
 
     host_command->host_instruction = (end_flag ? host_instruction::end_flag : 0)
                                    | (host_port_select & host_instruction::port_select::bit_mask)
@@ -59,6 +60,7 @@ struct host_command_writer {
     host_command->bus_data.source_ap = destination_ap & ap::port_select::bit_mask;
     host_command->bus_data.data_size = data_size / 4;
 
+    last_send_offset = send_offset;
     send_offset += (sizeof (command_type)) + send_trailing;
     recv_offset += (sizeof (response_type)) + recv_trailing;
 
@@ -76,6 +78,22 @@ struct host_command_writer {
     append_command<C, R>(host_instruction::port_select::d, ap::de::device | ap::port_select::d, true);
     return ret;
   }
+
+  void set_end_flag()
+  {
+    using host_command_type = maple::host_command<uint8_t[0]>;
+    auto host_command = reinterpret_cast<host_command_type *>(&send_buf[last_send_offset]);
+    host_command->host_instruction |= host_instruction::end_flag;
+  }
+
+  uint32_t reset()
+  {
+    const uint32_t old_recv_offset = recv_offset;
+    // reset writer
+    send_offset = 0;
+    recv_offset = 0;
+    return old_recv_offset;
+  }
 };
 
 }
diff --git a/regs/gen/core_bits.py b/regs/gen/core_bits.py
index 3861916..939caca 100644
--- a/regs/gen/core_bits.py
+++ b/regs/gen/core_bits.py
@@ -15,22 +15,26 @@ def aggregate_registers(d):
     return dict(aggregated)
 
 def parse_bit_number(s):
-    assert '-' not in s
+    assert '-' not in s, s
+    assert ',' not in s, s
     return int(s, 10)
 
-def parse_bit_set(s, split_char):
-    assert len(list(c for c in s if c == split_char)) == 1
-    left, right = map(parse_bit_number, s.split(split_char, maxsplit=1))
-    assert left > right, (left, right)
-    return left, right
+def parse_bit_set(s, split_char, maxsplit):
+    #assert len(list(c for c in s if c == split_char)) == 1, s
+    split = list(map(parse_bit_number, s.split(split_char, maxsplit=maxsplit)))
+    for i in range(len(split) - 1):
+        left = split[i]
+        right = split[i+1]
+        assert left > right, (left, right)
+    return split
 
 def parse_bit_range(s):
     if '-' in s:
-        left, right = parse_bit_set(s, '-')
+        left, right = parse_bit_set(s, '-', 1)
         return set(range(right, left+1))
     elif ',' in s:
-        left, right = parse_bit_set(s, ',')
-        return set([right, left])
+        bits = parse_bit_set(s, ',', -1)
+        return set(bits)
     else:
         num = parse_bit_number(s)
         return set([num])
@@ -124,8 +128,10 @@ def aggregate_all_enums(aggregated):
 '''
 
 def mask_from_bits(bits):
-    h, l = max(bits), min(bits)
-    mask = 2 ** ((h - l) + 1) - 1
+    mask = 0
+    for b in bits:
+        mask |= 1 << b
+    mask >>= min(bits)
     return mask
 
 def parse_value(value):
diff --git a/regs/sh7091_bits.csv b/regs/sh7091_bits.csv
index db82ffd..59efd22 100644
--- a/regs/sh7091_bits.csv
+++ b/regs/sh7091_bits.csv
@@ -293,3 +293,74 @@
 "SCIF","SCSPTR2","SPB2DT","0","input_output_data_is_high_level","1",,
 ,,,,,,,
 "SCIF","SCLSR2","ORER","0","overrun_error_occured","1",,
+,,,,,,,
+"SH","SR",,"30","md","1",,
+"SH","SR",,"29","rb","1",,
+"SH","SR",,"28","bl","1",,
+"SH","SR",,"15","fd","1",,
+"SH","SR",,"9","m","1",,
+"SH","SR",,"8","q","1",,
+"SH","SR",,"7-4","imask",,"0b1111",
+"SH","SR",,"1","s","1",,
+"SH","SR",,"0","t","1",,
+,,,,,,,
+"SH","FPSCR",,"21","fr","1",,
+"SH","FPSCR",,"20","sz","1",,
+"SH","FPSCR",,"19","pr","1",,
+"SH","FPSCR",,"18","dn","1",,
+"SH","FPSCR","CAUSE","17-12","fpu_error","0b100000",,
+"SH","FPSCR","CAUSE","17-12","invalid_operation","0b010000",,
+"SH","FPSCR","CAUSE","17-12","division_by_zero","0b001000",,
+"SH","FPSCR","CAUSE","17-12","overflow","0b000100",,
+"SH","FPSCR","CAUSE","17-12","underflow","0b000010",,
+"SH","FPSCR","CAUSE","17-12","inexact","0b000001",,
+"SH","FPSCR","ENABLED","11-7","invalid_operation","0b10000",,
+"SH","FPSCR","ENABLED","11-7","division_by_zero","0b01000",,
+"SH","FPSCR","ENABLED","11-7","overflow","0b00100",,
+"SH","FPSCR","ENABLED","11-7","underflow","0b00010",,
+"SH","FPSCR","ENABLED","11-7","inexact","0b00001",,
+"SH","FPSCR","FLAG","6-2","invalid_operation","0b10000",,
+"SH","FPSCR","FLAG","6-2","division_by_zero","0b01000",,
+"SH","FPSCR","FLAG","6-2","overflow","0b00100",,
+"SH","FPSCR","FLAG","6-2","underflow","0b00010",,
+"SH","FPSCR","FLAG","6-2","inexact","0b00001",,
+"SH","FPSCR","RM","1-0","round_to_nearest","0b00",,
+"SH","FPSCR","RM","1-0","round_to_zero","0b01",,
+,,,,,,,
+"UBC","BAMRA","BAMA","3,1,0","all_bara_bits_are_included_in_break_conditions","0b0000",,
+"UBC","BAMRA","BAMA","3,1,0","lower_10_bits_of_bara_are_not_included_in_break_conditions","0b0001",,
+"UBC","BAMRA","BAMA","3,1,0","lower_12_bits_of_bara_are_not_included_in_break_conditions","0b0010",,
+"UBC","BAMRA","BAMA","3,1,0","all_bara_bits_are_not_included_in_break_conditions","0b0011",,
+"UBC","BAMRA","BAMA","3,1,0","lower_16_bits_of_bara_are_not_included_in_break_conditions","0b1000",,
+"UBC","BAMRA","BAMA","3,1,0","lower_20_bits_of_bara_are_not_included_in_break_conditions","0b1001",,
+"UBC","BAMRA","BASMA","2","all_basra_bits_are_included_in_break_conditions","0",,
+"UBC","BAMRA","BASMA","2","no_basra_bits_are_included_in_break_conditions","1",,
+,,,,,,,
+"UBC","BBRA","SZA","6,1,0","operand_size_is_not_included_in_break_conditions","0b00",,
+"UBC","BBRA","SZA","6,1,0","byte_access_is_used_as_break_condition","0b01",,
+"UBC","BBRA","SZA","6,1,0","word_access_is_used_as_break_condition","0b10",,
+"UBC","BBRA","SZA","6,1,0","longword_access_is_used_as_break_condition","0b11",,
+"UBC","BBRA","SZA","6,1,0","quadword_access_is_used_as_break_condition","0b1000000",,
+"UBC","BBRA","IDA","5-4","condition_comparison_is_not_performed","0b00",,
+"UBC","BBRA","IDA","5-4","instruction_access_cycle_is_used_as_break_condition","0b01",,
+"UBC","BBRA","IDA","5-4","operand_access_cycle_is_used_as_break_condition","0b10",,
+"UBC","BBRA","IDA","5-4","instruction_access_cycle_or_operand_access_cycle_is_used_as_break_condition","0b11",,
+"UBC","BBRA","RWA","3-2","condition_comparison_is_not_performed","0b00",,
+"UBC","BBRA","RWA","3-2","read_cycle_is_used_as_break_condition","0b01",,
+"UBC","BBRA","RWA","3-2","write_cycle_is_used_as_break_condition","0b10",,
+"UBC","BBRA","RWA","3-2","read_cycle_or_write_cycle_is_used_as_break_condition","0b11",,
+,,,,,,,
+"UBC","BRCR","CMFA","15","channel_a_break_condition_is_not_matched","0",,
+"UBC","BRCR","CMFA","15","channel_a_break_condition_match_has_occured","1",,
+"UBC","BRCR","CMFB","14","channel_b_break_condition_is_not_matched","0",,
+"UBC","BRCR","CMFB","14","channel_b_break_condition_match_has_occured","1",,
+"UBC","BRCR","PCBA","10","channel_a_pc_break_is_effected_before_instruction_execution","0",,
+"UBC","BRCR","PCBA","10","channel_a_pc_break_is_effected_after_instruction_execution","1",,
+"UBC","BRCR","DBEB","7","data_bus_condition_is_not_included_in_channel_b_conditions","0",,
+"UBC","BRCR","DBEB","7","data_bus_condition_is_included_in_channel_b_conditions","1",,
+"UBC","BRCR","PCBB","6","channel_b_pc_break_is_effected_before_instruction_execution","0",,
+"UBC","BRCR","PCBB","6","channel_b_pc_break_is_effected_after_instruction_execution","1",,
+"UBC","BRCR","SEQ","3","channel_a_and_b_comparison_are_performed_as_independent_condition","0",,
+"UBC","BRCR","SEQ","3","channel_a_and_b_comparison_are_performed_as_sequential_condition","1",,
+"UBC","BRCR","UBDE","0","user_break_debug_function_is_not_used","0",,
+"UBC","BRCR","UBDE","0","user_break_debug_function_is_used","1",,
diff --git a/regs/sh7091_bits.ods b/regs/sh7091_bits.ods
index e15da92..5956d1e 100644
Binary files a/regs/sh7091_bits.ods and b/regs/sh7091_bits.ods differ
diff --git a/serial_load.cpp b/serial_load.cpp
index c0849c1..d29c181 100644
--- a/serial_load.cpp
+++ b/serial_load.cpp
@@ -72,7 +72,6 @@ static void poststart_read()
 static void prestart_maple_raw__command()
 {
   uint32_t dest = reinterpret_cast<uint32_t>(&__send_buf);
-  //uint32_t dest = 0xac000020;
   uint32_t size = state.buf.arg[0];
   serial::recv_dma(dest - 1, size + 1);
   state.reply_crc.value = 0xffffffff;
@@ -82,7 +81,6 @@ static void prestart_maple_raw__command()
 static void prestart_maple_raw__response()
 {
   uint32_t src = reinterpret_cast<uint32_t>(&__recv_buf);
-  //uint32_t src = 0xac002020;
   uint32_t size = state.buf.arg[1];
   serial::send_dma(src, size);
   state.reply_crc.value = 0xffffffff;
diff --git a/sh7091/sh7091_bits.hpp b/sh7091/sh7091_bits.hpp
index 2a931d9..bac8ffd 100644
--- a/sh7091/sh7091_bits.hpp
+++ b/sh7091/sh7091_bits.hpp
@@ -3,826 +3,1394 @@
 #include <cstdint>
 
 namespace ccn {
-  namespace pteh {
-    constexpr uint32_t VPN(uint32_t reg) { return (reg >> 10) & 0x3fffff; }
-    constexpr uint32_t ASID(uint32_t reg) { return (reg >> 0) & 0xff; }
-  }
+namespace pteh {
+constexpr uint32_t VPN(uint32_t reg) { return (reg >> 10) & 0x3fffff; }
+constexpr uint32_t ASID(uint32_t reg) { return (reg >> 0) & 0xff; }
+}
 
-  namespace ptel {
-    constexpr uint32_t PPN(uint32_t reg) { return (reg >> 10) & 0x7ffff; }
+namespace ptel {
+constexpr uint32_t PPN(uint32_t reg) { return (reg >> 10) & 0x7ffff; }
 
-    namespace v {
-      constexpr uint32_t invalid = 0 << 8;
-      constexpr uint32_t valid = 1 << 8;
+namespace v {
+constexpr uint32_t invalid = 0 << 8;
 
-      constexpr uint32_t bit_mask = 0x1 << 8;
-    }
+constexpr uint32_t valid = 1 << 8;
 
-    namespace sz {
-      constexpr uint32_t _1_kbyte_page = 0b0000 << 4;
-      constexpr uint32_t _4_kbyte_page = 0b0001 << 4;
-      constexpr uint32_t _64_kbyte_page = 0b1000 << 4;
-      constexpr uint32_t _1_mbyte_page = 0b1001 << 4;
 
-      constexpr uint32_t bit_mask = 0xf << 4;
-    }
+constexpr uint32_t bit_mask = 0x1 << 8;
 
-    namespace pr {
-      constexpr uint32_t read_only_in_privileged_mode = 0b00 << 5;
-      constexpr uint32_t read_write_in_privileged_mode = 0b01 << 5;
-      constexpr uint32_t read_only_in_privileged_and_user_mode = 0b10 << 5;
-      constexpr uint32_t read_write_in_privileged_and_user_mode = 0b11 << 5;
+}
 
-      constexpr uint32_t bit_mask = 0x3 << 5;
-    }
+namespace sz {
+constexpr uint32_t _1_kbyte_page = 0b0000 << 4;
 
-    namespace c {
-      constexpr uint32_t not_cacheable = 0 << 3;
-      constexpr uint32_t cacheable = 1 << 3;
+constexpr uint32_t _4_kbyte_page = 0b0001 << 4;
 
-      constexpr uint32_t bit_mask = 0x1 << 3;
-    }
+constexpr uint32_t _64_kbyte_page = 0b1000 << 4;
 
-    namespace d {
-      constexpr uint32_t write_has_not_been_performed = 0 << 2;
-      constexpr uint32_t write_has_been_performed = 1 << 2;
+constexpr uint32_t _1_mbyte_page = 0b1001 << 4;
 
-      constexpr uint32_t bit_mask = 0x1 << 2;
-    }
 
-    namespace sh {
-      constexpr uint32_t pages_are_shared_by_processes = 0 << 1;
-      constexpr uint32_t pages_are_not_shared_by_processes = 1 << 1;
+constexpr uint32_t bit_mask = 0x9 << 4;
 
-      constexpr uint32_t bit_mask = 0x1 << 1;
-    }
+}
 
-    namespace wt {
-      constexpr uint32_t copy_back_mode = 0 << 0;
-      constexpr uint32_t write_through_mode = 1 << 0;
+namespace pr {
+constexpr uint32_t read_only_in_privileged_mode = 0b00 << 5;
 
-      constexpr uint32_t bit_mask = 0x1 << 0;
-    }
-  }
+constexpr uint32_t read_write_in_privileged_mode = 0b01 << 5;
 
-  namespace mmucr {
-    constexpr uint32_t LRUI(uint32_t reg) { return (reg >> 26) & 0x3f; }
-    constexpr uint32_t URB(uint32_t reg) { return (reg >> 18) & 0x3f; }
-    constexpr uint32_t URC(uint32_t reg) { return (reg >> 10) & 0x3f; }
+constexpr uint32_t read_only_in_privileged_and_user_mode = 0b10 << 5;
 
-    namespace sqmd {
-      constexpr uint32_t user_privileged_access_possible = 0 << 9;
-      constexpr uint32_t privileged_access_possible = 1 << 9;
+constexpr uint32_t read_write_in_privileged_and_user_mode = 0b11 << 5;
 
-      constexpr uint32_t bit_mask = 0x1 << 9;
-    }
 
-    namespace sv {
-      constexpr uint32_t multiple_virtual_memory_mode = 0 << 8;
-      constexpr uint32_t single_virtual_memory_mode = 1 << 8;
+constexpr uint32_t bit_mask = 0x3 << 5;
 
-      constexpr uint32_t bit_mask = 0x1 << 8;
-    }
+}
 
-    namespace ti {
-      constexpr uint32_t invalidate_all_utlb_itlb_bits = 1 << 2;
+namespace c {
+constexpr uint32_t not_cacheable = 0 << 3;
 
-      constexpr uint32_t bit_mask = 0x1 << 2;
-    }
+constexpr uint32_t cacheable = 1 << 3;
 
-    namespace at {
-      constexpr uint32_t mmu_disabled = 0 << 0;
-      constexpr uint32_t mmu_enabled = 1 << 0;
 
-      constexpr uint32_t bit_mask = 0x1 << 0;
-    }
-  }
+constexpr uint32_t bit_mask = 0x1 << 3;
 
-  namespace basra {
-    constexpr uint32_t basa(uint32_t num) { return (num & 0xff) << 0; }
-  }
+}
 
-  namespace basrb {
-    constexpr uint32_t basa(uint32_t num) { return (num & 0xff) << 0; }
-  }
+namespace d {
+constexpr uint32_t write_has_not_been_performed = 0 << 2;
 
-  namespace ccr {
-    namespace iix {
-      constexpr uint32_t address_bits_12_5_used_for_ic_entry_selection = 0 << 15;
-      constexpr uint32_t address_bits_25_and_11_5_used_for_ic_entry_selection = 1 << 15;
+constexpr uint32_t write_has_been_performed = 1 << 2;
 
-      constexpr uint32_t bit_mask = 0x1 << 15;
-    }
 
-    namespace ici {
-      constexpr uint32_t clear_v_bits_of_all_ic_entries = 1 << 11;
+constexpr uint32_t bit_mask = 0x1 << 2;
 
-      constexpr uint32_t bit_mask = 0x1 << 11;
-    }
+}
 
-    namespace ice {
-      constexpr uint32_t ic_not_used = 0 << 8;
-      constexpr uint32_t ic_used = 1 << 8;
+namespace sh {
+constexpr uint32_t pages_are_shared_by_processes = 0 << 1;
 
-      constexpr uint32_t bit_mask = 0x1 << 8;
-    }
+constexpr uint32_t pages_are_not_shared_by_processes = 1 << 1;
 
-    namespace oix {
-      constexpr uint32_t address_bits_13_5_used_for_oc_entry_selection = 0 << 7;
-      constexpr uint32_t address_bits_25_and_12_5_used_for_oc_entry_selection = 1 << 7;
 
-      constexpr uint32_t bit_mask = 0x1 << 7;
-    }
+constexpr uint32_t bit_mask = 0x1 << 1;
 
-    namespace ora {
-      constexpr uint32_t _16_kbytes_used_as_cache = 0 << 5;
-      constexpr uint32_t _8_kbytes_used_as_cache_8_kbytes_used_as_ram = 1 << 5;
+}
 
-      constexpr uint32_t bit_mask = 0x1 << 5;
-    }
+namespace wt {
+constexpr uint32_t copy_back_mode = 0 << 0;
 
-    namespace oci {
-      constexpr uint32_t clear_v_and_u_bits_of_all_oc_entries = 1 << 3;
+constexpr uint32_t write_through_mode = 1 << 0;
 
-      constexpr uint32_t bit_mask = 0x1 << 3;
-    }
 
-    namespace cb {
-      constexpr uint32_t write_through_mode = 0 << 2;
-      constexpr uint32_t copy_back_mode = 1 << 2;
+constexpr uint32_t bit_mask = 0x1 << 0;
 
-      constexpr uint32_t bit_mask = 0x1 << 2;
-    }
+}
+}
 
-    namespace wt {
-      constexpr uint32_t copy_back_mode = 0 << 1;
-      constexpr uint32_t write_through_mode = 1 << 1;
+namespace mmucr {
+constexpr uint32_t LRUI(uint32_t reg) { return (reg >> 26) & 0x3f; }
+constexpr uint32_t URB(uint32_t reg) { return (reg >> 18) & 0x3f; }
+constexpr uint32_t URC(uint32_t reg) { return (reg >> 10) & 0x3f; }
 
-      constexpr uint32_t bit_mask = 0x1 << 1;
-    }
+namespace sqmd {
+constexpr uint32_t user_privileged_access_possible = 0 << 9;
 
-    namespace oce {
-      constexpr uint32_t oc_not_used = 0 << 0;
-      constexpr uint32_t oc_used = 1 << 0;
+constexpr uint32_t privileged_access_possible = 1 << 9;
 
-      constexpr uint32_t bit_mask = 0x1 << 0;
-    }
-  }
 
-  namespace tra {
-    constexpr uint32_t imm(uint32_t reg) { return (reg >> 2) & 0xff; }
-  }
+constexpr uint32_t bit_mask = 0x1 << 9;
 
-  namespace expevt {
-    constexpr uint32_t exception_code(uint32_t reg) { return (reg >> 0) & 0xfff; }
-  }
+}
 
-  namespace intevt {
-    constexpr uint32_t exception_code(uint32_t reg) { return (reg >> 0) & 0xfff; }
-  }
+namespace sv {
+constexpr uint32_t multiple_virtual_memory_mode = 0 << 8;
 
-  namespace ptea {
-    namespace tc {
-      constexpr uint32_t area_5_is_used = 0 << 3;
-      constexpr uint32_t area_6_is_used = 1 << 3;
+constexpr uint32_t single_virtual_memory_mode = 1 << 8;
 
-      constexpr uint32_t bit_mask = 0x1 << 3;
-    }
 
-    namespace sa {
-      constexpr uint32_t undefined = 0b000 << 0;
-      constexpr uint32_t variable_size_io_space = 0b001 << 0;
-      constexpr uint32_t _8_bit_io_space = 0b010 << 0;
-      constexpr uint32_t _16_bit_io_space = 0b011 << 0;
-      constexpr uint32_t _8_bit_common_memory_space = 0b100 << 0;
-      constexpr uint32_t _16_bit_common_memory_space = 0b101 << 0;
-      constexpr uint32_t _8_bit_attribute_memory_space = 0b110 << 0;
-      constexpr uint32_t _16_bit_attribute_memory_space = 0b111 << 0;
+constexpr uint32_t bit_mask = 0x1 << 8;
 
-      constexpr uint32_t bit_mask = 0x7 << 0;
-    }
-  }
+}
 
-  namespace qacr0 {
-    constexpr uint32_t area(uint32_t num) { return (num & 0x7) << 2; }
-  }
+namespace ti {
+constexpr uint32_t invalidate_all_utlb_itlb_bits = 1 << 2;
 
-  namespace qacr1 {
-    constexpr uint32_t area(uint32_t num) { return (num & 0x7) << 2; }
-  }
+
+constexpr uint32_t bit_mask = 0x1 << 2;
+
+}
+
+namespace at {
+constexpr uint32_t mmu_disabled = 0 << 0;
+
+constexpr uint32_t mmu_enabled = 1 << 0;
+
+
+constexpr uint32_t bit_mask = 0x1 << 0;
+
+}
+}
+
+namespace basra {
+constexpr uint32_t basa(uint32_t num) { return (num & 0xff) << 0; }
+}
+
+namespace basrb {
+constexpr uint32_t basa(uint32_t num) { return (num & 0xff) << 0; }
+}
+
+namespace ccr {
+namespace iix {
+constexpr uint32_t address_bits_12_5_used_for_ic_entry_selection = 0 << 15;
+
+constexpr uint32_t address_bits_25_and_11_5_used_for_ic_entry_selection = 1 << 15;
+
+
+constexpr uint32_t bit_mask = 0x1 << 15;
+
+}
+
+namespace ici {
+constexpr uint32_t clear_v_bits_of_all_ic_entries = 1 << 11;
+
+
+constexpr uint32_t bit_mask = 0x1 << 11;
+
+}
+
+namespace ice {
+constexpr uint32_t ic_not_used = 0 << 8;
+
+constexpr uint32_t ic_used = 1 << 8;
+
+
+constexpr uint32_t bit_mask = 0x1 << 8;
+
+}
+
+namespace oix {
+constexpr uint32_t address_bits_13_5_used_for_oc_entry_selection = 0 << 7;
+
+constexpr uint32_t address_bits_25_and_12_5_used_for_oc_entry_selection = 1 << 7;
+
+
+constexpr uint32_t bit_mask = 0x1 << 7;
+
+}
+
+namespace ora {
+constexpr uint32_t _16_kbytes_used_as_cache = 0 << 5;
+
+constexpr uint32_t _8_kbytes_used_as_cache_8_kbytes_used_as_ram = 1 << 5;
+
+
+constexpr uint32_t bit_mask = 0x1 << 5;
+
+}
+
+namespace oci {
+constexpr uint32_t clear_v_and_u_bits_of_all_oc_entries = 1 << 3;
+
+
+constexpr uint32_t bit_mask = 0x1 << 3;
+
+}
+
+namespace cb {
+constexpr uint32_t write_through_mode = 0 << 2;
+
+constexpr uint32_t copy_back_mode = 1 << 2;
+
+
+constexpr uint32_t bit_mask = 0x1 << 2;
+
+}
+
+namespace wt {
+constexpr uint32_t copy_back_mode = 0 << 1;
+
+constexpr uint32_t write_through_mode = 1 << 1;
+
+
+constexpr uint32_t bit_mask = 0x1 << 1;
+
+}
+
+namespace oce {
+constexpr uint32_t oc_not_used = 0 << 0;
+
+constexpr uint32_t oc_used = 1 << 0;
+
+
+constexpr uint32_t bit_mask = 0x1 << 0;
+
+}
+}
+
+namespace tra {
+constexpr uint32_t imm(uint32_t reg) { return (reg >> 2) & 0xff; }
+}
+
+namespace expevt {
+constexpr uint32_t exception_code(uint32_t reg) { return (reg >> 0) & 0xfff; }
+}
+
+namespace intevt {
+constexpr uint32_t exception_code(uint32_t reg) { return (reg >> 0) & 0xfff; }
+}
+
+namespace ptea {
+namespace tc {
+constexpr uint32_t area_5_is_used = 0 << 3;
+
+constexpr uint32_t area_6_is_used = 1 << 3;
+
+
+constexpr uint32_t bit_mask = 0x1 << 3;
+
+}
+
+namespace sa {
+constexpr uint32_t undefined = 0b000 << 0;
+
+constexpr uint32_t variable_size_io_space = 0b001 << 0;
+
+constexpr uint32_t _8_bit_io_space = 0b010 << 0;
+
+constexpr uint32_t _16_bit_io_space = 0b011 << 0;
+
+constexpr uint32_t _8_bit_common_memory_space = 0b100 << 0;
+
+constexpr uint32_t _16_bit_common_memory_space = 0b101 << 0;
+
+constexpr uint32_t _8_bit_attribute_memory_space = 0b110 << 0;
+
+constexpr uint32_t _16_bit_attribute_memory_space = 0b111 << 0;
+
+
+constexpr uint32_t bit_mask = 0x7 << 0;
+
+}
+}
+
+namespace qacr0 {
+constexpr uint32_t area(uint32_t num) { return (num & 0x7) << 2; }
+}
+
+namespace qacr1 {
+constexpr uint32_t area(uint32_t num) { return (num & 0x7) << 2; }
+}
 
 }
 
 namespace dmac {
-  namespace dmatcr {
-    constexpr uint32_t transfer_count(uint32_t num) { return (num & 0xffffff) << 0; }
-  }
+namespace dmatcr {
+constexpr uint32_t transfer_count(uint32_t num) { return (num & 0xffffff) << 0; }
+}
 
-  namespace chcr {
-    namespace ssa {
-      constexpr uint32_t reserved_in_pcmcia_access = 0b000 << 29;
-      constexpr uint32_t dynamic_bus_sizing_io_space = 0b001 << 29;
-      constexpr uint32_t _8_bit_io_space = 0b010 << 29;
-      constexpr uint32_t _16_bit_io_space = 0b011 << 29;
-      constexpr uint32_t _8_bit_common_memory_space = 0b100 << 29;
-      constexpr uint32_t _16_bit_common_memory_space = 0b101 << 29;
-      constexpr uint32_t _8_bit_attribute_memory_space = 0b110 << 29;
-      constexpr uint32_t _16_bit_attribute_memory_space = 0b111 << 29;
+namespace chcr {
+namespace ssa {
+constexpr uint32_t reserved_in_pcmcia_access = 0b000 << 29;
 
-      constexpr uint32_t bit_mask = 0x7 << 29;
-    }
+constexpr uint32_t dynamic_bus_sizing_io_space = 0b001 << 29;
 
-    namespace stc {
-      constexpr uint32_t c5_space_wait_cycle_selection = 0 << 28;
-      constexpr uint32_t c6_space_wait_cycle_selection = 1 << 28;
+constexpr uint32_t _8_bit_io_space = 0b010 << 29;
 
-      constexpr uint32_t bit_mask = 0x1 << 28;
-    }
+constexpr uint32_t _16_bit_io_space = 0b011 << 29;
 
-    namespace dsa {
-      constexpr uint32_t reserved_in_pcmcia_access = 0b000 << 25;
-      constexpr uint32_t dynamic_bus_sizing_io_space = 0b001 << 25;
-      constexpr uint32_t _8_bit_io_space = 0b010 << 25;
-      constexpr uint32_t _16_bit_io_space = 0b011 << 25;
-      constexpr uint32_t _8_bit_common_memory_space = 0b100 << 25;
-      constexpr uint32_t _16_bit_common_memory_space = 0b101 << 25;
-      constexpr uint32_t _8_bit_attribute_memory_space = 0b110 << 25;
-      constexpr uint32_t _16_bit_attribute_memory_space = 0b111 << 25;
+constexpr uint32_t _8_bit_common_memory_space = 0b100 << 29;
 
-      constexpr uint32_t bit_mask = 0x7 << 25;
-    }
+constexpr uint32_t _16_bit_common_memory_space = 0b101 << 29;
 
-    namespace dtc {
-      constexpr uint32_t c5_space_wait_cycle_selection = 0 << 24;
-      constexpr uint32_t c6_space_wait_cycle_selection = 1 << 24;
+constexpr uint32_t _8_bit_attribute_memory_space = 0b110 << 29;
 
-      constexpr uint32_t bit_mask = 0x1 << 24;
-    }
+constexpr uint32_t _16_bit_attribute_memory_space = 0b111 << 29;
 
-    namespace ds {
-      constexpr uint32_t low_level_detection = 0 << 19;
-      constexpr uint32_t falling_edge_detection = 1 << 19;
 
-      constexpr uint32_t bit_mask = 0x1 << 19;
-    }
+constexpr uint32_t bit_mask = 0x7 << 29;
 
-    namespace rl {
-      constexpr uint32_t drak_is_an_active_high = 0 << 18;
-      constexpr uint32_t drak_is_an_active_low = 1 << 18;
+}
 
-      constexpr uint32_t bit_mask = 0x1 << 18;
-    }
+namespace stc {
+constexpr uint32_t c5_space_wait_cycle_selection = 0 << 28;
 
-    namespace am {
-      constexpr uint32_t dack_is_output_in_read_cycle = 0 << 17;
-      constexpr uint32_t dack_is_output_in_write_cycle = 1 << 17;
+constexpr uint32_t c6_space_wait_cycle_selection = 1 << 28;
 
-      constexpr uint32_t bit_mask = 0x1 << 17;
-    }
 
-    namespace al {
-      constexpr uint32_t active_high_output = 0 << 16;
-      constexpr uint32_t active_low_output = 1 << 16;
+constexpr uint32_t bit_mask = 0x1 << 28;
 
-      constexpr uint32_t bit_mask = 0x1 << 16;
-    }
+}
 
-    namespace dm {
-      constexpr uint32_t destination_address_fixed = 0b00 << 14;
-      constexpr uint32_t destination_address_incremented = 0b01 << 14;
-      constexpr uint32_t destination_address_decremented = 0b10 << 14;
+namespace dsa {
+constexpr uint32_t reserved_in_pcmcia_access = 0b000 << 25;
 
-      constexpr uint32_t bit_mask = 0x3 << 14;
-    }
+constexpr uint32_t dynamic_bus_sizing_io_space = 0b001 << 25;
 
-    namespace sm {
-      constexpr uint32_t source_address_fixed = 0b00 << 12;
-      constexpr uint32_t source_address_incremented = 0b01 << 12;
-      constexpr uint32_t source_address_decremented = 0b10 << 12;
+constexpr uint32_t _8_bit_io_space = 0b010 << 25;
 
-      constexpr uint32_t bit_mask = 0x3 << 12;
-    }
+constexpr uint32_t _16_bit_io_space = 0b011 << 25;
 
-    namespace rs {
-      constexpr uint32_t resource_select(uint32_t num) { return (num & 0xf) << 8; }
+constexpr uint32_t _8_bit_common_memory_space = 0b100 << 25;
 
-      constexpr uint32_t bit_mask = 0xf << 8;
-    }
+constexpr uint32_t _16_bit_common_memory_space = 0b101 << 25;
 
-    namespace tm {
-      constexpr uint32_t cycle_steal_mode = 0 << 7;
-      constexpr uint32_t cycle_burst_mode = 1 << 7;
+constexpr uint32_t _8_bit_attribute_memory_space = 0b110 << 25;
 
-      constexpr uint32_t bit_mask = 0x1 << 7;
-    }
+constexpr uint32_t _16_bit_attribute_memory_space = 0b111 << 25;
 
-    namespace ts {
-      constexpr uint32_t _64_bit = 0b000 << 4;
-      constexpr uint32_t _8_bit = 0b001 << 4;
-      constexpr uint32_t _16_bit = 0b010 << 4;
-      constexpr uint32_t _32_bit = 0b011 << 4;
-      constexpr uint32_t _32_byte = 0b100 << 4;
 
-      constexpr uint32_t bit_mask = 0x7 << 4;
-    }
+constexpr uint32_t bit_mask = 0x7 << 25;
 
-    namespace ie {
-      constexpr uint32_t interrupt_request_not_generated = 0 << 2;
-      constexpr uint32_t interrupt_request_generated = 1 << 2;
+}
 
-      constexpr uint32_t bit_mask = 0x1 << 2;
-    }
+namespace dtc {
+constexpr uint32_t c5_space_wait_cycle_selection = 0 << 24;
 
-    namespace te {
-      constexpr uint32_t transfers_not_completed = 0 << 1;
-      constexpr uint32_t transfers_completed = 1 << 1;
+constexpr uint32_t c6_space_wait_cycle_selection = 1 << 24;
 
-      constexpr uint32_t bit_mask = 0x1 << 1;
-    }
 
-    namespace de {
-      constexpr uint32_t channel_operation_disabled = 0 << 0;
-      constexpr uint32_t channel_operation_enabled = 1 << 0;
+constexpr uint32_t bit_mask = 0x1 << 24;
 
-      constexpr uint32_t bit_mask = 0x1 << 0;
-    }
-  }
+}
 
-  namespace dmaor {
-    namespace ddt {
-      constexpr uint32_t normal_dma_mode = 0 << 15;
-      constexpr uint32_t on_demand_data_transfer_mode = 1 << 15;
+namespace ds {
+constexpr uint32_t low_level_detection = 0 << 19;
 
-      constexpr uint32_t bit_mask = 0x1 << 15;
-    }
+constexpr uint32_t falling_edge_detection = 1 << 19;
 
-    namespace pr {
-      constexpr uint32_t ch0_ch1_ch2_ch3 = 0b00 << 8;
-      constexpr uint32_t ch0_ch2_ch3_ch1 = 0b01 << 8;
-      constexpr uint32_t ch2_ch0_ch1_ch3 = 0b10 << 8;
-      constexpr uint32_t round_robin = 0b11 << 8;
 
-      constexpr uint32_t bit_mask = 0x3 << 8;
-    }
+constexpr uint32_t bit_mask = 0x1 << 19;
 
-    namespace ae {
-      constexpr uint32_t no_address_error__dma_transfer_enabled = 0 << 2;
-      constexpr uint32_t address_error__dma_transfer_disabled = 1 << 2;
+}
 
-      constexpr uint32_t bit_mask = 0x1 << 2;
-    }
+namespace rl {
+constexpr uint32_t drak_is_an_active_high = 0 << 18;
 
-    namespace nmif {
-      constexpr uint32_t no_nmi__dma_transfer_enabled = 0 << 1;
-      constexpr uint32_t nmi__dma_transfer_disabled = 1 << 1;
+constexpr uint32_t drak_is_an_active_low = 1 << 18;
 
-      constexpr uint32_t bit_mask = 0x1 << 1;
-    }
 
-    namespace dme {
-      constexpr uint32_t operation_disabled_on_all_channels = 0 << 0;
-      constexpr uint32_t operation_enabled_on_all_channels = 1 << 0;
+constexpr uint32_t bit_mask = 0x1 << 18;
 
-      constexpr uint32_t bit_mask = 0x1 << 0;
-    }
-  }
+}
+
+namespace am {
+constexpr uint32_t dack_is_output_in_read_cycle = 0 << 17;
+
+constexpr uint32_t dack_is_output_in_write_cycle = 1 << 17;
+
+
+constexpr uint32_t bit_mask = 0x1 << 17;
+
+}
+
+namespace al {
+constexpr uint32_t active_high_output = 0 << 16;
+
+constexpr uint32_t active_low_output = 1 << 16;
+
+
+constexpr uint32_t bit_mask = 0x1 << 16;
+
+}
+
+namespace dm {
+constexpr uint32_t destination_address_fixed = 0b00 << 14;
+
+constexpr uint32_t destination_address_incremented = 0b01 << 14;
+
+constexpr uint32_t destination_address_decremented = 0b10 << 14;
+
+
+constexpr uint32_t bit_mask = 0x3 << 14;
+
+}
+
+namespace sm {
+constexpr uint32_t source_address_fixed = 0b00 << 12;
+
+constexpr uint32_t source_address_incremented = 0b01 << 12;
+
+constexpr uint32_t source_address_decremented = 0b10 << 12;
+
+
+constexpr uint32_t bit_mask = 0x3 << 12;
+
+}
+
+namespace rs {
+constexpr uint32_t resource_select(uint32_t num) { return (num & 0xf) << 8; }
+
+constexpr uint32_t bit_mask = 0xf << 8;
+
+}
+
+namespace tm {
+constexpr uint32_t cycle_steal_mode = 0 << 7;
+
+constexpr uint32_t cycle_burst_mode = 1 << 7;
+
+
+constexpr uint32_t bit_mask = 0x1 << 7;
+
+}
+
+namespace ts {
+constexpr uint32_t _64_bit = 0b000 << 4;
+
+constexpr uint32_t _8_bit = 0b001 << 4;
+
+constexpr uint32_t _16_bit = 0b010 << 4;
+
+constexpr uint32_t _32_bit = 0b011 << 4;
+
+constexpr uint32_t _32_byte = 0b100 << 4;
+
+
+constexpr uint32_t bit_mask = 0x7 << 4;
+
+}
+
+namespace ie {
+constexpr uint32_t interrupt_request_not_generated = 0 << 2;
+
+constexpr uint32_t interrupt_request_generated = 1 << 2;
+
+
+constexpr uint32_t bit_mask = 0x1 << 2;
+
+}
+
+namespace te {
+constexpr uint32_t transfers_not_completed = 0 << 1;
+
+constexpr uint32_t transfers_completed = 1 << 1;
+
+
+constexpr uint32_t bit_mask = 0x1 << 1;
+
+}
+
+namespace de {
+constexpr uint32_t channel_operation_disabled = 0 << 0;
+
+constexpr uint32_t channel_operation_enabled = 1 << 0;
+
+
+constexpr uint32_t bit_mask = 0x1 << 0;
+
+}
+}
+
+namespace dmaor {
+namespace ddt {
+constexpr uint32_t normal_dma_mode = 0 << 15;
+
+constexpr uint32_t on_demand_data_transfer_mode = 1 << 15;
+
+
+constexpr uint32_t bit_mask = 0x1 << 15;
+
+}
+
+namespace pr {
+constexpr uint32_t ch0_ch1_ch2_ch3 = 0b00 << 8;
+
+constexpr uint32_t ch0_ch2_ch3_ch1 = 0b01 << 8;
+
+constexpr uint32_t ch2_ch0_ch1_ch3 = 0b10 << 8;
+
+constexpr uint32_t round_robin = 0b11 << 8;
+
+
+constexpr uint32_t bit_mask = 0x3 << 8;
+
+}
+
+namespace ae {
+constexpr uint32_t no_address_error__dma_transfer_enabled = 0 << 2;
+
+constexpr uint32_t address_error__dma_transfer_disabled = 1 << 2;
+
+
+constexpr uint32_t bit_mask = 0x1 << 2;
+
+}
+
+namespace nmif {
+constexpr uint32_t no_nmi__dma_transfer_enabled = 0 << 1;
+
+constexpr uint32_t nmi__dma_transfer_disabled = 1 << 1;
+
+
+constexpr uint32_t bit_mask = 0x1 << 1;
+
+}
+
+namespace dme {
+constexpr uint32_t operation_disabled_on_all_channels = 0 << 0;
+
+constexpr uint32_t operation_enabled_on_all_channels = 1 << 0;
+
+
+constexpr uint32_t bit_mask = 0x1 << 0;
+
+}
+}
 
 }
 
 namespace intc {
-  namespace icr {
-    namespace nmil {
-      constexpr uint32_t pin_input_level_is_low = 0 << 15;
-      constexpr uint32_t pin_input_level_is_high = 1 << 15;
+namespace icr {
+namespace nmil {
+constexpr uint32_t pin_input_level_is_low = 0 << 15;
 
-      constexpr uint32_t bit_mask = 0x1 << 15;
-    }
+constexpr uint32_t pin_input_level_is_high = 1 << 15;
 
-    namespace mai {
-      constexpr uint32_t interrupts_enabled_while_nmi_pin_is_low = 0 << 14;
-      constexpr uint32_t interrupts_disabled_while_nmi_pin_is_low = 1 << 14;
 
-      constexpr uint32_t bit_mask = 0x1 << 14;
-    }
+constexpr uint32_t bit_mask = 0x1 << 15;
 
-    namespace nmib {
-      constexpr uint32_t interrupt_requests_witheld = 0 << 9;
-      constexpr uint32_t interrupt_requests_detected = 1 << 9;
+}
 
-      constexpr uint32_t bit_mask = 0x1 << 9;
-    }
+namespace mai {
+constexpr uint32_t interrupts_enabled_while_nmi_pin_is_low = 0 << 14;
 
-    namespace nmie {
-      constexpr uint32_t interrupt_on_falling_edge_of_nmi = 0 << 8;
-      constexpr uint32_t interrupt_on_rising_edge_of_nmi = 1 << 8;
+constexpr uint32_t interrupts_disabled_while_nmi_pin_is_low = 1 << 14;
 
-      constexpr uint32_t bit_mask = 0x1 << 8;
-    }
 
-    namespace irlm {
-      constexpr uint32_t level_encoded_interrupt_requests = 0 << 7;
-      constexpr uint32_t independent_interrupt_request = 1 << 7;
+constexpr uint32_t bit_mask = 0x1 << 14;
 
-      constexpr uint32_t bit_mask = 0x1 << 7;
-    }
-  }
+}
 
-  namespace ipra {
-    constexpr uint32_t TMU0(uint32_t num) { return (num & 0xf) << 12; }
-    constexpr uint32_t TMU1(uint32_t num) { return (num & 0xf) << 8; }
-    constexpr uint32_t TMU2(uint32_t num) { return (num & 0xf) << 4; }
-    constexpr uint32_t RTC(uint32_t num) { return (num & 0xf) << 0; }
-  }
+namespace nmib {
+constexpr uint32_t interrupt_requests_witheld = 0 << 9;
 
-  namespace iprb {
-    constexpr uint32_t WDT(uint32_t num) { return (num & 0xf) << 12; }
-    constexpr uint32_t REF(uint32_t num) { return (num & 0xf) << 8; }
-    constexpr uint32_t SCI1(uint32_t num) { return (num & 0xf) << 4; }
-  }
+constexpr uint32_t interrupt_requests_detected = 1 << 9;
 
-  namespace iprc {
-    constexpr uint32_t GPIO(uint32_t num) { return (num & 0xf) << 12; }
-    constexpr uint32_t DMAC(uint32_t num) { return (num & 0xf) << 8; }
-    constexpr uint32_t SCIF(uint32_t num) { return (num & 0xf) << 4; }
-    constexpr uint32_t UDI(uint32_t num) { return (num & 0xf) << 0; }
-  }
+
+constexpr uint32_t bit_mask = 0x1 << 9;
+
+}
+
+namespace nmie {
+constexpr uint32_t interrupt_on_falling_edge_of_nmi = 0 << 8;
+
+constexpr uint32_t interrupt_on_rising_edge_of_nmi = 1 << 8;
+
+
+constexpr uint32_t bit_mask = 0x1 << 8;
+
+}
+
+namespace irlm {
+constexpr uint32_t level_encoded_interrupt_requests = 0 << 7;
+
+constexpr uint32_t independent_interrupt_request = 1 << 7;
+
+
+constexpr uint32_t bit_mask = 0x1 << 7;
+
+}
+}
+
+namespace ipra {
+constexpr uint32_t TMU0(uint32_t num) { return (num & 0xf) << 12; }
+constexpr uint32_t TMU1(uint32_t num) { return (num & 0xf) << 8; }
+constexpr uint32_t TMU2(uint32_t num) { return (num & 0xf) << 4; }
+constexpr uint32_t RTC(uint32_t num) { return (num & 0xf) << 0; }
+}
+
+namespace iprb {
+constexpr uint32_t WDT(uint32_t num) { return (num & 0xf) << 12; }
+constexpr uint32_t REF(uint32_t num) { return (num & 0xf) << 8; }
+constexpr uint32_t SCI1(uint32_t num) { return (num & 0xf) << 4; }
+}
+
+namespace iprc {
+constexpr uint32_t GPIO(uint32_t num) { return (num & 0xf) << 12; }
+constexpr uint32_t DMAC(uint32_t num) { return (num & 0xf) << 8; }
+constexpr uint32_t SCIF(uint32_t num) { return (num & 0xf) << 4; }
+constexpr uint32_t UDI(uint32_t num) { return (num & 0xf) << 0; }
+}
 
 }
 
 namespace tmu {
-  namespace tocr {
-    namespace tcoe {
-      constexpr uint32_t tclk_is_external_clock_or_input_capture = 0 << 0;
-      constexpr uint32_t tclk_is_on_chip_rtc = 1 << 0;
+namespace tocr {
+namespace tcoe {
+constexpr uint32_t tclk_is_external_clock_or_input_capture = 0 << 0;
+constexpr uint32_t tclk_is_on_chip_rtc = 1 << 0;
 
-      constexpr uint32_t bit_mask = 0x1 << 0;
-    }
-  }
 
-  namespace tstr {
-    namespace str2 {
-      constexpr uint32_t counter_start = 1 << 2;
+constexpr uint32_t bit_mask = 0x1 << 0;
 
-      constexpr uint32_t bit_mask = 0x1 << 2;
-    }
+}
+}
 
-    namespace str1 {
-      constexpr uint32_t counter_start = 1 << 1;
+namespace tstr {
+namespace str2 {
+constexpr uint32_t counter_start = 1 << 2;
 
-      constexpr uint32_t bit_mask = 0x1 << 1;
-    }
 
-    namespace str0 {
-      constexpr uint32_t counter_start = 1 << 0;
+constexpr uint32_t bit_mask = 0x1 << 2;
 
-      constexpr uint32_t bit_mask = 0x1 << 0;
-    }
-  }
+}
 
-  namespace tcr0 {
-    constexpr uint32_t UNF = 1 << 8;
-    constexpr uint32_t UNIE = 1 << 5;
+namespace str1 {
+constexpr uint32_t counter_start = 1 << 1;
 
-    namespace ckeg {
-      constexpr uint32_t rising = 0b00 << 3;
-      constexpr uint32_t falling = 0b01 << 3;
-      constexpr uint32_t rising_falling = 0b10 << 3;
 
-      constexpr uint32_t bit_mask = 0x3 << 3;
-    }
+constexpr uint32_t bit_mask = 0x1 << 1;
 
-    namespace tpsc {
-      constexpr uint32_t p_phi_4 = 0b000 << 0;
-      constexpr uint32_t p_phi_16 = 0b001 << 0;
-      constexpr uint32_t p_phi_64 = 0b010 << 0;
-      constexpr uint32_t p_phi_256 = 0b011 << 0;
-      constexpr uint32_t p_phi_1024 = 0b100 << 0;
-      constexpr uint32_t rtc_output = 0b110 << 0;
-      constexpr uint32_t external = 0b111 << 0;
+}
 
-      constexpr uint32_t bit_mask = 0x7 << 0;
-    }
-  }
+namespace str0 {
+constexpr uint32_t counter_start = 1 << 0;
 
-  namespace tcr1 {
-    constexpr uint32_t UNF = 1 << 8;
-    constexpr uint32_t UNIE = 1 << 5;
 
-    namespace ckeg {
-      constexpr uint32_t rising = 0b00 << 3;
-      constexpr uint32_t falling = 0b01 << 3;
-      constexpr uint32_t rising_falling = 0b10 << 3;
+constexpr uint32_t bit_mask = 0x1 << 0;
 
-      constexpr uint32_t bit_mask = 0x3 << 3;
-    }
+}
+}
 
-    namespace tpsc {
-      constexpr uint32_t p_phi_4 = 0b000 << 0;
-      constexpr uint32_t p_phi_16 = 0b001 << 0;
-      constexpr uint32_t p_phi_64 = 0b010 << 0;
-      constexpr uint32_t p_phi_256 = 0b011 << 0;
-      constexpr uint32_t p_phi_1024 = 0b100 << 0;
-      constexpr uint32_t rtc_output = 0b110 << 0;
-      constexpr uint32_t external = 0b111 << 0;
+namespace tcr0 {
+constexpr uint32_t UNF = 1 << 8;
 
-      constexpr uint32_t bit_mask = 0x7 << 0;
-    }
-  }
+constexpr uint32_t UNIE = 1 << 5;
 
-  namespace tcr2 {
-    constexpr uint32_t ICPF = 1 << 9;
-    constexpr uint32_t UNF = 1 << 8;
 
-    namespace icpe {
-      constexpr uint32_t disabled = 0b00 << 6;
-      constexpr uint32_t enabled = 0b10 << 6;
-      constexpr uint32_t enabled_with_interrupts = 0b11 << 6;
+namespace ckeg {
+constexpr uint32_t rising = 0b00 << 3;
 
-      constexpr uint32_t bit_mask = 0x3 << 6;
-    }
+constexpr uint32_t falling = 0b01 << 3;
 
-    constexpr uint32_t UNIE = 1 << 5;
+constexpr uint32_t rising_falling = 0b10 << 3;
 
-    namespace ckeg {
-      constexpr uint32_t rising = 0b00 << 3;
-      constexpr uint32_t falling = 0b01 << 3;
-      constexpr uint32_t rising_falling = 0b10 << 3;
 
-      constexpr uint32_t bit_mask = 0x3 << 3;
-    }
+constexpr uint32_t bit_mask = 0x3 << 3;
 
-    namespace tpsc {
-      constexpr uint32_t p_phi_4 = 0b000 << 0;
-      constexpr uint32_t p_phi_16 = 0b001 << 0;
-      constexpr uint32_t p_phi_64 = 0b010 << 0;
-      constexpr uint32_t p_phi_256 = 0b011 << 0;
-      constexpr uint32_t p_phi_1024 = 0b100 << 0;
-      constexpr uint32_t rtc_output = 0b110 << 0;
-      constexpr uint32_t external = 0b111 << 0;
+}
 
-      constexpr uint32_t bit_mask = 0x7 << 0;
-    }
-  }
+namespace tpsc {
+constexpr uint32_t p_phi_4 = 0b000 << 0;
+
+constexpr uint32_t p_phi_16 = 0b001 << 0;
+
+constexpr uint32_t p_phi_64 = 0b010 << 0;
+
+constexpr uint32_t p_phi_256 = 0b011 << 0;
+
+constexpr uint32_t p_phi_1024 = 0b100 << 0;
+
+constexpr uint32_t rtc_output = 0b110 << 0;
+
+constexpr uint32_t external = 0b111 << 0;
+
+constexpr uint32_t bit_mask = 0x7 << 0;
+
+}
+}
+
+namespace tcr1 {
+constexpr uint32_t UNF = 1 << 8;
+
+constexpr uint32_t UNIE = 1 << 5;
+
+
+namespace ckeg {
+constexpr uint32_t rising = 0b00 << 3;
+
+constexpr uint32_t falling = 0b01 << 3;
+
+constexpr uint32_t rising_falling = 0b10 << 3;
+
+
+constexpr uint32_t bit_mask = 0x3 << 3;
+
+}
+
+namespace tpsc {
+constexpr uint32_t p_phi_4 = 0b000 << 0;
+
+constexpr uint32_t p_phi_16 = 0b001 << 0;
+
+constexpr uint32_t p_phi_64 = 0b010 << 0;
+
+constexpr uint32_t p_phi_256 = 0b011 << 0;
+
+constexpr uint32_t p_phi_1024 = 0b100 << 0;
+
+constexpr uint32_t rtc_output = 0b110 << 0;
+
+constexpr uint32_t external = 0b111 << 0;
+
+constexpr uint32_t bit_mask = 0x7 << 0;
+
+}
+}
+
+namespace tcr2 {
+constexpr uint32_t ICPF = 1 << 9;
+
+constexpr uint32_t UNF = 1 << 8;
+
+
+namespace icpe {
+constexpr uint32_t disabled = 0b00 << 6;
+
+constexpr uint32_t enabled = 0b10 << 6;
+
+constexpr uint32_t enabled_with_interrupts = 0b11 << 6;
+
+
+constexpr uint32_t bit_mask = 0x3 << 6;
+
+}
+
+constexpr uint32_t UNIE = 1 << 5;
+
+
+namespace ckeg {
+constexpr uint32_t rising = 0b00 << 3;
+
+constexpr uint32_t falling = 0b01 << 3;
+
+constexpr uint32_t rising_falling = 0b10 << 3;
+
+
+constexpr uint32_t bit_mask = 0x3 << 3;
+
+}
+
+namespace tpsc {
+constexpr uint32_t p_phi_4 = 0b000 << 0;
+
+constexpr uint32_t p_phi_16 = 0b001 << 0;
+
+constexpr uint32_t p_phi_64 = 0b010 << 0;
+
+constexpr uint32_t p_phi_256 = 0b011 << 0;
+
+constexpr uint32_t p_phi_1024 = 0b100 << 0;
+
+constexpr uint32_t rtc_output = 0b110 << 0;
+
+constexpr uint32_t external = 0b111 << 0;
+
+constexpr uint32_t bit_mask = 0x7 << 0;
+
+}
+}
 
 }
 
 namespace scif {
-  namespace scsmr2 {
-    namespace chr {
-      constexpr uint32_t _8_bit_data = 0 << 6;
-      constexpr uint32_t _7_bit_data = 1 << 6;
+namespace scsmr2 {
+namespace chr {
+constexpr uint32_t _8_bit_data = 0 << 6;
 
-      constexpr uint32_t bit_mask = 0x1 << 6;
-    }
+constexpr uint32_t _7_bit_data = 1 << 6;
 
-    namespace pe {
-      constexpr uint32_t parity_disabled = 0 << 5;
-      constexpr uint32_t parity_enabled = 1 << 5;
 
-      constexpr uint32_t bit_mask = 0x1 << 5;
-    }
-
-    namespace oe {
-      constexpr uint32_t even_parity = 0 << 4;
-      constexpr uint32_t odd_parity = 1 << 4;
-
-      constexpr uint32_t bit_mask = 0x1 << 4;
-    }
-
-    namespace stop {
-      constexpr uint32_t _1_stop_bit = 0 << 3;
-      constexpr uint32_t _2_stop_bits = 1 << 3;
-
-      constexpr uint32_t bit_mask = 0x1 << 3;
-    }
-
-    namespace cks {
-      constexpr uint32_t p_phi_clock = 0b00 << 0;
-      constexpr uint32_t p_phi_4_clock = 0b01 << 0;
-      constexpr uint32_t p_phi_16_clock = 0b10 << 0;
-      constexpr uint32_t p_phi_64_clock = 0b11 << 0;
-
-      constexpr uint32_t bit_mask = 0x3 << 0;
-    }
-  }
-
-  namespace scscr2 {
-    namespace tie {
-      constexpr uint32_t transmit_fifo_data_empty_interrupt_disabled = 0 << 7;
-      constexpr uint32_t transmit_fifo_data_empty_interrupt_enabled = 1 << 7;
-
-      constexpr uint32_t bit_mask = 0x1 << 7;
-    }
-
-    namespace rie {
-      constexpr uint32_t request_disabled = 0 << 6;
-      constexpr uint32_t request_enabled = 1 << 6;
-
-      constexpr uint32_t bit_mask = 0x1 << 6;
-    }
-
-    namespace te {
-      constexpr uint32_t transmission_disabled = 0 << 5;
-      constexpr uint32_t transmission_enabled = 1 << 5;
-
-      constexpr uint32_t bit_mask = 0x1 << 5;
-    }
-
-    namespace re {
-      constexpr uint32_t reception_disabled = 0 << 4;
-      constexpr uint32_t reception_enabled = 1 << 4;
-
-      constexpr uint32_t bit_mask = 0x1 << 4;
-    }
-
-    namespace reie {
-      constexpr uint32_t requests_disabled = 0 << 3;
-      constexpr uint32_t requests_enabled = 1 << 3;
-
-      constexpr uint32_t bit_mask = 0x1 << 3;
-    }
-
-    namespace cke1 {
-      constexpr uint32_t sck2_pin_functions_as_input_pin = 0 << 1;
-      constexpr uint32_t sck2_pin_functions_as_clock_input = 1 << 1;
-
-      constexpr uint32_t bit_mask = 0x1 << 1;
-    }
-  }
-
-  namespace scfsr2 {
-    namespace per3_0 {
-      constexpr uint32_t number_of_parity_errors(uint32_t reg) { return (reg >> 12) & 0xf; }
-
-      constexpr uint32_t bit_mask = 0xf << 12;
-    }
-
-    namespace fer3_0 {
-      constexpr uint32_t number_of_framing_errors(uint32_t reg) { return (reg >> 8) & 0xf; }
-
-      constexpr uint32_t bit_mask = 0xf << 8;
-    }
-
-    namespace er {
-      constexpr uint32_t no_framing_error_or_parity_error = 0 << 7;
-      constexpr uint32_t framing_error_or_parity_error = 1 << 7;
-
-      constexpr uint32_t bit_mask = 0x1 << 7;
-    }
-
-    namespace tend {
-      constexpr uint32_t transmission_in_progress = 0 << 6;
-      constexpr uint32_t transmission_has_ended = 1 << 6;
-
-      constexpr uint32_t bit_mask = 0x1 << 6;
-    }
-
-    namespace tdfe {
-      constexpr uint32_t transmit_data_bytes_does_exceed_trigger = 0 << 5;
-      constexpr uint32_t transmit_data_bytes_does_not_exceed_trigger = 1 << 5;
-
-      constexpr uint32_t bit_mask = 0x1 << 5;
-    }
-
-    namespace brk {
-      constexpr uint32_t break_not_received = 0 << 4;
-      constexpr uint32_t break_received = 1 << 4;
-
-      constexpr uint32_t bit_mask = 0x1 << 4;
-    }
-
-    namespace fer {
-      constexpr uint32_t no_framing_error = 0 << 3;
-      constexpr uint32_t framing_error = 1 << 3;
-
-      constexpr uint32_t bit_mask = 0x1 << 3;
-    }
-
-    namespace per {
-      constexpr uint32_t parity_error = 0 << 2;
-      constexpr uint32_t no_parity_error = 1 << 2;
-
-      constexpr uint32_t bit_mask = 0x1 << 2;
-    }
-
-    namespace rdf {
-      constexpr uint32_t receive_data_bytes_less_than_receive_trigger = 0 << 1;
-      constexpr uint32_t receive_data_bytes_greater_than_or_equal_receive_trigger = 1 << 1;
-
-      constexpr uint32_t bit_mask = 0x1 << 1;
-    }
-
-    namespace dr {
-      constexpr uint32_t reception_is_in_progress = 0 << 0;
-      constexpr uint32_t no_further_data_has_arrived = 1 << 0;
-
-      constexpr uint32_t bit_mask = 0x1 << 0;
-    }
-  }
-
-  namespace scfcr2 {
-    namespace rtrg {
-      constexpr uint32_t trigger_on_1_byte = 0b00 << 6;
-      constexpr uint32_t trigger_on_4_bytes = 0b01 << 6;
-      constexpr uint32_t trigger_on_8_bytes = 0b10 << 6;
-      constexpr uint32_t trigger_on_14_byte = 0b11 << 6;
-
-      constexpr uint32_t bit_mask = 0x3 << 6;
-    }
-
-    namespace ttrg {
-      constexpr uint32_t trigger_on_8_bytes = 0b00 << 4;
-      constexpr uint32_t trigger_on_4_bytes = 0b01 << 4;
-      constexpr uint32_t trigger_on_2_bytes = 0b10 << 4;
-      constexpr uint32_t trigger_on_1_bytes = 0b11 << 4;
-
-      constexpr uint32_t bit_mask = 0x3 << 4;
-    }
-
-    namespace mce {
-      constexpr uint32_t modem_signals_disabled = 0 << 3;
-      constexpr uint32_t modem_signals_enabled = 1 << 3;
-
-      constexpr uint32_t bit_mask = 0x1 << 3;
-    }
-
-    namespace tfrst {
-      constexpr uint32_t reset_operation_disabled = 0 << 2;
-      constexpr uint32_t reset_operation_enabled = 1 << 2;
-
-      constexpr uint32_t bit_mask = 0x1 << 2;
-    }
-
-    namespace rfrst {
-      constexpr uint32_t reset_operation_disabled = 0 << 1;
-      constexpr uint32_t reset_operation_enabled = 1 << 1;
-
-      constexpr uint32_t bit_mask = 0x1 << 1;
-    }
-
-    namespace loop {
-      constexpr uint32_t loopback_test_disabled = 0 << 0;
-      constexpr uint32_t loopback_test_enabled = 1 << 0;
-
-      constexpr uint32_t bit_mask = 0x1 << 0;
-    }
-  }
-
-  namespace scfdr2 {
-    constexpr uint32_t transmit_data_bytes(uint32_t reg) { return (reg >> 8) & 0x1f; }
-    constexpr uint32_t receive_data_bytes(uint32_t reg) { return (reg >> 0) & 0x1f; }
-  }
-
-  namespace scsptr2 {
-    namespace rtsio {
-      constexpr uint32_t rtsdt_not_output_to_rts2 = 0 << 7;
-      constexpr uint32_t rtsdt_output_to_rts2 = 1 << 7;
-
-      constexpr uint32_t bit_mask = 0x1 << 7;
-    }
-
-    namespace rtsdt {
-      constexpr uint32_t input_output_data_is_low_level = 0 << 6;
-      constexpr uint32_t input_output_data_is_high_level = 1 << 6;
-
-      constexpr uint32_t bit_mask = 0x1 << 6;
-    }
-
-    namespace ctsio {
-      constexpr uint32_t ctsdt_is_not_output_to_cts2 = 0 << 5;
-      constexpr uint32_t ctsdt_is_output_to_cts2 = 1 << 5;
-
-      constexpr uint32_t bit_mask = 0x1 << 5;
-    }
-
-    namespace ctsdt {
-      constexpr uint32_t input_output_data_is_low_level = 0 << 4;
-      constexpr uint32_t input_output_data_is_high_level = 1 << 4;
-
-      constexpr uint32_t bit_mask = 0x1 << 4;
-    }
-
-    namespace spb2io {
-      constexpr uint32_t spb2dt_is_not_output_to_txd2 = 0 << 1;
-      constexpr uint32_t spb2dt_is_output_to_txd2 = 1 << 1;
-
-      constexpr uint32_t bit_mask = 0x1 << 1;
-    }
-
-    namespace spb2dt {
-      constexpr uint32_t input_output_data_is_low_level = 0 << 0;
-      constexpr uint32_t input_output_data_is_high_level = 1 << 0;
-
-      constexpr uint32_t bit_mask = 0x1 << 0;
-    }
-  }
-
-  namespace sclsr2 {
-    namespace orer {
-      constexpr uint32_t overrun_error_occured = 1 << 0;
-
-      constexpr uint32_t bit_mask = 0x1 << 0;
-    }
-  }
+constexpr uint32_t bit_mask = 0x1 << 6;
+
+}
+
+namespace pe {
+constexpr uint32_t parity_disabled = 0 << 5;
+
+constexpr uint32_t parity_enabled = 1 << 5;
+
+
+constexpr uint32_t bit_mask = 0x1 << 5;
+
+}
+
+namespace oe {
+constexpr uint32_t even_parity = 0 << 4;
+
+constexpr uint32_t odd_parity = 1 << 4;
+
+
+constexpr uint32_t bit_mask = 0x1 << 4;
+
+}
+
+namespace stop {
+constexpr uint32_t _1_stop_bit = 0 << 3;
+
+constexpr uint32_t _2_stop_bits = 1 << 3;
+
+
+constexpr uint32_t bit_mask = 0x1 << 3;
+
+}
+
+namespace cks {
+constexpr uint32_t p_phi_clock = 0b00 << 0;
+
+constexpr uint32_t p_phi_4_clock = 0b01 << 0;
+
+constexpr uint32_t p_phi_16_clock = 0b10 << 0;
+
+constexpr uint32_t p_phi_64_clock = 0b11 << 0;
+
+
+constexpr uint32_t bit_mask = 0x3 << 0;
+
+}
+}
+
+namespace scscr2 {
+namespace tie {
+constexpr uint32_t transmit_fifo_data_empty_interrupt_disabled = 0 << 7;
+
+constexpr uint32_t transmit_fifo_data_empty_interrupt_enabled = 1 << 7;
+
+
+constexpr uint32_t bit_mask = 0x1 << 7;
+
+}
+
+namespace rie {
+constexpr uint32_t request_disabled = 0 << 6;
+
+constexpr uint32_t request_enabled = 1 << 6;
+
+
+constexpr uint32_t bit_mask = 0x1 << 6;
+
+}
+
+namespace te {
+constexpr uint32_t transmission_disabled = 0 << 5;
+
+constexpr uint32_t transmission_enabled = 1 << 5;
+
+
+constexpr uint32_t bit_mask = 0x1 << 5;
+
+}
+
+namespace re {
+constexpr uint32_t reception_disabled = 0 << 4;
+
+constexpr uint32_t reception_enabled = 1 << 4;
+
+
+constexpr uint32_t bit_mask = 0x1 << 4;
+
+}
+
+namespace reie {
+constexpr uint32_t requests_disabled = 0 << 3;
+
+constexpr uint32_t requests_enabled = 1 << 3;
+
+
+constexpr uint32_t bit_mask = 0x1 << 3;
+
+}
+
+namespace cke1 {
+constexpr uint32_t sck2_pin_functions_as_input_pin = 0 << 1;
+
+constexpr uint32_t sck2_pin_functions_as_clock_input = 1 << 1;
+
+
+constexpr uint32_t bit_mask = 0x1 << 1;
+
+}
+}
+
+namespace scfsr2 {
+namespace per3_0 {
+constexpr uint32_t number_of_parity_errors(uint32_t reg) { return (reg >> 12) & 0xf; }
+
+constexpr uint32_t bit_mask = 0xf << 12;
+
+}
+
+namespace fer3_0 {
+constexpr uint32_t number_of_framing_errors(uint32_t reg) { return (reg >> 8) & 0xf; }
+
+constexpr uint32_t bit_mask = 0xf << 8;
+
+}
+
+namespace er {
+constexpr uint32_t no_framing_error_or_parity_error = 0 << 7;
+
+constexpr uint32_t framing_error_or_parity_error = 1 << 7;
+
+
+constexpr uint32_t bit_mask = 0x1 << 7;
+
+}
+
+namespace tend {
+constexpr uint32_t transmission_in_progress = 0 << 6;
+
+constexpr uint32_t transmission_has_ended = 1 << 6;
+
+
+constexpr uint32_t bit_mask = 0x1 << 6;
+
+}
+
+namespace tdfe {
+constexpr uint32_t transmit_data_bytes_does_exceed_trigger = 0 << 5;
+
+constexpr uint32_t transmit_data_bytes_does_not_exceed_trigger = 1 << 5;
+
+
+constexpr uint32_t bit_mask = 0x1 << 5;
+
+}
+
+namespace brk {
+constexpr uint32_t break_not_received = 0 << 4;
+
+constexpr uint32_t break_received = 1 << 4;
+
+
+constexpr uint32_t bit_mask = 0x1 << 4;
+
+}
+
+namespace fer {
+constexpr uint32_t no_framing_error = 0 << 3;
+
+constexpr uint32_t framing_error = 1 << 3;
+
+
+constexpr uint32_t bit_mask = 0x1 << 3;
+
+}
+
+namespace per {
+constexpr uint32_t parity_error = 0 << 2;
+
+constexpr uint32_t no_parity_error = 1 << 2;
+
+
+constexpr uint32_t bit_mask = 0x1 << 2;
+
+}
+
+namespace rdf {
+constexpr uint32_t receive_data_bytes_less_than_receive_trigger = 0 << 1;
+
+constexpr uint32_t receive_data_bytes_greater_than_or_equal_receive_trigger = 1 << 1;
+
+
+constexpr uint32_t bit_mask = 0x1 << 1;
+
+}
+
+namespace dr {
+constexpr uint32_t reception_is_in_progress = 0 << 0;
+
+constexpr uint32_t no_further_data_has_arrived = 1 << 0;
+
+
+constexpr uint32_t bit_mask = 0x1 << 0;
+
+}
+}
+
+namespace scfcr2 {
+namespace rtrg {
+constexpr uint32_t trigger_on_1_byte = 0b00 << 6;
+
+constexpr uint32_t trigger_on_4_bytes = 0b01 << 6;
+
+constexpr uint32_t trigger_on_8_bytes = 0b10 << 6;
+
+constexpr uint32_t trigger_on_14_byte = 0b11 << 6;
+
+
+constexpr uint32_t bit_mask = 0x3 << 6;
+
+}
+
+namespace ttrg {
+constexpr uint32_t trigger_on_8_bytes = 0b00 << 4;
+
+constexpr uint32_t trigger_on_4_bytes = 0b01 << 4;
+
+constexpr uint32_t trigger_on_2_bytes = 0b10 << 4;
+
+constexpr uint32_t trigger_on_1_bytes = 0b11 << 4;
+
+
+constexpr uint32_t bit_mask = 0x3 << 4;
+
+}
+
+namespace mce {
+constexpr uint32_t modem_signals_disabled = 0 << 3;
+
+constexpr uint32_t modem_signals_enabled = 1 << 3;
+
+
+constexpr uint32_t bit_mask = 0x1 << 3;
+
+}
+
+namespace tfrst {
+constexpr uint32_t reset_operation_disabled = 0 << 2;
+
+constexpr uint32_t reset_operation_enabled = 1 << 2;
+
+
+constexpr uint32_t bit_mask = 0x1 << 2;
+
+}
+
+namespace rfrst {
+constexpr uint32_t reset_operation_disabled = 0 << 1;
+
+constexpr uint32_t reset_operation_enabled = 1 << 1;
+
+
+constexpr uint32_t bit_mask = 0x1 << 1;
+
+}
+
+namespace loop {
+constexpr uint32_t loopback_test_disabled = 0 << 0;
+
+constexpr uint32_t loopback_test_enabled = 1 << 0;
+
+
+constexpr uint32_t bit_mask = 0x1 << 0;
+
+}
+}
+
+namespace scfdr2 {
+constexpr uint32_t transmit_data_bytes(uint32_t reg) { return (reg >> 8) & 0x1f; }
+constexpr uint32_t receive_data_bytes(uint32_t reg) { return (reg >> 0) & 0x1f; }
+}
+
+namespace scsptr2 {
+namespace rtsio {
+constexpr uint32_t rtsdt_not_output_to_rts2 = 0 << 7;
+
+constexpr uint32_t rtsdt_output_to_rts2 = 1 << 7;
+
+
+constexpr uint32_t bit_mask = 0x1 << 7;
+
+}
+
+namespace rtsdt {
+constexpr uint32_t input_output_data_is_low_level = 0 << 6;
+
+constexpr uint32_t input_output_data_is_high_level = 1 << 6;
+
+
+constexpr uint32_t bit_mask = 0x1 << 6;
+
+}
+
+namespace ctsio {
+constexpr uint32_t ctsdt_is_not_output_to_cts2 = 0 << 5;
+
+constexpr uint32_t ctsdt_is_output_to_cts2 = 1 << 5;
+
+
+constexpr uint32_t bit_mask = 0x1 << 5;
+
+}
+
+namespace ctsdt {
+constexpr uint32_t input_output_data_is_low_level = 0 << 4;
+
+constexpr uint32_t input_output_data_is_high_level = 1 << 4;
+
+
+constexpr uint32_t bit_mask = 0x1 << 4;
+
+}
+
+namespace spb2io {
+constexpr uint32_t spb2dt_is_not_output_to_txd2 = 0 << 1;
+
+constexpr uint32_t spb2dt_is_output_to_txd2 = 1 << 1;
+
+
+constexpr uint32_t bit_mask = 0x1 << 1;
+
+}
+
+namespace spb2dt {
+constexpr uint32_t input_output_data_is_low_level = 0 << 0;
+
+constexpr uint32_t input_output_data_is_high_level = 1 << 0;
+
+
+constexpr uint32_t bit_mask = 0x1 << 0;
+
+}
+}
+
+namespace sclsr2 {
+namespace orer {
+constexpr uint32_t overrun_error_occured = 1 << 0;
+
+
+constexpr uint32_t bit_mask = 0x1 << 0;
+
+}
+}
+
+}
+
+namespace sh {
+namespace sr {
+constexpr uint32_t md = 1 << 30;
+
+constexpr uint32_t rb = 1 << 29;
+
+constexpr uint32_t bl = 1 << 28;
+
+constexpr uint32_t fd = 1 << 15;
+
+constexpr uint32_t m = 1 << 9;
+
+constexpr uint32_t q = 1 << 8;
+
+constexpr uint32_t imask(uint32_t num) { return (num & 0xf) << 4; }
+constexpr uint32_t s = 1 << 1;
+
+constexpr uint32_t t = 1 << 0;
+
+}
+
+namespace fpscr {
+constexpr uint32_t fr = 1 << 21;
+
+constexpr uint32_t sz = 1 << 20;
+
+constexpr uint32_t pr = 1 << 19;
+
+constexpr uint32_t dn = 1 << 18;
+
+
+namespace cause {
+constexpr uint32_t fpu_error = 0b100000 << 12;
+
+constexpr uint32_t invalid_operation = 0b010000 << 12;
+
+constexpr uint32_t division_by_zero = 0b001000 << 12;
+
+constexpr uint32_t overflow = 0b000100 << 12;
+
+constexpr uint32_t underflow = 0b000010 << 12;
+
+constexpr uint32_t inexact = 0b000001 << 12;
+
+
+constexpr uint32_t bit_mask = 0x3f << 12;
+
+}
+
+namespace enabled {
+constexpr uint32_t invalid_operation = 0b10000 << 7;
+
+constexpr uint32_t division_by_zero = 0b01000 << 7;
+
+constexpr uint32_t overflow = 0b00100 << 7;
+
+constexpr uint32_t underflow = 0b00010 << 7;
+
+constexpr uint32_t inexact = 0b00001 << 7;
+
+
+constexpr uint32_t bit_mask = 0x1f << 7;
+
+}
+
+namespace flag {
+constexpr uint32_t invalid_operation = 0b10000 << 2;
+
+constexpr uint32_t division_by_zero = 0b01000 << 2;
+
+constexpr uint32_t overflow = 0b00100 << 2;
+
+constexpr uint32_t underflow = 0b00010 << 2;
+
+constexpr uint32_t inexact = 0b00001 << 2;
+
+
+constexpr uint32_t bit_mask = 0x1f << 2;
+
+}
+
+namespace rm {
+constexpr uint32_t round_to_nearest = 0b00 << 0;
+
+constexpr uint32_t round_to_zero = 0b01 << 0;
+
+
+constexpr uint32_t bit_mask = 0x3 << 0;
+
+}
+}
+
+}
+
+namespace ubc {
+namespace bamra {
+namespace bama {
+constexpr uint32_t all_bara_bits_are_included_in_break_conditions = 0b0000 << 0;
+
+constexpr uint32_t lower_10_bits_of_bara_are_not_included_in_break_conditions = 0b0001 << 0;
+
+constexpr uint32_t lower_12_bits_of_bara_are_not_included_in_break_conditions = 0b0010 << 0;
+
+constexpr uint32_t all_bara_bits_are_not_included_in_break_conditions = 0b0011 << 0;
+
+constexpr uint32_t lower_16_bits_of_bara_are_not_included_in_break_conditions = 0b1000 << 0;
+
+constexpr uint32_t lower_20_bits_of_bara_are_not_included_in_break_conditions = 0b1001 << 0;
+
+
+constexpr uint32_t bit_mask = 0xb << 0;
+
+}
+
+namespace basma {
+constexpr uint32_t all_basra_bits_are_included_in_break_conditions = 0 << 2;
+
+constexpr uint32_t no_basra_bits_are_included_in_break_conditions = 1 << 2;
+
+
+constexpr uint32_t bit_mask = 0x1 << 2;
+
+}
+}
+
+namespace bbra {
+namespace sza {
+constexpr uint32_t operand_size_is_not_included_in_break_conditions = 0b00 << 0;
+
+constexpr uint32_t byte_access_is_used_as_break_condition = 0b01 << 0;
+
+constexpr uint32_t word_access_is_used_as_break_condition = 0b10 << 0;
+
+constexpr uint32_t longword_access_is_used_as_break_condition = 0b11 << 0;
+
+constexpr uint32_t quadword_access_is_used_as_break_condition = 0b1000000 << 0;
+
+
+constexpr uint32_t bit_mask = 0x43 << 0;
+
+}
+
+namespace ida {
+constexpr uint32_t condition_comparison_is_not_performed = 0b00 << 4;
+
+constexpr uint32_t instruction_access_cycle_is_used_as_break_condition = 0b01 << 4;
+
+constexpr uint32_t operand_access_cycle_is_used_as_break_condition = 0b10 << 4;
+
+constexpr uint32_t instruction_access_cycle_or_operand_access_cycle_is_used_as_break_condition = 0b11 << 4;
+
+
+constexpr uint32_t bit_mask = 0x3 << 4;
+
+}
+
+namespace rwa {
+constexpr uint32_t condition_comparison_is_not_performed = 0b00 << 2;
+
+constexpr uint32_t read_cycle_is_used_as_break_condition = 0b01 << 2;
+
+constexpr uint32_t write_cycle_is_used_as_break_condition = 0b10 << 2;
+
+constexpr uint32_t read_cycle_or_write_cycle_is_used_as_break_condition = 0b11 << 2;
+
+
+constexpr uint32_t bit_mask = 0x3 << 2;
+
+}
+}
+
+namespace brcr {
+namespace cmfa {
+constexpr uint32_t channel_a_break_condition_is_not_matched = 0 << 15;
+
+constexpr uint32_t channel_a_break_condition_match_has_occured = 1 << 15;
+
+
+constexpr uint32_t bit_mask = 0x1 << 15;
+
+}
+
+namespace cmfb {
+constexpr uint32_t channel_b_break_condition_is_not_matched = 0 << 14;
+
+constexpr uint32_t channel_b_break_condition_match_has_occured = 1 << 14;
+
+
+constexpr uint32_t bit_mask = 0x1 << 14;
+
+}
+
+namespace pcba {
+constexpr uint32_t channel_a_pc_break_is_effected_before_instruction_execution = 0 << 10;
+
+constexpr uint32_t channel_a_pc_break_is_effected_after_instruction_execution = 1 << 10;
+
+
+constexpr uint32_t bit_mask = 0x1 << 10;
+
+}
+
+namespace dbeb {
+constexpr uint32_t data_bus_condition_is_not_included_in_channel_b_conditions = 0 << 7;
+
+constexpr uint32_t data_bus_condition_is_included_in_channel_b_conditions = 1 << 7;
+
+
+constexpr uint32_t bit_mask = 0x1 << 7;
+
+}
+
+namespace pcbb {
+constexpr uint32_t channel_b_pc_break_is_effected_before_instruction_execution = 0 << 6;
+
+constexpr uint32_t channel_b_pc_break_is_effected_after_instruction_execution = 1 << 6;
+
+
+constexpr uint32_t bit_mask = 0x1 << 6;
+
+}
+
+namespace seq {
+constexpr uint32_t channel_a_and_b_comparison_are_performed_as_independent_condition = 0 << 3;
+
+constexpr uint32_t channel_a_and_b_comparison_are_performed_as_sequential_condition = 1 << 3;
+
+
+constexpr uint32_t bit_mask = 0x1 << 3;
+
+}
+
+namespace ubde {
+constexpr uint32_t user_break_debug_function_is_not_used = 0 << 0;
+
+constexpr uint32_t user_break_debug_function_is_used = 1 << 0;
+
+
+constexpr uint32_t bit_mask = 0x1 << 0;
+
+}
+}
 
 }