132 lines
3.3 KiB
NASM
132 lines
3.3 KiB
NASM
include(common.m4)
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;;; begin glcd_init
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glcd_fill: LDY # 00
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LDA # %01000000 ; Y address
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JSR a :glcd_w_rs0_c2
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LDA # %01000000 ; Y address
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JSR a :glcd_w_rs0_c1
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_glcd_next_page: TYA i
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ORA # %10111000 ; X page
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JSR a :glcd_w_rs0_c2
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TYA i
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ORA # %10111000 ; X page
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JSR a :glcd_w_rs0_c1
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LDX # 40
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_glcd_fill_page: LDA zp 0
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JSR a :glcd_w_rs1_c2
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LDA zp 0
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JSR a :glcd_w_rs1_c1
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DEX i
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BNE r :_glcd_fill_page
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INY i
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CPY # 8
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BNE r :_glcd_next_page
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RTS s
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;;; end glcd_init
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;; write "instruction"
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glcd_w_rs0_c2: JSR a :glcd_wait_c2
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STA a VIA0_PORTB
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LDA # hh(G_C2)
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STA a VIA0_PORTA
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LDA # hh(G_C2|G_E)
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STA a VIA0_PORTA
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LDA # hh(G_C2)
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STA a VIA0_PORTA
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RTS s
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glcd_w_rs0_c1: JSR a :glcd_wait_c1
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STA a VIA0_PORTB
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LDA # hh(G_C1)
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STA a VIA0_PORTA
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LDA # hh(G_C1|G_E)
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STA a VIA0_PORTA
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LDA # hh(G_C1)
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STA a VIA0_PORTA
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RTS s
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;; write "data" to lcd
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glcd_w_rs1_c2: JSR a :glcd_wait_c2
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STA a VIA0_PORTB
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LDA # hh(G_RS|G_C2)
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STA a VIA0_PORTA
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LDA # hh(G_RS|G_C2|G_E)
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STA a VIA0_PORTA
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LDA # hh(G_RS|G_C2)
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STA a VIA0_PORTA
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RTS s
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glcd_w_rs1_c1: JSR a :glcd_wait_c1
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STA a VIA0_PORTB
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LDA # hh(G_RS|G_C1)
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STA a VIA0_PORTA
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LDA # hh(G_RS|G_C1|G_E)
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STA a VIA0_PORTA
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LDA # hh(G_RS|G_C1)
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STA a VIA0_PORTA
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RTS s
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;; wait BF
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glcd_wait_c2: PHA s
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LDA # %00000000 ;; Set pins 0-7 on Port B to Input
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STA a VIA0_DDRB
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_glcd_wait-c2: LDA # hh(G_RW|G_C2)
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STA a VIA0_PORTA
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LDA # hh(G_RW|G_C2|G_E)
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STA a VIA0_PORTA
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LDA a VIA0_PORTB
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AND # %10000000
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BNE r :_glcd_wait-c2
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LDA # hh(G_RW|G_C2)
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STA a VIA0_PORTA
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LDA # %11111111 ;; Set pins 0-7 on Port B to Output
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STA a VIA0_DDRB
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PLA s
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RTS s
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;; wait BF
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glcd_wait_c1: PHA s
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LDA # %00000000 ;; Set pins 0-7 on Port B to Input
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STA a VIA0_DDRB
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_glcd_wait-c1: LDA # hh(G_RW|G_C1)
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STA a VIA0_PORTA
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LDA # hh(G_RW|G_C1|G_E)
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STA a VIA0_PORTA
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LDA a VIA0_PORTB
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AND # %10000000
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BNE r :_glcd_wait-c1
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LDA # hh(G_RW|G_C1)
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STA a VIA0_PORTA
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LDA # %11111111 ;; Set pins 0-7 on Port B to Output
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STA a VIA0_DDRB
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PLA s
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RTS s
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