include(common.m4)

;;; begin glcd_init
glcd_fill:      LDY # 00

                LDA # %01000000 ; Y address
                JSR a :glcd_w_rs0_c2

                LDA # %01000000 ; Y address
                JSR a :glcd_w_rs0_c1

_glcd_next_page:        TYA i
                        ORA # %10111000 ; X page
                        JSR a :glcd_w_rs0_c2

                        TYA i
                        ORA # %10111000 ; X page
                        JSR a :glcd_w_rs0_c1

                        LDX # 40
_glcd_fill_page:                LDA zp 0
                                JSR a :glcd_w_rs1_c2

                                LDA zp 0
                                JSR a :glcd_w_rs1_c1

                                DEX i
                                BNE r :_glcd_fill_page
                        INY i
                        CPY # 8
                        BNE r :_glcd_next_page
                RTS s
;;; end glcd_init


        ;; write "instruction"
glcd_w_rs0_c2:  JSR a :glcd_wait_c2

                STA a VIA0_PORTB
                LDA # hh(G_C2)
                STA a VIA0_PORTA
                LDA # hh(G_C2|G_E)
                STA a VIA0_PORTA

                LDA # hh(G_C2)
                STA a VIA0_PORTA

                RTS s

glcd_w_rs0_c1:  JSR a :glcd_wait_c1

                STA a VIA0_PORTB
                LDA # hh(G_C1)
                STA a VIA0_PORTA
                LDA # hh(G_C1|G_E)
                STA a VIA0_PORTA
                LDA # hh(G_C1)
                STA a VIA0_PORTA

                RTS s

        ;; write "data" to lcd
glcd_w_rs1_c2:  JSR a :glcd_wait_c2

                STA a VIA0_PORTB
                LDA # hh(G_RS|G_C2)
                STA a VIA0_PORTA
                LDA # hh(G_RS|G_C2|G_E)
                STA a VIA0_PORTA
                LDA # hh(G_RS|G_C2)
                STA a VIA0_PORTA

                RTS s

glcd_w_rs1_c1:  JSR a :glcd_wait_c1

                STA a VIA0_PORTB
                LDA # hh(G_RS|G_C1)
                STA a VIA0_PORTA
                LDA # hh(G_RS|G_C1|G_E)
                STA a VIA0_PORTA
                LDA # hh(G_RS|G_C1)
                STA a VIA0_PORTA

                RTS s

        ;; wait BF
glcd_wait_c2:   PHA s

                LDA # %00000000  ;; Set pins 0-7 on Port B to Input
                STA a VIA0_DDRB

_glcd_wait-c2:  LDA # hh(G_RW|G_C2)
                STA a VIA0_PORTA
                LDA # hh(G_RW|G_C2|G_E)
                STA a VIA0_PORTA
                LDA a VIA0_PORTB
                AND # %10000000
                BNE r :_glcd_wait-c2

                LDA # hh(G_RW|G_C2)
                STA a VIA0_PORTA

                LDA # %11111111  ;; Set pins 0-7 on Port B to Output
                STA a VIA0_DDRB

                PLA s
                RTS s

        ;; wait BF
glcd_wait_c1:   PHA s

                LDA # %00000000  ;; Set pins 0-7 on Port B to Input
                STA a VIA0_DDRB

_glcd_wait-c1:  LDA # hh(G_RW|G_C1)
                STA a VIA0_PORTA
                LDA # hh(G_RW|G_C1|G_E)
                STA a VIA0_PORTA
                LDA a VIA0_PORTB
                AND # %10000000
                BNE r :_glcd_wait-c1

                LDA # hh(G_RW|G_C1)
                STA a VIA0_PORTA

                LDA # %11111111  ;; Set pins 0-7 on Port B to Output
                STA a VIA0_DDRB

                PLA s
                RTS s