47 lines
1.4 KiB
C
47 lines
1.4 KiB
C
int dot_clock; /* Dot clock frequency in kHz. */
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int hdisplay; // hr
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int hsync_start; // hs
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int hsync_end; // he
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int htotal; // ht
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int vdisplay; // vr
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int vsync_start; // vs
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int vsync_end; // ve
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int vtotal; // vt
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int flags; // f /* Video mode flags; see below. */
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const char *name;
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// name hr vr clk hs he ht vs ve vt f
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// M("800x600x60",800,600,40000,840,968,1056,601,605,628,HP|VP),
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/* dac write */
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// 0x04 0x0a
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//tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLWR, TDV_GENDAC_PLL_0);
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{
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// TDV_GENDAC_ADDRMASK 0x07
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wreg = ((reg & TDV_GENDAC_ADDRMASK) << 8) | val;
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// TDV_OFF_DAC_DATA 0x22c
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tdvfb_cvg_write(sc, TDV_OFF_DAC_DATA, wreg);
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tdvfb_wait(sc);
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}
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/* dac read */
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{
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// reg = TDV_GENDAC_PLLWR 0x4 "PLL Address (write mode)"
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// reg = TDV_GENDAC_PLLDATA 0x5 "PLL Parameter"
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// reg = TDV_GENDAC_CMD 0x6 "Command"
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// reg = TDV_GENDAC_PLLRD 0x7 "PLL Address (read mode)"
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// TDV_DAC_DATA_READ (1 << 11) 0x800
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tdvfb_cvg_dac_write(sc, reg, TDV_DAC_DATA_READ);
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/* When fbiinit2/fbiinit3 address remapping is enabled (PCI Configuration
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register initEnable bit(2)=1), reading from fbiinit2 bits (7:0) returns the last
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value read from the external DAC (fbiinit2 bits(31:8) are undefined when address
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remapping is enabled).
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*/
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// TDV_OFF_DAC_READ 0x0218 fbiInit2
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rv = tdvfb_cvg_read(sc, TDV_OFF_DAC_READ);
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return rv & 0xFF;
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}
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