int dot_clock;		/* Dot clock frequency in kHz. */
int hdisplay;     // hr
int hsync_start;  // hs
int hsync_end;    // he
int htotal;       // ht
int vdisplay;     // vr
int vsync_start;  // vs
int vsync_end;    // ve
int vtotal;       // vt
int flags;	  // f	/* Video mode flags; see below. */
const char *name;

//   name         hr  vr  clk   hs  he  ht   vs  ve  vt  f
// M("800x600x60",800,600,40000,840,968,1056,601,605,628,HP|VP),

/* dac write */
//                        0x04              0x0a
//tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLWR, TDV_GENDAC_PLL_0);

{
  // TDV_GENDAC_ADDRMASK 0x07
  wreg = ((reg & TDV_GENDAC_ADDRMASK) << 8) | val;
  // TDV_OFF_DAC_DATA 0x22c
  tdvfb_cvg_write(sc, TDV_OFF_DAC_DATA, wreg);
  tdvfb_wait(sc);
}

/* dac read */
{
  // reg = TDV_GENDAC_PLLWR 0x4 "PLL Address (write mode)"
  // reg = TDV_GENDAC_PLLDATA 0x5 "PLL Parameter"
  // reg = TDV_GENDAC_CMD 0x6 "Command"
  // reg = TDV_GENDAC_PLLRD 0x7 "PLL Address (read mode)"
  // TDV_DAC_DATA_READ (1 << 11) 0x800
  tdvfb_cvg_dac_write(sc, reg, TDV_DAC_DATA_READ);

  /* When fbiinit2/fbiinit3 address remapping is enabled (PCI Configuration
     register initEnable bit(2)=1), reading from fbiinit2 bits (7:0) returns the last
     value read from the external DAC (fbiinit2 bits(31:8) are undefined when address
     remapping is enabled).
  */

  // TDV_OFF_DAC_READ 0x0218 fbiInit2
  rv = tdvfb_cvg_read(sc, TDV_OFF_DAC_READ);
  return rv & 0xFF;
}
