module vga_fb
  (input wire       clk,
   input wire	    rst,
   output reg [3:0] red,
   output reg [3:0] green,
   output reg [3:0] blue,
   output reg	    h_sync,
   output reg	    v_sync);


   wire [9:0] h_count;
   wire [9:0] v_count;
   wire	      display;

   wire	      h_sync1;
   wire	      v_sync1;

   vga_spg spg(.clk(clk),
	       .rst(rst),
	       .h_count(h_count),
	       .v_count(v_count),
	       .h_sync(h_sync1),
	       .v_sync(v_sync1),
	       .display(display));

   always @(posedge clk) begin
      h_sync <= h_sync1;
      v_sync <= v_sync1;

      if (display) begin
	 if (h_count == 0 && v_count == 0) begin
	    red <= 4'd15;
	    green <= 4'd15;
	    blue <= 4'd15;
	 end else if (v_count[3]) begin
	    red <= 4'd15;
	    green <= 4'd15;
	    blue <= 4'd0;
         end else begin
	    red <= 4'd15;
	    green <= 4'd0;
	    blue <= 4'd0;
         end
      end else begin
	 red <= 4'd0;
	 green <= 4'd0;
	 blue <= 4'd0;
      end
   end

endmodule