module vga_fb
  (input wire       clk,
   input wire	     rst,
   output reg [3:0]  red,
   output reg [3:0]  green,
   output reg [3:0]  blue,
   output reg	     h_sync,
   output reg	     v_sync,
   output wire [9:0] h_count,
   output wire [9:0] v_count,
   output wire	     display,
   output reg [18:0] addr
   );

   wire	      h_sync1;
   wire	      v_sync1;

   vga_spg spg(.clk(clk),
	       .rst(rst),
	       .h_count(h_count),
	       .v_count(v_count),
	       .h_sync(h_sync1),
	       .v_sync(v_sync1),
	       .display(display));

   //reg [18:0] addr;
   reg	      clk2;

   always @(posedge clk) begin
      if (rst)
	clk2 <= 1'b0;
      else
	clk2 <= ~clk2;

      if (rst || v_sync1) begin
	 addr <= 0;
      end else if (display) begin
	 if (clk2)
	   if (addr < 76799)
	     addr <= addr + 1;
	   else
	     addr <= 0;
      end
   end

   wire read = 1'b1;

   wire [11:0] rdata;

   vga_mem mem(.clk(clk),
	       .read(read),
	       .addr(addr),
	       .rdata(rdata));

   always @(posedge clk) begin
      h_sync <= !h_sync1;
      v_sync <= !v_sync1;

      if (display) begin
         red <= rdata[11:8];
	 green <= rdata[7:4];
         blue <= rdata[3:0];
      end else begin
	 red <= 4'd0;
	 green <= 4'd0;
	 blue <= 4'd0;
      end
   end

endmodule