module vga_tb;

   reg rst = 0;

   initial begin
      $dumpfile("test.vcd");
      $dumpvars;

      # 10 rst = 1;
      # 2 rst = 0;
      # 2800000 $finish;
   end

   reg clk = 0;
   always #1 clk = !clk;

   wire	[3:0] red;
   wire	[3:0] green;
   wire [3:0] blue;
   wire	      h_sync;
   wire	      v_sync;
   wire [9:0] h_count;
   wire [9:0] v_count;
   wire	      display;
   wire [18:0] addr;

   vga_fb fb(clk,
	     rst,
	     red,
	     green,
	     blue,
	     h_sync,
	     v_sync,
	     h_count,
	     v_count,
	     display,
	     addr);

   always @(negedge clk) begin
      if (!rst && display)
	$display("%h %h %h %h %h %h", addr, h_count, v_count, red, green, blue);
   end

endmodule