module vga_mem
  (input wire        clk,
   input wire	     read,
   input wire [18:0] addr,
   output reg [11:0] rdata
   );

   reg [11:0] mem [0:76799];

   initial
      $readmemh("vga_ram.hex", mem);

   always @(posedge clk) begin
      if (read) begin
         rdata <= mem[addr];
      end
   end
endmodule