set -eux

yosys <<EOF
read_verilog vga_spg.v
read_verilog vga_mem.v
read_verilog vga_fb.v
read_verilog vga_top.v
synth_gatemate -top vga_top -nomx8 -vlog net/synth.v
EOF

PR=/home/bilbo/cc-toolchain-linux/bin/p_r/p_r

$PR -i net/synth.v -o bin/vga -ccf vga.ccf -cCP

openFPGALoader --cable dirtyJtag bin/vga_00.cfg