Zack Buhman
fe6f12cbb6
Previously, ast transformations were performed informally as ad-hoc modifications to the generated C source code. In this commit, the same transformations are performed by rewriting the ast prior to code generation time. The most significant new transformer is transform_assignment_list. This transforms assignments such as: a, b, c = f(b, c, d) To: a = f(&b, &c, d) The former syntax is used frequently in the manual's description of FPU-related instructions.
182 lines
6.2 KiB
Python
182 lines
6.2 KiB
Python
mapping = {
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"ReadMemory8" : "read_memory8",
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"ReadMemory16" : "read_memory16",
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"ReadMemory32" : "read_memory32",
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"WriteMemory8" : "write_memory8",
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"WriteMemory16" : "write_memory16",
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"WriteMemory32" : "write_memory32",
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"ZeroExtend1" : "zero_extend1",
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"ZeroExtend4" : "zero_extend4",
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"ZeroExtend5" : "zero_extend5",
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"ZeroExtend8" : "zero_extend8",
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"ZeroExtend16" : "zero_extend16",
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"ZeroExtend32" : "zero_extend32",
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"SignedSaturate32": "signed_saturate32",
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"SignedSaturate48": "signed_saturate48",
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"SignExtend8" : "sign_extend8",
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"SignExtend12" : "sign_extend12",
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"SignExtend16" : "sign_extend16",
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"SignExtend32" : "sign_extend32",
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"Register" : "_register",
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"Bit" : "bit",
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"MACH" : "state->mach",
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"MACL" : "state->macl",
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"PR" : "state->pr[0]",
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"PR’" : "state->pr[1]",
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"PR’’" : "state->pr[2]",
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"PC" : "state->pc[0]",
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"PC’" : "state->pc[1]",
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"PC’’" : "state->pc[2]",
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"FPSCR" : "state->fpscr.value",
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"FPUL" : "state->fpul",
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"SR" : "state->sr.value",
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"SSR" : "state->ssr",
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"SPC" : "state->spc",
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"GBR" : "state->gbr",
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"VBR" : "state->vbr",
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"SGR" : "state->sgr",
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"DBR" : "state->dbr",
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"R0" : "REG(state, 0)",
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"Rm" : "REG(state, m)",
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"Rm_BANK" : "REG_BANK(state, m)",
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"Rn" : "REG(state, n)",
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"Rn_BANK" : "REG_BANK(state, n)",
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"T" : "state->sr.bits.t",
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"S" : "state->sr.bits.s",
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"Q" : "state->sr.bits.q",
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"M" : "state->sr.bits.m",
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"MD" : "state->sr.bits.md",
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"NOP" : "",
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"BREAK" : "BREAK",
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"FIRSTWRITE" : "FIRSTWRITE",
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"FPUDIS" : "FPUDIS",
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"FPUEXC" : "FPUEXC",
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"ILLSLOT" : "ILLSLOT",
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"RADDERR" : "RADDERR",
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"READPROT" : "READPROT",
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"RESINST" : "RESINST",
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"RTLBMISS" : "RTLBMISS",
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"SLOTFPUDIS" : "SLOTFPUDIS",
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"TRAP" : "TRAP",
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"WADDERR" : "WADDERR",
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"WRITEPROT" : "WRITEPROT",
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"WTLBMISS" : "WTLBMISS",
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"IsDelaySlot" : "is_delay_slot",
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"SLEEP" : "sleep",
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"OCBP" : "ocbp",
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"ASID" : "ASID",
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"VPN" : "VPN",
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"PPN" : "PPN",
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"SZ" : "SZ",
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"SZ0" : "SZ0",
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"SZ1" : "SZ1",
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"SH" : "SH",
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"WT" : "WT",
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"C" : "C",
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"D" : "D",
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"V" : "V",
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"ALLOCO" : "ALLOCO",
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"MMU" : "MMU",
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"MMUCR" : "MMUCR",
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"OCBI" : "OCBI",
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"OCBWB" : "OCBWB",
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"PREF" : "PREF",
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"PTEH" : "PTEH",
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"PTEL" : "PTEL",
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"URC" : "URC",
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"UTLB" : "UTLB",
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"AddressUnavailable": "address_unavailable",
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"DataAccessMiss" : "data_access_miss",
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"DirtyBit" : "dirty_bit",
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"ReadProhibited" : "read_prohibited",
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"WriteProhibited" : "write_prohibited",
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"FR0" : "FR_(state, 0)",
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"FRm" : "FR_(state, m)",
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"FRn" : "FR_(state, n)",
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"FP2m" : "FP2_(state, m)",
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"FP2n" : "FP2_(state, n)",
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"DR2m" : "DR2_(state, m)",
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"DR2n" : "DR2_(state, n)",
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"XD2m" : "XD2_(state, m)",
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"XD2n" : "XD2_(state, n)",
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"FV4n" : "FV4_(state, n)",
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"FV4m" : "FV4_(state, m)",
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"XMTRX" : "XMTRX(state)",
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"FR" : "fr",
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"ReadMemoryPair32" : "read_memory_pair32",
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"WriteMemoryPair32" : "write_memory_pair32",
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"FloatRegister32" : "float_register32",
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"FloatRegister64" : "float_register64",
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"FloatRegisterPair32" : "float_register_pair32",
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"FloatRegisterVector32": "float_register_vector32",
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"FloatValue32" : "float_value32",
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"FloatValue64" : "float_value64",
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"FloatValuePair32" : "float_value_pair32",
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"FloatValueVector32" : "float_value_vector32",
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"FloatValueMatrix32" : "float_value_matrix32",
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"FADD_S" : "fadd_s",
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"FADD_D" : "fadd_d",
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"FSUB_S" : "fsub_s",
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"FSUB_D" : "fsub_d",
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"FMUL_S" : "fmul_s",
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"FMUL_D" : "fmul_d",
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"FDIV_S" : "fdiv_s",
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"FDIV_D" : "fdiv_d",
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"FABS_S" : "fabs_s",
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"FABS_D" : "fabs_d",
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"FNEG_S" : "fneg_s",
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"FNEG_D" : "fneg_d",
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"FSQRT_S" : "fsqrt_s",
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"FSQRT_D" : "fsqrt_d",
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"FCMPEQ_S" : "fcmpeq_s",
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"FCMPEQ_D" : "fcmpeq_d",
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"FCMPGT_S" : "fcmpgt_s",
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"FCMPGT_D" : "fcmpgt_d",
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"FCNV_SD" : "fcnv_sd",
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"FCNV_DS" : "fcnv_ds",
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"FTRC_SL" : "ftrc_sl",
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"FTRC_DL" : "ftrc_dl",
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"FLOAT_LS" : "float_ls",
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"FLOAT_LD" : "float_ld",
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"FMAC_S" : "fmac_s",
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"FIPR_S" : "fipr_s",
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"FTRV_S" : "ftrv_s",
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"FpuIsDisabled" : "fpu_is_disabled",
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"FpuFlagI" : "fpu_flag_I",
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"FpuFlagU" : "fpu_flag_U",
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"FpuFlagO" : "fpu_flag_O",
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"FpuFlagZ" : "fpu_flag_Z",
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"FpuFlagV" : "fpu_flag_V",
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"FpuCauseI" : "fpu_cause_I",
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"FpuCauseU" : "fpu_cause_U",
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"FpuCauseO" : "fpu_cause_O",
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"FpuCauseZ" : "fpu_cause_Z",
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"FpuCauseV" : "fpu_cause_V",
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"FpuCauseE" : "fpu_cause_E",
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"FpuEnableI" : "fpu_enable_I",
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"FpuEnableU" : "fpu_enable_U",
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"FpuEnableO" : "fpu_enable_O",
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"FpuEnableZ" : "fpu_enable_Z",
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"FpuEnableV" : "fpu_enable_V",
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}
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