sh-dis/identifier_substitution.py
Zack Buhman b6c629baad initial SH4 emulator implementation in C
This currently only implements the SH2 instructions.
2024-04-21 20:54:32 +08:00

108 lines
2.7 KiB
Python

mapping = {
"ReadMemory8" : "read_memory8",
"ReadMemory16" : "read_memory16",
"ReadMemory32" : "read_memory32",
"WriteMemory8" : "write_memory8",
"WriteMemory16" : "write_memory16",
"WriteMemory32" : "write_memory32",
"ZeroExtend1" : "zero_extend1",
"ZeroExtend4" : "zero_extend4",
"ZeroExtend5" : "zero_extend5",
"ZeroExtend8" : "zero_extend8",
"ZeroExtend16" : "zero_extend16",
"ZeroExtend32" : "zero_extend32",
"SignedSaturate32": "signed_saturate32",
"SignedSaturate48": "signed_saturate48",
"SignExtend8" : "sign_extend8",
"SignExtend12" : "sign_extend12",
"SignExtend16" : "sign_extend16",
"SignExtend32" : "sign_extend32",
"Register" : "_register",
"Bit" : "bit",
"MACH" : "state->mach",
"MACL" : "state->macl",
"PR" : "state->pr[0]",
"PR’" : "state->pr[1]",
"PR’’" : "state->pr[2]",
"PC" : "state->pc[0]",
"PC’" : "state->pc[1]",
"PC’’" : "state->pc[2]",
"FPSCR" : "state->fpscr",
"FPUL" : "state->fpul",
"SR" : "state->sr.value",
"SSR" : "state->ssr",
"SPC" : "state->spc",
"GBR" : "state->gbr",
"VBR" : "state->vbr",
"SGR" : "state->sgr",
"DBR" : "state->dbr",
"R0" : "REG(state, 0)",
"Rm" : "REG(state, m)",
"Rm_BANK" : "REG_BANK(state, m)",
"Rn" : "REG(state, n)",
"Rn_BANK" : "REG_BANK(state, n)",
"T" : "state->sr.bits.t",
"S" : "state->sr.bits.s",
"Q" : "state->sr.bits.q",
"M" : "state->sr.bits.m",
"MD" : "state->sr.bits.md",
"NOP" : "",
"BREAK" : "BREAK",
"FIRSTWRITE" : "FIRSTWRITE",
"FPUDIS" : "FPUDIS",
"FPUEXC" : "FPUEXC",
"ILLSLOT" : "ILLSLOT",
"RADDERR" : "RADDERR",
"READPROT" : "READPROT",
"RESINST" : "RESINST",
"RTLBMISS" : "RTLBMISS",
"SLOTFPUDIS" : "SLOTFPUDIS",
"TRAP" : "TRAP",
"WADDERR" : "WADDERR",
"WRITEPROT" : "WRITEPROT",
"WTLBMISS" : "WTLBMISS",
"IsDelaySlot" : "is_delay_slot",
"SLEEP" : "sleep",
"OCBP" : "ocbp",
}
"""
ASID
VPN
PPN
SZ
SZ0
SZ1
SH
PR
WT
C
D
V
AddressUnavailable
ALLOCO
DataAccessMiss
DirtyBit
FpuIsDisabled
IsDelaySlot
MMU
MMUCR
OCBI
OCBWB
PREF
PTEH
PTEL
ReadProhibited
URC
UTLB
WriteProhibited
"""