sh-dis/bitfield.py
Zack Buhman 8a300ba4c6 initial SH4 emulator implementation in C
This currently only implements the SH2 instructions.
2024-04-22 20:53:36 +08:00

75 lines
2.8 KiB
Python

sr_bits = (
("T" , 0 , 1), # true/false condition
("S" , 1 , 1), # saturation
("IMASK", 4 , 4), # interrupt mask level, 4 bits
("Q" , 8 , 1), # state for divide step
("M" , 9 , 1), # state for divide step
("FD" , 15, 1), # FPU disable
("BL" , 28, 1), # Exception/interrupt block bit
("RB" , 29, 1), # General register bank specifier in privileged mode
("MD" , 30, 1), # Processor mode
)
#define FPSCR__RM (1 << 0 ) /* Rounding mode */
#define FPSCR__FLAG_INEXACT (1 << 2 )
#define FPSCR__FLAG_UNDERFLOW (1 << 3 )
#define FPSCR__FLAG_OVERFLOW (1 << 4 )
#define FPSCR__FLAG_DIVISION_BY_ZERO (1 << 5 )
#define FPSCR__FLAG_INVALID_OPERATION (1 << 6 )
#define FPSCR__ENABLE_INEXACT (1 << 7 )
#define FPSCR__ENABLE_UNDERFLOW (1 << 8 )
#define FPSCR__ENABLE_OVERFLOW (1 << 9 )
#define FPSCR__ENABLE_DIVISION_BY_ZERO (1 << 10)
#define FPSCR__ENABLE_INVALID (1 << 11)
#define FPSCR__CAUSE_INEXACT (1 << 12)
#define FPSCR__CAUSE_UNDERFLOW (1 << 13)
#define FPSCR__CAUSE_OVERFLOW (1 << 14)
#define FPSCR__CAUSE_DIVISION_BY_ZERO (1 << 15)
#define FPSCR__CAUSE_INVALID (1 << 16)
#define FPSCR__CAUSE_FPU_ERROR (1 << 17)
#define FPSCR__DN (1 << 18) /* Denormalization mode */
#define FPSCR__PR (1 << 19) /* Precision mode */
#define FPSCR__SZ (1 << 20) /* Transfer size mode */
#define FPSCR__FR (1 << 21) /* Floating-point register bank */
def generate_bitfield(bits, start=0, end=31):
res = 0
current = start
for name, index, length in bits:
if index != current:
size = index - current
yield f"_res{res}", size
res += 1
yield name, length
current = index + 1
end_len = end + 1
if current != end_len:
yield f"_res{res}", end_len - current
def generate_bitfield_little(bits):
return generate_bitfield(bits)
def generate_bitfield_big(bits):
return reversed(list(generate_bitfield(bits)))
def generate(struct_name, bits):
yield "#pragma once"
yield ""
yield "#include <stdint.h>"
yield ""
yield f"struct {struct_name} {{"
yield "#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__"
for name, size in generate_bitfield_little(bits):
yield f" uint32_t {name.lower()} : {size};"
yield "#elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__"
for name, size in generate_bitfield_big(bits):
yield f" uint32_t {name.lower()} : {size};"
yield "#else"
yield '# error "unsupported endianness"'
yield "#endif"
yield "};"
if __name__ == "__main__":
print('\n'.join(generate("sr_bits", sr_bits)))