119 lines
4.8 KiB
Python
119 lines
4.8 KiB
Python
mode_name = {
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'': 'no_operand',
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'Rn': 'destination_operand_only',
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'Rm': 'destination_operand_only',
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'Rm,Rn': 'source_and_destination_operands',
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'Rm,SR': 'transfer_to_sr',
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'Rm,SSR': 'transfer_to_ssr',
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'Rm,SPC': 'transfer_to_spc',
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'Rm,GBR': 'transfer_to_gbr',
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'Rm,VBR': 'transfer_to_vbr',
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'Rm,DBR': 'transfer_to_dbr',
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'Rm,MACH': 'transfer_to_mach',
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'Rm,MACL': 'transfer_to_macl',
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'Rm,Rn_BANK': 'transfer_to_rn_bank',
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'Rm,PR': 'transfer_to_pr',
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'SR,Rn': 'transfer_from_sr',
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'SSR,Rn': 'transfer_from_ssr',
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'SPC,Rn': 'transfer_from_spc',
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'GBR,Rn': 'transfer_from_gbr',
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'VBR,Rn': 'transfer_from_vbr',
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'DBR,Rn': 'transfer_from_dbr',
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'SGR,Rn': 'transfer_from_sgr',
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'MACH,Rn': 'transfer_from_mach',
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'MACL,Rn': 'transfer_from_macl',
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'Rm_BANK,Rn': 'transfer_from_rm_bank',
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'PR,Rn': 'transfer_from_pr',
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'@Rn': 'destination_operand_only',
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'Rm,@Rn': 'store_register_direct_data_transfer',
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'R0,@Rn': 'r0_store_register_direct_data_transfer',
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'@Rm,Rn': 'load_register_direct_data_transfer',
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'@Rm+,@Rn+': 'multiply_and_accumulate_operation',
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'@Rm+,Rn': 'load_direct_data_transfer_from_register',
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'@Rm+,SR': 'load_to_sr',
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'@Rm+,SSR': 'load_to_ssr',
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'@Rm+,SPC': 'load_to_spc',
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'@Rm+,GBR': 'load_to_gbr',
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'@Rm+,VBR': 'load_to_vbr',
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'@Rm+,DBR': 'load_to_dbr',
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'@Rm+,MACH': 'load_to_mach',
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'@Rm+,MACL': 'load_to_macl',
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'@Rm+,Rn_BANK': 'load_to_rn_bank',
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'@Rm+,PR': 'load_to_pr',
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'Rm,@-Rn': 'store_direct_data_transfer_from_register',
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'SR,@-Rn': 'store_from_sr',
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'SSR,@-Rn': 'store_from_ssr',
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'SPC,@-Rn': 'store_from_spc',
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'GBR,@-Rn': 'store_from_gbr',
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'VBR,@-Rn': 'store_from_vbr',
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'DBR,@-Rn': 'store_from_dbr',
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'SGR,@-Rn': 'store_from_sgr',
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'MACH,@-Rn': 'store_from_mach',
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'MACL,@-Rn': 'store_from_macl',
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'Rm_BANK,@-Rn': 'store_from_rm_bank',
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'PR,@-Rn': 'store_from_pr',
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'R0,@(disp,Rn)': 'store_register_indirect_with_displacement',
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'Rm,@(disp,Rn)': 'store_register_indirect_with_displacement',
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'@(disp,Rm),R0': 'load_register_indirect_with_displacement',
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'@(disp,Rm),Rn': 'load_register_indirect_with_displacement',
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'Rm,@(R0,Rn)': 'store_indexed_register_indirect',
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'@(R0,Rm),Rn': 'load_indexed_register_indirect',
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'R0,@(disp,GBR)': 'store_gbr_indirect_with_displacement',
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'@(disp,GBR),R0': 'load_gbr_indirect_with_displacement',
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'#imm,@(R0,GBR)': 'store_indexed_gbr_indirect',
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'@(R0,GBR),#imm': 'load_indexed_gbr_indirect',
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'@(disp,PC),Rn': 'pc_relative_with_displacement',
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'@(disp,PC),R0': 'pc_relative_with_displacement',
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'label': 'pc_relative',
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'#imm,Rn': 'immediate',
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'#imm,R0': 'immediate',
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'#imm': 'immediate',
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# floating point
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'FRn': 'destination_operand_only',
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'DRn': 'destination_operand_only_double',
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'FRm,FRn': 'source_and_destination_operands',
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'DRm,DRn': 'source_and_destination_operands_double',
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'XDm,XDn': 'source_and_destination_operands_bank',
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'DRm,XDn': 'double_to_bank',
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'XDm,DRn': 'bank_to_double',
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'@Rm,FRn': 'load_register_direct_data_transfer',
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'@Rm,DRn': 'load_register_direct_data_transfer_double',
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'@Rm,XDn': 'load_register_direct_data_transfer_bank',
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'@(R0,Rm),FRn': 'load_indexed_register_indirect',
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'@(R0,Rm),DRn': 'load_indexed_register_indirect_double',
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'@(R0,Rm),XDn': 'load_indexed_register_indirect_bank',
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'@Rm+,FRn': 'load_direct_data_transfer_from_register',
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'@Rm+,DRn': 'load_direct_data_transfer_from_register_double',
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'@Rm+,XDn': 'load_direct_data_transfer_from_register_bank',
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'FRm,@Rn': 'store_register_direct_data_transfer',
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'DRm,@Rn': 'store_register_direct_data_transfer_double',
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'XDm,@Rn': 'store_register_direct_data_transfer_bank',
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'FRm,@-Rn': 'store_direct_data_transfer_from_register',
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'DRm,@-Rn': 'store_direct_data_transfer_from_register_double',
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'XDm,@-Rn': 'store_direct_data_transfer_from_register_bank',
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'FRm,@(R0,Rn)': 'store_indexed_register_indirect',
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'DRm,@(R0,Rn)': 'store_indexed_register_indirect_double',
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'XDm,@(R0,Rn)': 'store_indexed_register_indirect_bank',
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'FRm,FPUL': 'frm_to_fpul',
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'DRm,FPUL': 'drm_to_fpul',
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'FPUL,FRn': 'fpul_to_frn',
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'FPUL,DRn': 'fpul_to_drn',
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'FR0,FRm,FRn': 'fr0_frm_frn',
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'Rm,FPSCR': 'transfer_to_fpscr',
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'Rm,FPUL': 'transfer_to_fpul',
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'@Rm+,FPSCR': 'load_to_fpscr',
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'@Rm+,FPUL': 'load_to_fpul',
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'FPSCR,Rn': 'transfer_from_fpscr',
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'FPUL,Rn': 'transfer_from_fpul',
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'FPUL,@-Rn': 'store_from_fpul',
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'FPSCR,@-Rn': 'store_from_fpscr',
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'FVm,FVn': 'fvm_fvn',
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'XMTRX,FVn': 'xmtrx_fvn',
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}
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def instruction_function_name(ins):
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name = ins.instruction.replace('.', '_').replace('/', '_').lower()
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assert ins.operands in mode_name, (ins.instruction, ins.operands)
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mode = mode_name[ins.operands]
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return '__'.join([name, mode])
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