Zack Buhman
7299da7bdb
Previously, ast transformations were performed informally as ad-hoc modifications to the generated C source code. In this commit, the same transformations are performed by rewriting the ast prior to code generation time. The most significant new transformer is transform_assignment_list. This transforms assignments such as: a, b, c = f(b, c, d) To: a = f(&b, &c, d) The former syntax is used frequently in the manual's description of FPU-related instructions.
93 lines
2.7 KiB
C
93 lines
2.7 KiB
C
#pragma once
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#include <assert.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include "status_bits.h"
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#define SR__RB (1 << 29)
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#define SR__MD (1 << 30)
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#define BANK(sr) (((sr) & SR__RB) && ((sr) & SR__MD))
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#define REGN(sr, x) (((x) & (1 << 3)) ? (x) : ((x) ^ (BANK(sr) << 4)))
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#define REG(state, x) ((state)->general_register[REGN((state)->sr.value, (x))])
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#define REGN_BANK(sr, x) (((x) & (1 << 3)) ? (x) : ((x) ^ ((!BANK(sr)) << 4)))
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#define REG_BANK(state, x) ((state)->general_register[REGN_BANK((state)->sr.value, (x))])
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static_assert(REGN(0, 0 ) == 0 );
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static_assert(REGN(0, 7 ) == 7 );
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static_assert(REGN(0, 8 ) == 8 );
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static_assert(REGN(0, 15) == 15);
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static_assert(REGN(SR__MD | SR__RB, 0 ) == 16);
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static_assert(REGN(SR__MD | SR__RB, 7 ) == 23);
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static_assert(REGN(SR__MD | SR__RB, 8 ) == 8 );
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static_assert(REGN(SR__MD | SR__RB, 15) == 15);
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static_assert(REGN_BANK(0, 0 ) == 16);
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static_assert(REGN_BANK(0, 7 ) == 23);
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static_assert(REGN_BANK(0, 8 ) == 8 );
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static_assert(REGN_BANK(0, 15) == 15);
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static_assert(REGN_BANK(SR__MD | SR__RB, 0 ) == 0 );
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static_assert(REGN_BANK(SR__MD | SR__RB, 7 ) == 7 );
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static_assert(REGN_BANK(SR__MD | SR__RB, 8 ) == 8 );
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static_assert(REGN_BANK(SR__MD | SR__RB, 15) == 15);
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union floating_point_registers {
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uint32_t fr[32];
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uint32_t fp[16][2];
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uint64_t dr[16];
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uint32_t fv[8][4];
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uint32_t fm[2][16];
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};
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static_assert((sizeof (union floating_point_registers)) == 32 * 4);
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#define FR_N(state, x) ((x) ^ ((state)->fpscr.fr << 4))
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#define FR_(state, x) ((state)->floating_point_register.fr[FR_N(state, x)])
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#define FP_N(state, x) ((x) ^ ((state)->fpscr.fr << 3))
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#define FP_(state, x) ((state)->floating_point_register.fp[FP_N(state, x)])
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#define DR2_N(state, x) ((x) ^ ((state)->fpscr.fr << 3))
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#define DR2_(state, x) ((state)->floating_point_register.dr[DR2_N(state, x)])
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#define XD2_N(state, x) ((x) ^ ((!(state)->fpscr.fr) << 3))
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#define XD2_(state, x) ((state)->floating_point_register.dr[XD2_N(state, x)])
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#define FV4_N(state, x) ((x) ^ ((state)->fpscr.fr << 2))
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#define FV4_(state, x) ((state)->floating_point_register.dr[FV4_N(state, x)])
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#define XMTRX_N(state) (!(state)->fpscr.fr)
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#define XMTRX(state) ((state)->floating_point_register.fm[XMTRX_N(state)])
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struct architectural_state {
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uint32_t general_register[24];
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// system_register
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uint32_t mach;
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uint32_t macl;
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uint32_t pr[3];
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uint32_t pc[3];
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union {
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struct fpscr_bits bits;
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uint32_t value;
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} fpscr;
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uint32_t fpul;
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//
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// control_register
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union {
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struct sr_bits bits;
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uint32_t value;
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} sr;
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uint32_t ssr;
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uint32_t spc;
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uint32_t gbr;
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uint32_t vbr;
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uint32_t sgr;
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uint32_t dbr;
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//
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union floating_point_registers floating_point_register;
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bool is_delay_slot;
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};
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//
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