1480 lines
48 KiB
C
1480 lines
48 KiB
C
#include "decode_execute.h"
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#include "impl.h"
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enum decode_status decode_and_execute_instruction(struct architectural_state * state, struct memory_map * map, uint16_t code)
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{
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switch (code & 0b1111000000000000) {
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case 0b0001000000000000: // MOV.L Rm,@(disp,Rn)
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t d = (code >> 0) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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mov_l__store_register_indirect_with_displacement(state, map, m, d, n);
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return DECODE__DEFINED;
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}
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case 0b0101000000000000: // MOV.L @(disp,Rm),Rn
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{
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uint32_t d = (code >> 0) & ((1 << 4) - 1);
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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mov_l__load_register_indirect_with_displacement(state, map, d, m, n);
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return DECODE__DEFINED;
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}
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case 0b0111000000000000: // ADD #imm,Rn
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{
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uint32_t i = (code >> 0) & ((1 << 8) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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add__immediate(state, map, i, n);
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return DECODE__DEFINED;
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}
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case 0b1001000000000000: // MOV.W @(disp,PC),Rn
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{
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uint32_t d = (code >> 0) & ((1 << 8) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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mov_w__pc_relative_with_displacement(state, map, d, n);
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return DECODE__DEFINED;
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}
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case 0b1010000000000000: // BRA label
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{
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uint32_t d = (code >> 0) & ((1 << 12) - 1);
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bra__pc_relative(state, map, d);
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return DECODE__DEFINED;
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}
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case 0b1011000000000000: // BSR label
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{
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uint32_t d = (code >> 0) & ((1 << 12) - 1);
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bsr__pc_relative(state, map, d);
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return DECODE__DEFINED;
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}
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case 0b1101000000000000: // MOV.L @(disp,PC),Rn
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{
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uint32_t d = (code >> 0) & ((1 << 8) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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mov_l__pc_relative_with_displacement(state, map, d, n);
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return DECODE__DEFINED;
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}
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case 0b1110000000000000: // MOV #imm,Rn
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{
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uint32_t i = (code >> 0) & ((1 << 8) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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mov__immediate(state, map, i, n);
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return DECODE__DEFINED;
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}
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}
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switch (code & 0b1111000000001111) {
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case 0b0000000000000100: // MOV.B Rm,@(R0,Rn)
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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mov_b__store_indexed_register_indirect(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0000000000000101: // MOV.W Rm,@(R0,Rn)
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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mov_w__store_indexed_register_indirect(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0000000000000110: // MOV.L Rm,@(R0,Rn)
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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mov_l__store_indexed_register_indirect(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0000000000000111: // MUL.L Rm,Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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mul_l__source_and_destination_operands(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0000000000001100: // MOV.B @(R0,Rm),Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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mov_b__load_indexed_register_indirect(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0000000000001101: // MOV.W @(R0,Rm),Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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mov_w__load_indexed_register_indirect(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0000000000001110: // MOV.L @(R0,Rm),Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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mov_l__load_indexed_register_indirect(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0000000000001111: // MAC.L @Rm+,@Rn+
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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mac_l__multiply_and_accumulate_operation(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0010000000000000: // MOV.B Rm,@Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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mov_b__store_register_direct_data_transfer(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0010000000000001: // MOV.W Rm,@Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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mov_w__store_register_direct_data_transfer(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0010000000000010: // MOV.L Rm,@Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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mov_l__store_register_direct_data_transfer(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0010000000000100: // MOV.B Rm,@-Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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mov_b__store_direct_data_transfer_from_register(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0010000000000101: // MOV.W Rm,@-Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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mov_w__store_direct_data_transfer_from_register(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0010000000000110: // MOV.L Rm,@-Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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mov_l__store_direct_data_transfer_from_register(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0010000000000111: // DIV0S Rm,Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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div0s__source_and_destination_operands(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0010000000001000: // TST Rm,Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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tst__source_and_destination_operands(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0010000000001001: // AND Rm,Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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and__source_and_destination_operands(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0010000000001010: // XOR Rm,Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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xor__source_and_destination_operands(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0010000000001011: // OR Rm,Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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or__source_and_destination_operands(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0010000000001100: // CMP/STR Rm,Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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cmp_str__source_and_destination_operands(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0010000000001101: // XTRCT Rm,Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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xtrct__source_and_destination_operands(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0010000000001110: // MULU.W Rm,Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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mulu_w__source_and_destination_operands(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0010000000001111: // MULS.W Rm,Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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muls_w__source_and_destination_operands(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0011000000000000: // CMP/EQ Rm,Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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cmp_eq__source_and_destination_operands(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0011000000000010: // CMP/HS Rm,Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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cmp_hs__source_and_destination_operands(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0011000000000011: // CMP/GE Rm,Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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cmp_ge__source_and_destination_operands(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0011000000000100: // DIV1 Rm,Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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div1__source_and_destination_operands(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0011000000000101: // DMULU.L Rm,Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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dmulu_l__source_and_destination_operands(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0011000000000110: // CMP/HI Rm,Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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cmp_hi__source_and_destination_operands(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0011000000000111: // CMP/GT Rm,Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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cmp_gt__source_and_destination_operands(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0011000000001000: // SUB Rm,Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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sub__source_and_destination_operands(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0011000000001010: // SUBC Rm,Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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subc__source_and_destination_operands(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0011000000001011: // SUBV Rm,Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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subv__source_and_destination_operands(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0011000000001100: // ADD Rm,Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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add__source_and_destination_operands(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0011000000001101: // DMULS.L Rm,Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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dmuls_l__source_and_destination_operands(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0011000000001110: // ADDC Rm,Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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addc__source_and_destination_operands(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0011000000001111: // ADDV Rm,Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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addv__source_and_destination_operands(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0100000000001100: // SHAD Rm,Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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shad__source_and_destination_operands(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0100000000001101: // SHLD Rm,Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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shld__source_and_destination_operands(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0100000000001111: // MAC.W @Rm+,@Rn+
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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mac_w__multiply_and_accumulate_operation(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0110000000000000: // MOV.B @Rm,Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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mov_b__load_register_direct_data_transfer(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0110000000000001: // MOV.W @Rm,Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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mov_w__load_register_direct_data_transfer(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0110000000000010: // MOV.L @Rm,Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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mov_l__load_register_direct_data_transfer(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0110000000000011: // MOV Rm,Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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mov__source_and_destination_operands(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0110000000000100: // MOV.B @Rm+,Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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mov_b__load_direct_data_transfer_from_register(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0110000000000101: // MOV.W @Rm+,Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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mov_w__load_direct_data_transfer_from_register(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0110000000000110: // MOV.L @Rm+,Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
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uint32_t n = (code >> 8) & ((1 << 4) - 1);
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mov_l__load_direct_data_transfer_from_register(state, map, m, n);
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return DECODE__DEFINED;
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}
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case 0b0110000000000111: // NOT Rm,Rn
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{
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uint32_t m = (code >> 4) & ((1 << 4) - 1);
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
not__source_and_destination_operands(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0110000000001000: // SWAP.B Rm,Rn
|
|
{
|
|
uint32_t m = (code >> 4) & ((1 << 4) - 1);
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
swap_b__source_and_destination_operands(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0110000000001001: // SWAP.W Rm,Rn
|
|
{
|
|
uint32_t m = (code >> 4) & ((1 << 4) - 1);
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
swap_w__source_and_destination_operands(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0110000000001010: // NEGC Rm,Rn
|
|
{
|
|
uint32_t m = (code >> 4) & ((1 << 4) - 1);
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
negc__source_and_destination_operands(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0110000000001011: // NEG Rm,Rn
|
|
{
|
|
uint32_t m = (code >> 4) & ((1 << 4) - 1);
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
neg__source_and_destination_operands(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0110000000001100: // EXTU.B Rm,Rn
|
|
{
|
|
uint32_t m = (code >> 4) & ((1 << 4) - 1);
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
extu_b__source_and_destination_operands(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0110000000001101: // EXTU.W Rm,Rn
|
|
{
|
|
uint32_t m = (code >> 4) & ((1 << 4) - 1);
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
extu_w__source_and_destination_operands(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0110000000001110: // EXTS.B Rm,Rn
|
|
{
|
|
uint32_t m = (code >> 4) & ((1 << 4) - 1);
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
exts_b__source_and_destination_operands(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0110000000001111: // EXTS.W Rm,Rn
|
|
{
|
|
uint32_t m = (code >> 4) & ((1 << 4) - 1);
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
exts_w__source_and_destination_operands(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000000000000: // FADD FRm,FRn
|
|
{
|
|
uint32_t m = (code >> 4) & ((1 << 4) - 1);
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
fadd__source_and_destination_operands(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000000000001: // FSUB FRm,FRn
|
|
{
|
|
uint32_t m = (code >> 4) & ((1 << 4) - 1);
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
fsub__source_and_destination_operands(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000000000010: // FMUL FRm,FRn
|
|
{
|
|
uint32_t m = (code >> 4) & ((1 << 4) - 1);
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
fmul__source_and_destination_operands(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000000000011: // FDIV FRm,FRn
|
|
{
|
|
uint32_t m = (code >> 4) & ((1 << 4) - 1);
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
fdiv__source_and_destination_operands(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000000000100: // FCMP/EQ FRm,FRn
|
|
{
|
|
uint32_t m = (code >> 4) & ((1 << 4) - 1);
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
fcmp_eq__source_and_destination_operands(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000000000101: // FCMP/GT FRm,FRn
|
|
{
|
|
uint32_t m = (code >> 4) & ((1 << 4) - 1);
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
fcmp_gt__source_and_destination_operands(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000000000110: // FMOV.S @(R0,Rm),FRn
|
|
{
|
|
uint32_t m = (code >> 4) & ((1 << 4) - 1);
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
fmov_s__load_indexed_register_indirect(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000000000111: // FMOV.S FRm,@(R0,Rn)
|
|
{
|
|
uint32_t m = (code >> 4) & ((1 << 4) - 1);
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
fmov_s__store_indexed_register_indirect(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000000001000: // FMOV.S @Rm,FRn
|
|
{
|
|
uint32_t m = (code >> 4) & ((1 << 4) - 1);
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
fmov_s__load_register_direct_data_transfer(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000000001001: // FMOV.S @Rm+,FRn
|
|
{
|
|
uint32_t m = (code >> 4) & ((1 << 4) - 1);
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
fmov_s__load_direct_data_transfer_from_register(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000000001010: // FMOV.S FRm,@Rn
|
|
{
|
|
uint32_t m = (code >> 4) & ((1 << 4) - 1);
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
fmov_s__store_register_direct_data_transfer(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000000001011: // FMOV.S FRm,@-Rn
|
|
{
|
|
uint32_t m = (code >> 4) & ((1 << 4) - 1);
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
fmov_s__store_direct_data_transfer_from_register(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000000001100: // FMOV FRm,FRn
|
|
{
|
|
uint32_t m = (code >> 4) & ((1 << 4) - 1);
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
fmov__source_and_destination_operands(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000000001110: // FMAC FR0,FRm,FRn
|
|
{
|
|
uint32_t m = (code >> 4) & ((1 << 4) - 1);
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
fmac__fr0_frm_frn(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
}
|
|
switch (code & 0b1111111100000000) {
|
|
case 0b1000000000000000: // MOV.B R0,@(disp,Rn)
|
|
{
|
|
uint32_t d = (code >> 0) & ((1 << 4) - 1);
|
|
uint32_t n = (code >> 4) & ((1 << 4) - 1);
|
|
mov_b__store_register_indirect_with_displacement(state, map, d, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1000000100000000: // MOV.W R0,@(disp,Rn)
|
|
{
|
|
uint32_t d = (code >> 0) & ((1 << 4) - 1);
|
|
uint32_t n = (code >> 4) & ((1 << 4) - 1);
|
|
mov_w__store_register_indirect_with_displacement(state, map, d, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1000010000000000: // MOV.B @(disp,Rm),R0
|
|
{
|
|
uint32_t d = (code >> 0) & ((1 << 4) - 1);
|
|
uint32_t m = (code >> 4) & ((1 << 4) - 1);
|
|
mov_b__load_register_indirect_with_displacement(state, map, d, m);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1000010100000000: // MOV.W @(disp,Rm),R0
|
|
{
|
|
uint32_t d = (code >> 0) & ((1 << 4) - 1);
|
|
uint32_t m = (code >> 4) & ((1 << 4) - 1);
|
|
mov_w__load_register_indirect_with_displacement(state, map, d, m);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1000100000000000: // CMP/EQ #imm,R0
|
|
{
|
|
uint32_t i = (code >> 0) & ((1 << 8) - 1);
|
|
cmp_eq__immediate(state, map, i);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1000100100000000: // BT label
|
|
{
|
|
uint32_t d = (code >> 0) & ((1 << 8) - 1);
|
|
bt__pc_relative(state, map, d);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1000101100000000: // BF label
|
|
{
|
|
uint32_t d = (code >> 0) & ((1 << 8) - 1);
|
|
bf__pc_relative(state, map, d);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1000110100000000: // BT/S label
|
|
{
|
|
uint32_t d = (code >> 0) & ((1 << 8) - 1);
|
|
bt_s__pc_relative(state, map, d);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1000111100000000: // BF/S label
|
|
{
|
|
uint32_t d = (code >> 0) & ((1 << 8) - 1);
|
|
bf_s__pc_relative(state, map, d);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1100000000000000: // MOV.B R0,@(disp,GBR)
|
|
{
|
|
uint32_t d = (code >> 0) & ((1 << 8) - 1);
|
|
mov_b__store_gbr_indirect_with_displacement(state, map, d);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1100000100000000: // MOV.W R0,@(disp,GBR)
|
|
{
|
|
uint32_t d = (code >> 0) & ((1 << 8) - 1);
|
|
mov_w__store_gbr_indirect_with_displacement(state, map, d);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1100001000000000: // MOV.L R0,@(disp,GBR)
|
|
{
|
|
uint32_t d = (code >> 0) & ((1 << 8) - 1);
|
|
mov_l__store_gbr_indirect_with_displacement(state, map, d);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1100001100000000: // TRAPA #imm
|
|
{
|
|
uint32_t i = (code >> 0) & ((1 << 8) - 1);
|
|
trapa__immediate(state, map, i);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1100010000000000: // MOV.B @(disp,GBR),R0
|
|
{
|
|
uint32_t d = (code >> 0) & ((1 << 8) - 1);
|
|
mov_b__load_gbr_indirect_with_displacement(state, map, d);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1100010100000000: // MOV.W @(disp,GBR),R0
|
|
{
|
|
uint32_t d = (code >> 0) & ((1 << 8) - 1);
|
|
mov_w__load_gbr_indirect_with_displacement(state, map, d);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1100011000000000: // MOV.L @(disp,GBR),R0
|
|
{
|
|
uint32_t d = (code >> 0) & ((1 << 8) - 1);
|
|
mov_l__load_gbr_indirect_with_displacement(state, map, d);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1100011100000000: // MOVA @(disp,PC),R0
|
|
{
|
|
uint32_t d = (code >> 0) & ((1 << 8) - 1);
|
|
mova__pc_relative_with_displacement(state, map, d);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1100100000000000: // TST #imm,R0
|
|
{
|
|
uint32_t i = (code >> 0) & ((1 << 8) - 1);
|
|
tst__immediate(state, map, i);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1100100100000000: // AND #imm,R0
|
|
{
|
|
uint32_t i = (code >> 0) & ((1 << 8) - 1);
|
|
and__immediate(state, map, i);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1100101000000000: // XOR #imm,R0
|
|
{
|
|
uint32_t i = (code >> 0) & ((1 << 8) - 1);
|
|
xor__immediate(state, map, i);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1100101100000000: // OR #imm,R0
|
|
{
|
|
uint32_t i = (code >> 0) & ((1 << 8) - 1);
|
|
or__immediate(state, map, i);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1100110000000000: // TST.B #imm,@(R0,GBR)
|
|
{
|
|
uint32_t i = (code >> 0) & ((1 << 8) - 1);
|
|
tst_b__store_indexed_gbr_indirect(state, map, i);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1100110100000000: // AND.B #imm,@(R0,GBR)
|
|
{
|
|
uint32_t i = (code >> 0) & ((1 << 8) - 1);
|
|
and_b__store_indexed_gbr_indirect(state, map, i);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1100111000000000: // XOR.B #imm,@(R0,GBR)
|
|
{
|
|
uint32_t i = (code >> 0) & ((1 << 8) - 1);
|
|
xor_b__store_indexed_gbr_indirect(state, map, i);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1100111100000000: // OR.B #imm,@(R0,GBR)
|
|
{
|
|
uint32_t i = (code >> 0) & ((1 << 8) - 1);
|
|
or_b__store_indexed_gbr_indirect(state, map, i);
|
|
return DECODE__DEFINED;
|
|
}
|
|
}
|
|
switch (code & 0b1111000011111111) {
|
|
case 0b0000000000000010: // STC SR,Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
stc__transfer_from_sr(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0000000000000011: // BSRF Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
bsrf__destination_operand_only(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0000000000001010: // STS MACH,Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
sts__transfer_from_mach(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0000000000010010: // STC GBR,Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
stc__transfer_from_gbr(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0000000000011010: // STS MACL,Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
sts__transfer_from_macl(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0000000000100010: // STC VBR,Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
stc__transfer_from_vbr(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0000000000100011: // BRAF Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
braf__destination_operand_only(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0000000000101001: // MOVT Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
movt__destination_operand_only(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0000000000101010: // STS PR,Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
sts__transfer_from_pr(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0000000000110010: // STC SSR,Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
stc__transfer_from_ssr(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0000000000111010: // STC SGR,Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
stc__transfer_from_sgr(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0000000001000010: // STC SPC,Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
stc__transfer_from_spc(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0000000001011010: // STS FPUL,Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
sts__transfer_from_fpul(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0000000001101010: // STS FPSCR,Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
sts__transfer_from_fpscr(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0000000011111010: // STC DBR,Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
stc__transfer_from_dbr(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000000000000: // SHLL Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
shll__destination_operand_only(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000000000001: // SHLR Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
shlr__destination_operand_only(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000000000010: // STS.L MACH,@-Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
sts_l__store_from_mach(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000000000011: // STC.L SR,@-Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
stc_l__store_from_sr(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000000000100: // ROTL Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
rotl__destination_operand_only(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000000000101: // ROTR Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
rotr__destination_operand_only(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000000000110: // LDS.L @Rm+,MACH
|
|
{
|
|
uint32_t m = (code >> 8) & ((1 << 4) - 1);
|
|
lds_l__load_to_mach(state, map, m);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000000000111: // LDC.L @Rm+,SR
|
|
{
|
|
uint32_t m = (code >> 8) & ((1 << 4) - 1);
|
|
ldc_l__load_to_sr(state, map, m);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000000001000: // SHLL2 Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
shll2__destination_operand_only(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000000001001: // SHLR2 Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
shlr2__destination_operand_only(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000000001010: // LDS Rm,MACH
|
|
{
|
|
uint32_t m = (code >> 8) & ((1 << 4) - 1);
|
|
lds__transfer_to_mach(state, map, m);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000000001011: // JSR @Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
jsr__destination_operand_only(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000000001110: // LDC Rm,SR
|
|
{
|
|
uint32_t m = (code >> 8) & ((1 << 4) - 1);
|
|
ldc__transfer_to_sr(state, map, m);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000000010000: // DT Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
dt__destination_operand_only(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000000010001: // CMP/PZ Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
cmp_pz__destination_operand_only(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000000010010: // STS.L MACL,@-Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
sts_l__store_from_macl(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000000010011: // STC.L GBR,@-Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
stc_l__store_from_gbr(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000000010101: // CMP/PL Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
cmp_pl__destination_operand_only(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000000010110: // LDS.L @Rm+,MACL
|
|
{
|
|
uint32_t m = (code >> 8) & ((1 << 4) - 1);
|
|
lds_l__load_to_macl(state, map, m);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000000010111: // LDC.L @Rm+,GBR
|
|
{
|
|
uint32_t m = (code >> 8) & ((1 << 4) - 1);
|
|
ldc_l__load_to_gbr(state, map, m);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000000011000: // SHLL8 Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
shll8__destination_operand_only(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000000011001: // SHLR8 Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
shlr8__destination_operand_only(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000000011010: // LDS Rm,MACL
|
|
{
|
|
uint32_t m = (code >> 8) & ((1 << 4) - 1);
|
|
lds__transfer_to_macl(state, map, m);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000000011011: // TAS.B @Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
tas_b__destination_operand_only(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000000011110: // LDC Rm,GBR
|
|
{
|
|
uint32_t m = (code >> 8) & ((1 << 4) - 1);
|
|
ldc__transfer_to_gbr(state, map, m);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000000100000: // SHAL Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
shal__destination_operand_only(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000000100001: // SHAR Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
shar__destination_operand_only(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000000100010: // STS.L PR,@-Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
sts_l__store_from_pr(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000000100011: // STC.L VBR,@-Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
stc_l__store_from_vbr(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000000100100: // ROTCL Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
rotcl__destination_operand_only(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000000100101: // ROTCR Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
rotcr__destination_operand_only(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000000100110: // LDS.L @Rm+,PR
|
|
{
|
|
uint32_t m = (code >> 8) & ((1 << 4) - 1);
|
|
lds_l__load_to_pr(state, map, m);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000000100111: // LDC.L @Rm+,VBR
|
|
{
|
|
uint32_t m = (code >> 8) & ((1 << 4) - 1);
|
|
ldc_l__load_to_vbr(state, map, m);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000000101000: // SHLL16 Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
shll16__destination_operand_only(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000000101001: // SHLR16 Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
shlr16__destination_operand_only(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000000101010: // LDS Rm,PR
|
|
{
|
|
uint32_t m = (code >> 8) & ((1 << 4) - 1);
|
|
lds__transfer_to_pr(state, map, m);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000000101011: // JMP @Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
jmp__destination_operand_only(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000000101110: // LDC Rm,VBR
|
|
{
|
|
uint32_t m = (code >> 8) & ((1 << 4) - 1);
|
|
ldc__transfer_to_vbr(state, map, m);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000000110010: // STC.L SGR,@-Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
stc_l__store_from_sgr(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000000110011: // STC.L SSR,@-Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
stc_l__store_from_ssr(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000000110111: // LDC.L @Rm+,SSR
|
|
{
|
|
uint32_t m = (code >> 8) & ((1 << 4) - 1);
|
|
ldc_l__load_to_ssr(state, map, m);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000000111110: // LDC Rm,SSR
|
|
{
|
|
uint32_t m = (code >> 8) & ((1 << 4) - 1);
|
|
ldc__transfer_to_ssr(state, map, m);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000001000011: // STC.L SPC,@-Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
stc_l__store_from_spc(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000001000111: // LDC.L @Rm+,SPC
|
|
{
|
|
uint32_t m = (code >> 8) & ((1 << 4) - 1);
|
|
ldc_l__load_to_spc(state, map, m);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000001001110: // LDC Rm,SPC
|
|
{
|
|
uint32_t m = (code >> 8) & ((1 << 4) - 1);
|
|
ldc__transfer_to_spc(state, map, m);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000001010010: // STS.L FPUL,@-Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
sts_l__store_from_fpul(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000001010110: // LDS.L @Rm+,FPUL
|
|
{
|
|
uint32_t m = (code >> 8) & ((1 << 4) - 1);
|
|
lds_l__load_to_fpul(state, map, m);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000001011010: // LDS Rm,FPUL
|
|
{
|
|
uint32_t m = (code >> 8) & ((1 << 4) - 1);
|
|
lds__transfer_to_fpul(state, map, m);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000001100010: // STS.L FPSCR,@-Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
sts_l__store_from_fpscr(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000001100110: // LDS.L @Rm+,FPSCR
|
|
{
|
|
uint32_t m = (code >> 8) & ((1 << 4) - 1);
|
|
lds_l__load_to_fpscr(state, map, m);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000001101010: // LDS Rm,FPSCR
|
|
{
|
|
uint32_t m = (code >> 8) & ((1 << 4) - 1);
|
|
lds__transfer_to_fpscr(state, map, m);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000011110010: // STC.L DBR,@-Rn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
stc_l__store_from_dbr(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000011110110: // LDC.L @Rm+,DBR
|
|
{
|
|
uint32_t m = (code >> 8) & ((1 << 4) - 1);
|
|
ldc_l__load_to_dbr(state, map, m);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000011111010: // LDC Rm,DBR
|
|
{
|
|
uint32_t m = (code >> 8) & ((1 << 4) - 1);
|
|
ldc__transfer_to_dbr(state, map, m);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000000001101: // FSTS FPUL,FRn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
fsts__fpul_to_frn(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000000011101: // FLDS FRm,FPUL
|
|
{
|
|
uint32_t m = (code >> 8) & ((1 << 4) - 1);
|
|
flds__frm_to_fpul(state, map, m);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000000101101: // FLOAT FPUL,FRn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
float__fpul_to_frn(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000000111101: // FTRC FRm,FPUL
|
|
{
|
|
uint32_t m = (code >> 8) & ((1 << 4) - 1);
|
|
ftrc__frm_to_fpul(state, map, m);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000001001101: // FNEG FRn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
fneg__destination_operand_only(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000001011101: // FABS FRn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
fabs__destination_operand_only(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000001101101: // FSQRT FRn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
fsqrt__destination_operand_only(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000010001101: // FLDI0 FRn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
fldi0__destination_operand_only(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000010011101: // FLDI1 FRn
|
|
{
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
fldi1__destination_operand_only(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
}
|
|
switch (code & 0b1111111111111111) {
|
|
case 0b0000000000001000: // CLRT
|
|
{
|
|
clrt__no_operand(state, map);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0000000000001001: // NOP
|
|
{
|
|
nop__no_operand(state, map);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0000000000001011: // RTS
|
|
{
|
|
rts__no_operand(state, map);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0000000000011000: // SETT
|
|
{
|
|
sett__no_operand(state, map);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0000000000011001: // DIV0U
|
|
{
|
|
div0u__no_operand(state, map);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0000000000011011: // SLEEP
|
|
{
|
|
sleep__no_operand(state, map);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0000000000101000: // CLRMAC
|
|
{
|
|
clrmac__no_operand(state, map);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0000000000101011: // RTE
|
|
{
|
|
rte__no_operand(state, map);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0000000001001000: // CLRS
|
|
{
|
|
clrs__no_operand(state, map);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0000000001011000: // SETS
|
|
{
|
|
sets__no_operand(state, map);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111001111111101: // FSCHG
|
|
{
|
|
fschg__no_operand(state, map);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111101111111101: // FRCHG
|
|
{
|
|
frchg__no_operand(state, map);
|
|
return DECODE__DEFINED;
|
|
}
|
|
}
|
|
switch (code & 0b1111000010001111) {
|
|
case 0b0000000010000010: // STC Rm_BANK,Rn
|
|
{
|
|
uint32_t m = (code >> 4) & ((1 << 3) - 1);
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
stc__transfer_from_rm_bank(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000010000011: // STC.L Rm_BANK,@-Rn
|
|
{
|
|
uint32_t m = (code >> 4) & ((1 << 3) - 1);
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
stc_l__store_from_rm_bank(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000010000111: // LDC.L @Rm+,Rn_BANK
|
|
{
|
|
uint32_t m = (code >> 8) & ((1 << 4) - 1);
|
|
uint32_t n = (code >> 4) & ((1 << 3) - 1);
|
|
ldc_l__load_to_rn_bank(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b0100000010001110: // LDC Rm,Rn_BANK
|
|
{
|
|
uint32_t m = (code >> 8) & ((1 << 4) - 1);
|
|
uint32_t n = (code >> 4) & ((1 << 3) - 1);
|
|
ldc__transfer_to_rn_bank(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
}
|
|
switch (code & 0b1111000100011111) {
|
|
case 0b1111000000000000: // FADD DRm,DRn
|
|
{
|
|
uint32_t m = (code >> 5) & ((1 << 3) - 1);
|
|
uint32_t n = (code >> 9) & ((1 << 3) - 1);
|
|
fadd__source_and_destination_operands_double(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000000000001: // FSUB DRm,DRn
|
|
{
|
|
uint32_t m = (code >> 5) & ((1 << 3) - 1);
|
|
uint32_t n = (code >> 9) & ((1 << 3) - 1);
|
|
fsub__source_and_destination_operands_double(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000000000010: // FMUL DRm,DRn
|
|
{
|
|
uint32_t m = (code >> 5) & ((1 << 3) - 1);
|
|
uint32_t n = (code >> 9) & ((1 << 3) - 1);
|
|
fmul__source_and_destination_operands_double(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000000000011: // FDIV DRm,DRn
|
|
{
|
|
uint32_t m = (code >> 5) & ((1 << 3) - 1);
|
|
uint32_t n = (code >> 9) & ((1 << 3) - 1);
|
|
fdiv__source_and_destination_operands_double(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000000000100: // FCMP/EQ DRm,DRn
|
|
{
|
|
uint32_t m = (code >> 5) & ((1 << 3) - 1);
|
|
uint32_t n = (code >> 9) & ((1 << 3) - 1);
|
|
fcmp_eq__source_and_destination_operands_double(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000000000101: // FCMP/GT DRm,DRn
|
|
{
|
|
uint32_t m = (code >> 5) & ((1 << 3) - 1);
|
|
uint32_t n = (code >> 9) & ((1 << 3) - 1);
|
|
fcmp_gt__source_and_destination_operands_double(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000000001100: // FMOV DRm,DRn
|
|
{
|
|
uint32_t m = (code >> 5) & ((1 << 3) - 1);
|
|
uint32_t n = (code >> 9) & ((1 << 3) - 1);
|
|
fmov__source_and_destination_operands_double(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000000011100: // FMOV XDm,DRn
|
|
{
|
|
uint32_t m = (code >> 5) & ((1 << 3) - 1);
|
|
uint32_t n = (code >> 9) & ((1 << 3) - 1);
|
|
fmov__bank_to_double(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000100001100: // FMOV DRm,XDn
|
|
{
|
|
uint32_t m = (code >> 5) & ((1 << 3) - 1);
|
|
uint32_t n = (code >> 9) & ((1 << 3) - 1);
|
|
fmov__double_to_bank(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000100011100: // FMOV XDm,XDn
|
|
{
|
|
uint32_t m = (code >> 5) & ((1 << 3) - 1);
|
|
uint32_t n = (code >> 9) & ((1 << 3) - 1);
|
|
fmov__source_and_destination_operands_bank(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
}
|
|
switch (code & 0b1111000100001111) {
|
|
case 0b1111000000000110: // FMOV @(R0,Rm),DRn
|
|
{
|
|
uint32_t m = (code >> 4) & ((1 << 4) - 1);
|
|
uint32_t n = (code >> 9) & ((1 << 3) - 1);
|
|
fmov__load_indexed_register_indirect_double(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000000001000: // FMOV @Rm,DRn
|
|
{
|
|
uint32_t m = (code >> 4) & ((1 << 4) - 1);
|
|
uint32_t n = (code >> 9) & ((1 << 3) - 1);
|
|
fmov__load_register_direct_data_transfer_double(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000000001001: // FMOV @Rm+,DRn
|
|
{
|
|
uint32_t m = (code >> 4) & ((1 << 4) - 1);
|
|
uint32_t n = (code >> 9) & ((1 << 3) - 1);
|
|
fmov__load_direct_data_transfer_from_register_double(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000100000110: // FMOV @(R0,Rm),XDn
|
|
{
|
|
uint32_t m = (code >> 4) & ((1 << 4) - 1);
|
|
uint32_t n = (code >> 9) & ((1 << 3) - 1);
|
|
fmov__load_indexed_register_indirect_bank(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000100001000: // FMOV @Rm,XDn
|
|
{
|
|
uint32_t m = (code >> 4) & ((1 << 4) - 1);
|
|
uint32_t n = (code >> 9) & ((1 << 3) - 1);
|
|
fmov__load_register_direct_data_transfer_bank(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000100001001: // FMOV @Rm+,XDn
|
|
{
|
|
uint32_t m = (code >> 4) & ((1 << 4) - 1);
|
|
uint32_t n = (code >> 9) & ((1 << 3) - 1);
|
|
fmov__load_direct_data_transfer_from_register_bank(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
}
|
|
switch (code & 0b1111000000011111) {
|
|
case 0b1111000000000111: // FMOV DRm,@(R0,Rn)
|
|
{
|
|
uint32_t m = (code >> 5) & ((1 << 3) - 1);
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
fmov__store_indexed_register_indirect_double(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000000001010: // FMOV DRm,@Rn
|
|
{
|
|
uint32_t m = (code >> 5) & ((1 << 3) - 1);
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
fmov__store_register_direct_data_transfer_double(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000000001011: // FMOV DRm,@-Rn
|
|
{
|
|
uint32_t m = (code >> 5) & ((1 << 3) - 1);
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
fmov__store_direct_data_transfer_from_register_double(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000000010111: // FMOV XDm,@(R0,Rn)
|
|
{
|
|
uint32_t m = (code >> 5) & ((1 << 3) - 1);
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
fmov__store_indexed_register_indirect_bank(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000000011010: // FMOV XDm,@Rn
|
|
{
|
|
uint32_t m = (code >> 5) & ((1 << 3) - 1);
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
fmov__store_register_direct_data_transfer_bank(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000000011011: // FMOV XDm,@-Rn
|
|
{
|
|
uint32_t m = (code >> 5) & ((1 << 3) - 1);
|
|
uint32_t n = (code >> 8) & ((1 << 4) - 1);
|
|
fmov__store_direct_data_transfer_from_register_bank(state, map, m, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
}
|
|
switch (code & 0b1111000111111111) {
|
|
case 0b1111000000101101: // FLOAT FPUL,DRn
|
|
{
|
|
uint32_t n = (code >> 9) & ((1 << 3) - 1);
|
|
float__fpul_to_drn(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000000111101: // FTRC DRm,FPUL
|
|
{
|
|
uint32_t m = (code >> 9) & ((1 << 3) - 1);
|
|
ftrc__drm_to_fpul(state, map, m);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000001001101: // FNEG DRn
|
|
{
|
|
uint32_t n = (code >> 9) & ((1 << 3) - 1);
|
|
fneg__destination_operand_only_double(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000001011101: // FABS DRn
|
|
{
|
|
uint32_t n = (code >> 9) & ((1 << 3) - 1);
|
|
fabs__destination_operand_only_double(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000001101101: // FSQRT DRn
|
|
{
|
|
uint32_t n = (code >> 9) & ((1 << 3) - 1);
|
|
fsqrt__destination_operand_only_double(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000010101101: // FCNVSD FPUL,DRn
|
|
{
|
|
uint32_t n = (code >> 9) & ((1 << 3) - 1);
|
|
fcnvsd__fpul_to_drn(state, map, n);
|
|
return DECODE__DEFINED;
|
|
}
|
|
case 0b1111000010111101: // FCNVDS DRm,FPUL
|
|
{
|
|
uint32_t m = (code >> 9) & ((1 << 3) - 1);
|
|
fcnvds__drm_to_fpul(state, map, m);
|
|
return DECODE__DEFINED;
|
|
}
|
|
}
|
|
return DECODE__UNDEFINED;
|
|
}
|