mode_name = {
    '': 'no_operand',
    'Rn': 'destination_operand_only',
    'Rm': 'destination_operand_only',
    'Rm,Rn': 'source_and_destination_operands',
    'Rm,SR': 'transfer_to_sr',
    'Rm,SSR': 'transfer_to_ssr',
    'Rm,SPC': 'transfer_to_spc',
    'Rm,GBR': 'transfer_to_gbr',
    'Rm,VBR': 'transfer_to_vbr',
    'Rm,DBR': 'transfer_to_dbr',
    'Rm,MACH': 'transfer_to_mach',
    'Rm,MACL': 'transfer_to_macl',
    'Rm,Rn_BANK': 'transfer_to_rn_bank',
    'Rm,PR': 'transfer_to_pr',
    'SR,Rn': 'transfer_from_sr',
    'SSR,Rn': 'transfer_from_ssr',
    'SPC,Rn': 'transfer_from_spc',
    'GBR,Rn': 'transfer_from_gbr',
    'VBR,Rn': 'transfer_from_vbr',
    'DBR,Rn': 'transfer_from_dbr',
    'SGR,Rn': 'transfer_from_sgr',
    'MACH,Rn': 'transfer_from_mach',
    'MACL,Rn': 'transfer_from_macl',
    'Rm_BANK,Rn': 'transfer_from_rm_bank',
    'PR,Rn': 'transfer_from_pr',
    '@Rn': 'destination_operand_only',
    'Rm,@Rn': 'store_register_direct_data_transfer',
    'R0,@Rn': 'r0_store_register_direct_data_transfer',
    '@Rm,Rn': 'load_register_direct_data_transfer',
    '@Rm+,@Rn+': 'multiply_and_accumulate_operation',
    '@Rm+,Rn': 'load_direct_data_transfer_from_register',
    '@Rm+,SR': 'load_to_sr',
    '@Rm+,SSR': 'load_to_ssr',
    '@Rm+,SPC': 'load_to_spc',
    '@Rm+,GBR': 'load_to_gbr',
    '@Rm+,VBR': 'load_to_vbr',
    '@Rm+,DBR': 'load_to_dbr',
    '@Rm+,MACH': 'load_to_mach',
    '@Rm+,MACL': 'load_to_macl',
    '@Rm+,Rn_BANK': 'load_to_rn_bank',
    '@Rm+,PR': 'load_to_pr',
    'Rm,@-Rn': 'store_direct_data_transfer_from_register',
    'SR,@-Rn': 'store_from_sr',
    'SSR,@-Rn': 'store_from_ssr',
    'SPC,@-Rn': 'store_from_spc',
    'GBR,@-Rn': 'store_from_gbr',
    'VBR,@-Rn': 'store_from_vbr',
    'DBR,@-Rn': 'store_from_dbr',
    'SGR,@-Rn': 'store_from_sgr',
    'MACH,@-Rn': 'store_from_mach',
    'MACL,@-Rn': 'store_from_macl',
    'Rm_BANK,@-Rn': 'store_from_rm_bank',
    'PR,@-Rn': 'store_from_pr',
    'R0,@(disp,Rn)': 'store_register_indirect_with_displacement',
    'Rm,@(disp,Rn)': 'store_register_indirect_with_displacement',
    '@(disp,Rm),R0': 'load_register_indirect_with_displacement',
    '@(disp,Rm),Rn': 'load_register_indirect_with_displacement',
    'Rm,@(R0,Rn)': 'store_indexed_register_indirect',
    '@(R0,Rm),Rn': 'load_indexed_register_indirect',
    'R0,@(disp,GBR)': 'store_gbr_indirect_with_displacement',
    '@(disp,GBR),R0': 'load_gbr_indirect_with_displacement',
    '#imm,@(R0,GBR)': 'store_indexed_gbr_indirect',
    '@(R0,GBR),#imm': 'load_indexed_gbr_indirect',
    '@(disp,PC),Rn': 'pc_relative_with_displacement',
    '@(disp,PC),R0': 'pc_relative_with_displacement',
    'label': 'pc_relative',
    '#imm,Rn': 'immediate',
    '#imm,R0': 'immediate',
    '#imm': 'immediate',
    # floating point
    'FRn': 'destination_operand_only',
    'DRn': 'destination_operand_only_double',
    'FRm,FRn': 'source_and_destination_operands',
    'DRm,DRn': 'source_and_destination_operands_double',
    'XDm,XDn': 'source_and_destination_operands_bank',
    'DRm,XDn': 'double_to_bank',
    'XDm,DRn': 'bank_to_double',
    '@Rm,FRn': 'load_register_direct_data_transfer',
    '@Rm,DRn': 'load_register_direct_data_transfer_double',
    '@Rm,XDn': 'load_register_direct_data_transfer_bank',
    '@(R0,Rm),FRn': 'load_indexed_register_indirect',
    '@(R0,Rm),DRn': 'load_indexed_register_indirect_double',
    '@(R0,Rm),XDn': 'load_indexed_register_indirect_bank',
    '@Rm+,FRn': 'load_direct_data_transfer_from_register',
    '@Rm+,DRn': 'load_direct_data_transfer_from_register_double',
    '@Rm+,XDn': 'load_direct_data_transfer_from_register_bank',
    'FRm,@Rn': 'store_register_direct_data_transfer',
    'DRm,@Rn': 'store_register_direct_data_transfer_double',
    'XDm,@Rn': 'store_register_direct_data_transfer_bank',
    'FRm,@-Rn': 'store_direct_data_transfer_from_register',
    'DRm,@-Rn': 'store_direct_data_transfer_from_register_double',
    'XDm,@-Rn': 'store_direct_data_transfer_from_register_bank',
    'FRm,@(R0,Rn)': 'store_indexed_register_indirect',
    'DRm,@(R0,Rn)': 'store_indexed_register_indirect_double',
    'XDm,@(R0,Rn)': 'store_indexed_register_indirect_bank',
    'FRm,FPUL': 'frm_to_fpul',
    'DRm,FPUL': 'drm_to_fpul',
    'FPUL,FRn': 'fpul_to_frn',
    'FPUL,DRn': 'fpul_to_drn',
    'FR0,FRm,FRn': 'fr0_frm_frn',
    'Rm,FPSCR': 'transfer_to_fpscr',
    'Rm,FPUL': 'transfer_to_fpul',
    '@Rm+,FPSCR': 'load_to_fpscr',
    '@Rm+,FPUL': 'load_to_fpul',
    'FPSCR,Rn': 'transfer_from_fpscr',
    'FPUL,Rn': 'transfer_from_fpul',
    'FPUL,@-Rn': 'store_from_fpul',
    'FPSCR,@-Rn': 'store_from_fpscr',
    'FVm,FVn': 'fvm_fvn',
    'XMTRX,FVn': 'xmtrx_fvn',
}

def instruction_function_name(ins):
    name = ins.instruction.replace('.', '_').replace('/', '_').lower()
    assert ins.operands in mode_name, (ins.instruction, ins.operands)
    mode = mode_name[ins.operands]
    return '__'.join([name, mode])